source: rtems-docs/cpu-supplement/lattice_micro32.rst @ 633a24f

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4Lattice Mico32 Specific Information
5***********************************
6
7This chaper discusses the Lattice Mico32 architecture dependencies in this port
8of RTEMS. The Lattice Mico32 is a 32-bit Harvard, RISC architecture "soft"
9microprocessor, available for free with an open IP core licensing
10agreement. Although mainly targeted for Lattice FPGA devices the microprocessor
11can be implemented on other vendors' FPGAs, too.
12
13**Architecture Documents**
14
15For information on the Lattice Mico32 architecture, refer to the following
16documents available from Lattice Semiconductor http://www.latticesemi.com/.
17
18- *"LatticeMico32 Processor Reference Manual"*
19  http://www.latticesemi.com/dynamic/view_document.cfm?document_id=20890
20
21CPU Model Dependent Features
22============================
23
24The Lattice Mico32 architecture allows for different configurations of the
25processor. This port is based on the assumption that the following options are
26implemented:
27
28- hardware multiplier
29
30- hardware divider
31
32- hardware barrel shifter
33
34- sign extension instructions
35
36- instruction cache
37
38- data cache
39
40- debug
41
42Register Architecture
43=====================
44
45This section gives a brief introduction to the register architecture of the
46Lattice Mico32 processor.
47
48The Lattice Mico32 is a RISC archictecture processor with a 32-register file of
4932-bit registers.
50
51Register Name
52
53Function
54
55r0
56
57holds value zero
58
59r1-r25
60
61general purpose
62
63r26/gp
64
65general pupose / global pointer
66
67r27/fp
68
69general pupose / frame pointer
70
71r28/sp
72
73stack pointer
74
75r29/ra
76
77return address
78
79r30/ea
80
81exception address
82
83r31/ba
84
85breakpoint address
86
87Note that on processor startup all register values are undefined including r0,
88thus r0 has to be initialized to zero.
89
90Calling Conventions
91===================
92
93Calling Mechanism
94-----------------
95
96A call instruction places the return address to register r29 and a return from
97subroutine (ret) is actually a branch to r29/ra.
98
99Register Usage
100--------------
101
102A subroutine may freely use registers r1 to r10 which are *not* preserved
103across subroutine invocations.
104
105Parameter Passing
106-----------------
107
108When calling a C function the first eight arguments are stored in registers r1
109to r8. Registers r1 and r2 hold the return value.
110
111Memory Model
112============
113
114The Lattice Mico32 processor supports a flat memory model with a 4 Gbyte
115address space with 32-bit addresses.
116
117The following data types are supported:
118
119================== ==== ======================
120Type               Bits C Compiler Type
121================== ==== ======================
122unsigned byte      8    unsigned char
123signed byte        8    char
124unsigned half-word 16   unsigned short
125signed half-word   16   short
126unsigned word      32   unsigned int / unsigned long
127signed word        32   int / long
128================== ==== ======================
129
130Data accesses need to be aligned, with unaligned accesses result are undefined.
131
132Interrupt Processing
133====================
134
135The Lattice Mico32 has 32 interrupt lines which are however served by only one
136exception vector. When an interrupt occurs following happens:
137
138- address of next instruction placed in r30/ea
139
140- IE field of IE CSR saved to EIE field and IE field cleared preventing further
141  exceptions from occuring.
142
143- branch to interrupt exception address EBA CSR + 0xC0
144
145The interrupt exception handler determines from the state of the interrupt
146pending registers (IP CSR) and interrupt enable register (IE CSR) which
147interrupt to serve and jumps to the interrupt routine pointed to by the
148corresponding interrupt vector.
149
150For now there is no dedicated interrupt stack so every task in the system MUST
151have enough stack space to accommodate the worst case stack usage of that
152particular task and the interrupt service routines COMBINED.
153
154Nested interrupts are not supported.
155
156Default Fatal Error Processing
157==============================
158
159Upon detection of a fatal error by either the application or RTEMS during
160initialization the ``rtems_fatal_error_occurred`` directive supplied by the
161Fatal Error Manager is invoked.  The Fatal Error Manager will invoke the
162user-supplied fatal error handlers.  If no user-supplied handlers are
163configured or all of them return without taking action to shutdown the
164processor or reset, a default fatal error handler is invoked.
165
166Most of the action performed as part of processing the fatal error are
167described in detail in the Fatal Error Manager chapter in the User's Guide.
168However, the if no user provided extension or BSP specific fatal error handler
169takes action, the final default action is to invoke a CPU architecture specific
170function.  Typically this function disables interrupts and halts the processor.
171
172In each of the architecture specific chapters, this describes the precise
173operations of the default CPU specific fatal error handler.
174
175Symmetric Multiprocessing
176=========================
177
178SMP is not supported.
179
180Thread-Local Storage
181====================
182
183Thread-local storage is not implemented.
184
185Board Support Packages
186======================
187
188There are no Lattice Micro32 specific notes on BSPs.
189
190System Reset
191------------
192
193An RTEMS based application is initiated or re-initiated when the processor is
194reset.
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