1 | .. comment SPDX-License-Identifier: CC-BY-SA-4.0 |
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2 | |
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3 | .. COMMENT: COPYRIGHT (c) 1988-2002. |
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4 | .. COMMENT: On-Line Applications Research Corporation (OAR). |
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5 | .. COMMENT: All rights reserved. |
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6 | .. COMMENT: Jukka Pietarinen <jukka.pietarinen@mrf.fi>, 2008, |
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7 | .. COMMENT: Micro-Research Finland Oy |
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8 | |
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9 | Intel/AMD x86 Specific Information |
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10 | ********************************** |
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11 | |
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12 | This chapter discusses the Intel x86 architecture dependencies in this port of |
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13 | RTEMS. This family has multiple implementations from multiple vendors and |
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14 | suffers more from having evolved rather than being designed for growth. |
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15 | |
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16 | For information on the i386 processor, refer to the following documents: |
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17 | |
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18 | - *386 Programmer's Reference Manual, Intel, Order No. 230985-002*. |
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19 | |
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20 | - *386 Microprocessor Hardware Reference Manual, Intel, |
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21 | Order No. 231732-003*. |
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22 | |
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23 | - *80386 System Software Writer's Guide, Intel, Order No. 231499-001*. |
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24 | |
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25 | - *80387 Programmer's Reference Manual, Intel, Order No. 231917-001*. |
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26 | |
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27 | CPU Model Dependent Features |
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28 | ============================ |
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29 | |
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30 | This section presents the set of features which vary across i386 |
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31 | implementations and are of importance to RTEMS. The set of CPU model feature |
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32 | macros are defined in the :file:`cpukit/score/cpu/i386/i386.h` based upon the |
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33 | particular CPU model specified on the compilation command line. |
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34 | |
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35 | bswap Instruction |
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36 | ----------------- |
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37 | |
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38 | The macro ``I386_HAS_BSWAP`` is set to 1 to indicate that this CPU model has |
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39 | the ``bswap`` instruction which endian swaps a thirty-two bit quantity. This |
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40 | instruction appears to be present in all CPU models i486's and above. |
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41 | |
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42 | Calling Conventions |
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43 | =================== |
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44 | |
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45 | Processor Background |
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46 | -------------------- |
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47 | |
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48 | The i386 architecture supports a simple yet effective call and return |
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49 | mechanism. A subroutine is invoked via the call (``call``) instruction. This |
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50 | instruction pushes the return address on the stack. The return from subroutine |
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51 | (``ret``) instruction pops the return address off the current stack and |
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52 | transfers control to that instruction. It is is important to note that the |
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53 | i386 call and return mechanism does not automatically save or restore any |
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54 | registers. It is the responsibility of the high-level language compiler to |
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55 | define the register preservation and usage convention. |
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56 | |
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57 | Calling Mechanism |
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58 | ----------------- |
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59 | |
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60 | All RTEMS directives are invoked using a call instruction and return to the |
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61 | user application via the ret instruction. |
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62 | |
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63 | Register Usage |
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64 | -------------- |
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65 | |
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66 | As discussed above, the call instruction does not automatically save any |
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67 | registers. RTEMS uses the registers EAX, ECX, and EDX as scratch registers. |
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68 | These registers are not preserved by RTEMS directives therefore, the contents |
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69 | of these registers should not be assumed upon return from any RTEMS directive. |
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70 | |
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71 | Parameter Passing |
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72 | ----------------- |
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73 | |
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74 | RTEMS assumes that arguments are placed on the current stack before the |
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75 | directive is invoked via the call instruction. The first argument is assumed |
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76 | to be closest to the return address on the stack. This means that the first |
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77 | argument of the C calling sequence is pushed last. The following pseudo-code |
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78 | illustrates the typical sequence used to call a RTEMS directive with three (3) |
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79 | arguments: |
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80 | |
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81 | .. code-block:: c |
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82 | |
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83 | push third argument |
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84 | push second argument |
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85 | push first argument |
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86 | invoke directive |
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87 | remove arguments from the stack |
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88 | |
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89 | The arguments to RTEMS are typically pushed onto the stack using a push |
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90 | instruction. These arguments must be removed from the stack after control is |
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91 | returned to the caller. This removal is typically accomplished by adding the |
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92 | size of the argument list in bytes to the stack pointer. |
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93 | |
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94 | Memory Model |
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95 | ============ |
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96 | |
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97 | Flat Memory Model |
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98 | ----------------- |
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99 | |
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100 | RTEMS supports the i386 protected mode, flat memory model with paging disabled. |
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101 | In this mode, the i386 automatically converts every address from a logical to a |
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102 | physical address each time it is used. The i386 uses information provided in |
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103 | the segment registers and the Global Descriptor Table to convert these |
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104 | addresses. RTEMS assumes the existence of the following segments: |
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105 | |
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106 | - a single code segment at protection level (0) which contains all application |
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107 | and executive code. |
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108 | |
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109 | - a single data segment at protection level zero (0) which contains all |
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110 | application and executive data. |
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111 | |
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112 | The i386 segment registers and associated selectors must be initialized when |
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113 | the initialize_executive directive is invoked. RTEMS treats the segment |
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114 | registers as system registers and does not modify or context switch them. |
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115 | |
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116 | This i386 memory model supports a flat 32-bit address space with addresses |
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117 | ranging from 0x00000000 to 0xFFFFFFFF (4 gigabytes). Each address is |
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118 | represented by a 32-bit value and is byte addressable. The address may be used |
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119 | to reference a single byte, half-word (2-bytes), or word (4 bytes). |
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120 | |
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121 | Interrupt Processing |
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122 | ==================== |
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123 | |
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124 | Although RTEMS hides many of the processor dependent details of interrupt |
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125 | processing, it is important to understand how the RTEMS interrupt manager is |
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126 | mapped onto the processor's unique architecture. Discussed in this chapter are |
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127 | the the processor's response and control mechanisms as they pertain to RTEMS. |
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128 | |
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129 | Vectoring of Interrupt Handler |
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130 | ------------------------------ |
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131 | |
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132 | Although the i386 supports multiple privilege levels, RTEMS and all user |
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133 | software executes at privilege level 0. This decision was made by the RTEMS |
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134 | designers to enhance compatibility with processors which do not provide |
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135 | sophisticated protection facilities like those of the i386. This decision |
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136 | greatly simplifies the discussion of i386 processing, as one need only consider |
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137 | interrupts without privilege transitions. |
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138 | |
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139 | Upon receipt of an interrupt the i386 automatically performs the following |
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140 | actions: |
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141 | |
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142 | - pushes the EFLAGS register |
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143 | |
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144 | - pushes the far address of the interrupted instruction |
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145 | |
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146 | - vectors to the interrupt service routine (ISR). |
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147 | |
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148 | A nested interrupt is processed similarly by the i386. |
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149 | |
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150 | Interrupt Stack Frame |
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151 | --------------------- |
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152 | |
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153 | The structure of the Interrupt Stack Frame for the i386 which is placed on the |
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154 | interrupt stack by the processor in response to an interrupt is as follows: |
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155 | |
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156 | +----------------------+-------+ |
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157 | | Old EFLAGS Register | ESP+8 | |
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158 | +----------+-----------+-------+ |
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159 | | UNUSED | Old CS | ESP+4 | |
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160 | +----------+-----------+-------+ |
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161 | | Old EIP | ESP | |
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162 | +----------------------+-------+ |
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163 | |
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164 | |
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165 | Interrupt Levels |
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166 | ---------------- |
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167 | |
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168 | Although RTEMS supports 256 interrupt levels, the i386 only supports two - |
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169 | enabled and disabled. Interrupts are enabled when the interrupt-enable flag |
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170 | (IF) in the extended flags (EFLAGS) is set. Conversely, interrupt processing |
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171 | is inhibited when the IF is cleared. During a non-maskable interrupt, all |
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172 | other interrupts, including other non-maskable ones, are inhibited. |
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173 | |
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174 | RTEMS interrupt levels 0 and 1 such that level zero |
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175 | (0) indicates that interrupts are fully enabled and level one that interrupts |
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176 | are disabled. All other RTEMS interrupt levels are undefined and their |
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177 | behavior is unpredictable. |
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178 | |
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179 | Interrupt Stack |
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180 | --------------- |
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181 | |
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182 | The i386 family does not support a dedicated hardware interrupt stack. On this |
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183 | processor, RTEMS allocates and manages a dedicated interrupt stack. As part of |
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184 | vectoring a non-nested interrupt service routine, RTEMS switches from the stack |
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185 | of the interrupted task to a dedicated interrupt stack. When a non-nested |
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186 | interrupt returns, RTEMS switches back to the stack of the interrupted stack. |
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187 | The current stack pointer is not altered by RTEMS on nested interrupt. |
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188 | |
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189 | Default Fatal Error Processing |
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190 | ============================== |
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191 | |
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192 | The default fatal error handler for this architecture disables processor |
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193 | interrupts, places the error code in EAX, and executes a HLT instruction to |
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194 | halt the processor. |
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195 | |
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196 | Symmetric Multiprocessing |
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197 | ========================= |
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198 | |
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199 | SMP is not supported. |
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200 | |
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201 | Thread-Local Storage |
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202 | ==================== |
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203 | |
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204 | Thread-local storage is supported. |
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205 | |
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206 | Board Support Packages |
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207 | ====================== |
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208 | |
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209 | System Reset |
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210 | ------------ |
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211 | |
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212 | An RTEMS based application is initiated when the i386 processor is reset. When |
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213 | the i386 is reset, |
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214 | |
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215 | - The EAX register is set to indicate the results of the processor's power-up |
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216 | self test. If the self-test was not executed, the contents of this register |
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217 | are undefined. Otherwise, a non-zero value indicates the processor is faulty |
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218 | and a zero value indicates a successful self-test. |
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219 | |
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220 | - The DX register holds a component identifier and revision level. DH contains |
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221 | 3 to indicate an i386 component and DL contains a unique revision level |
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222 | indicator. |
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223 | |
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224 | - Control register zero (CR0) is set such that the processor is in real mode |
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225 | with paging disabled. Other portions of CR0 are used to indicate the |
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226 | presence of a numeric coprocessor. |
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227 | |
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228 | - All bits in the extended flags register (EFLAG) which are not permanently set |
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229 | are cleared. This inhibits all maskable interrupts. |
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230 | |
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231 | - The Interrupt Descriptor Register (IDTR) is set to point at address zero. |
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232 | |
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233 | - All segment registers are set to zero. |
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234 | |
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235 | - The instruction pointer is set to 0x0000FFF0. The first instruction executed |
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236 | after a reset is actually at 0xFFFFFFF0 because the i386 asserts the upper |
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237 | twelve address until the first intersegment (FAR) JMP or CALL instruction. |
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238 | When a JMP or CALL is executed, the upper twelve address lines are lowered |
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239 | and the processor begins executing in the first megabyte of memory. |
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240 | |
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241 | Typically, an intersegment JMP to the application's initialization code is |
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242 | placed at address 0xFFFFFFF0. |
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243 | |
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244 | Processor Initialization |
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245 | ------------------------ |
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246 | |
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247 | This initialization code is responsible for initializing all data structures |
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248 | required by the i386 in protected mode and for actually entering protected |
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249 | mode. The i386 must be placed in protected mode and the segment registers and |
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250 | associated selectors must be initialized before the initialize_executive |
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251 | directive is invoked. |
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252 | |
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253 | The initialization code is responsible for initializing the Global Descriptor |
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254 | Table such that the i386 is in the thirty-two bit flat memory model with paging |
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255 | disabled. In this mode, the i386 automatically converts every address from a |
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256 | logical to a physical address each time it is used. For more information on |
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257 | the memory model used by RTEMS, please refer to the Memory Model chapter in |
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258 | this document. |
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259 | |
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260 | Since the processor is in real mode upon reset, the processor must be switched |
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261 | to protected mode before RTEMS can execute. Before switching to protected |
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262 | mode, at least one descriptor table and two descriptors must be created. |
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263 | Descriptors are needed for a code segment and a data segment. ( This will give |
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264 | you the flat memory model.) The stack can be placed in a normal read/write |
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265 | data segment, so no descriptor for the stack is needed. Before the GDT can be |
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266 | used, the base address and limit must be loaded into the GDTR register using an |
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267 | LGDT instruction. |
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268 | |
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269 | If the hardware allows an NMI to be generated, you need to create the IDT and a |
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270 | gate for the NMI interrupt handler. Before the IDT can be used, the base |
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271 | address and limit for the idt must be loaded into the IDTR register using an |
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272 | LIDT instruction. |
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273 | |
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274 | Protected mode is entered by setting thye PE bit in the CR0 register. Either a |
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275 | LMSW or MOV CR0 instruction may be used to set this bit. Because the processor |
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276 | overlaps the interpretation of several instructions, it is necessary to discard |
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277 | the instructions from the read-ahead cache. A JMP instruction immediately after |
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278 | the LMSW changes the flow and empties the processor if intructions which have |
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279 | been pre-fetched and/or decoded. At this point, the processor is in protected |
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280 | mode and begins to perform protected mode application initialization. |
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281 | |
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282 | If the application requires that the IDTR be some value besides zero, then it |
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283 | should set it to the required value at this point. All tasks share the same |
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284 | i386 IDTR value. Because interrupts are enabled automatically by RTEMS as part |
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285 | of the initialize_executive directive, the IDTR MUST be set properly before |
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286 | this directive is invoked to insure correct interrupt vectoring. If processor |
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287 | caching is to be utilized, then it should be enabled during the reset |
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288 | application initialization code. The reset code which is executed before the |
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289 | call to initialize_executive has the following requirements: |
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290 | |
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291 | For more information regarding the i386 data structures and their contents, |
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292 | refer to Intel's 386 Programmer's Reference Manual. |
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