source: rtems-docs/cpu-supplement/epiphany.rst @ 0e46b34

5
Last change on this file since 0e46b34 was 0e46b34, checked in by Sebastian Huber <sebastian.huber@…>, on 02/07/19 at 12:06:26

cpu-supplement: Fix file name

  • Property mode set to 100644
File size: 2.1 KB
Line 
1.. SPDX-License-Identifier: CC-BY-SA-4.0
2
3.. Copyright (C) 1988, 2002 On-Line Applications Research Corporation (OAR)
4
5Epiphany Specific Information
6*****************************
7
8This chapter discusses the`Epiphany Architecture
9http://adapteva.com/docs/epiphany_sdk_ref.pdf dependencies in this port of
10RTEMS. Epiphany is a chip that can come with 16 and 64 cores, each of which can
11run RTEMS separately or they can work together to run a SMP RTEMS application.
12
13**Architecture Documents**
14
15For information on the Epiphany architecture refer to the *Epiphany
16Architecture Reference* http://adapteva.com/docs/epiphany_arch_ref.pdf.
17
18Calling Conventions
19===================
20
21Please refer to the *Epiphany SDK*
22http://adapteva.com/docs/epiphany_sdk_ref.pdf Appendix A: Application Binary
23Interface
24
25Floating Point Unit
26-------------------
27
28A floating point unit is currently not supported.
29
30Memory Model
31============
32
33A flat 32-bit memory model is supported, no caches. Each core has its own 32
34KiB strictly ordered local memory along with an access to a shared 32 MiB
35external DRAM.
36
37Interrupt Processing
38====================
39
40Every Epiphany core has 10 exception types:
41
42- Reset
43
44- Software Exception
45
46- Data Page Fault
47
48- Timer 0
49
50- Timer 1
51
52- Message Interrupt
53
54- DMA0 Interrupt
55
56- DMA1 Interrupt
57
58- WANT Interrupt
59
60- User Interrupt
61
62Interrupt Levels
63----------------
64
65There are only two levels: interrupts enabled and interrupts disabled.
66
67Interrupt Stack
68---------------
69
70The Epiphany RTEMS port uses a dedicated software interrupt stack.  The stack
71for interrupts is allocated during interrupt driver initialization.  When an
72interrupt is entered, the _ISR_Handler routine is responsible for switching
73from the interrupted task stack to RTEMS software interrupt stack.
74
75Default Fatal Error Processing
76==============================
77
78The default fatal error handler for this architecture performs the following
79actions:
80
81- disables operating system supported interrupts (IRQ),
82
83- places the error code in ``r0``, and
84
85- executes an infinite loop to simulate a halt processor instruction.
86
87Symmetric Multiprocessing
88=========================
89
90SMP is not supported.
Note: See TracBrowser for help on using the repository browser.