source: rtems-docs/cpu-supplement/ephiphany.rst @ 67195aa

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Last change on this file since 67195aa was 6916004, checked in by Chris Johns <chrisj@…>, on Nov 9, 2016 at 1:39:16 AM

cpu-supplement: Fix header levels.

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[489740f]1.. comment SPDX-License-Identifier: CC-BY-SA-4.0
2
[f233256]3.. COMMENT: COPYRIGHT (c) 1988-2002.
4.. COMMENT: On-Line Applications Research Corporation (OAR).
5.. COMMENT: All rights reserved.
6
[d755cbd]7Epiphany Specific Information
[6916004]8*****************************
[d755cbd]9
[f233256]10This chapter discusses the`Epiphany Architecture
11http://adapteva.com/docs/epiphany_sdk_ref.pdf dependencies in this port of
12RTEMS. Epiphany is a chip that can come with 16 and 64 cores, each of which can
13run RTEMS separately or they can work together to run a SMP RTEMS application.
[d755cbd]14
15**Architecture Documents**
16
[f233256]17For information on the Epiphany architecture refer to the *Epiphany
18Architecture Reference* http://adapteva.com/docs/epiphany_arch_ref.pdf.
[d755cbd]19
20Calling Conventions
21===================
22
[f233256]23Please refer to the *Epiphany SDK*
24http://adapteva.com/docs/epiphany_sdk_ref.pdf Appendix A: Application Binary
25Interface
[d755cbd]26
27Floating Point Unit
28-------------------
29
30A floating point unit is currently not supported.
31
32Memory Model
33============
34
[f233256]35A flat 32-bit memory model is supported, no caches. Each core has its own 32
36KiB strictly ordered local memory along with an access to a shared 32 MiB
37external DRAM.
[d755cbd]38
39Interrupt Processing
40====================
41
42Every Epiphany core has 10 exception types:
43
44- Reset
45
46- Software Exception
47
48- Data Page Fault
49
50- Timer 0
51
52- Timer 1
53
54- Message Interrupt
55
56- DMA0 Interrupt
57
58- DMA1 Interrupt
59
60- WANT Interrupt
61
62- User Interrupt
63
64Interrupt Levels
65----------------
66
67There are only two levels: interrupts enabled and interrupts disabled.
68
69Interrupt Stack
70---------------
71
[f233256]72The Epiphany RTEMS port uses a dedicated software interrupt stack.  The stack
73for interrupts is allocated during interrupt driver initialization.  When an
74interrupt is entered, the _ISR_Handler routine is responsible for switching
75from the interrupted task stack to RTEMS software interrupt stack.
[d755cbd]76
77Default Fatal Error Processing
78==============================
79
[f233256]80The default fatal error handler for this architecture performs the following
81actions:
[d755cbd]82
83- disables operating system supported interrupts (IRQ),
84
85- places the error code in ``r0``, and
86
87- executes an infinite loop to simulate a halt processor instruction.
88
89Symmetric Multiprocessing
90=========================
91
92SMP is not supported.
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