1 | .. SPDX-License-Identifier: CC-BY-SA-4.0 |
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2 | |
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3 | .. Copyright (C) 2015 University of York. |
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4 | .. COMMENT: Hesham ALMatary <hmka501@york.ac.uk> |
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5 | |
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6 | Blackfin Specific Information |
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7 | ***************************** |
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8 | |
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9 | This chapter discusses the Blackfin architecture dependencies in this port of |
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10 | RTEMS. |
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11 | |
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12 | **Architecture Documents** |
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13 | |
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14 | For information on the Blackfin architecture, refer to the following documents |
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15 | available from Analog Devices. |
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16 | |
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17 | TBD |
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18 | |
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19 | - *"ADSP-BF533 Blackfin Processor Hardware Reference."* http://www.analog.com/UploadedFiles/Associated_Docs/892485982bf533_hwr.pdf |
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20 | |
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21 | CPU Model Dependent Features |
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22 | ============================ |
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23 | |
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24 | CPUs of the Blackfin 53X only differ in the peripherals and thus in the device |
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25 | drivers. This port does not yet support the 56X dual core variants. |
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26 | |
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27 | Count Leading Zeroes Instruction |
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28 | -------------------------------- |
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29 | |
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30 | The Blackfin CPU has the BITTST instruction which could be used to speed up the |
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31 | find first bit operation. The use of this instruction should significantly |
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32 | speed up the scheduling associated with a thread blocking. |
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33 | |
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34 | Calling Conventions |
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35 | =================== |
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36 | |
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37 | This section is heavily based on content taken from the Blackfin uCLinux |
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38 | documentation wiki which is edited by Analog Devices and Arcturus Networks. |
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39 | http://docs.blackfin.uclinux.org/ |
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40 | |
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41 | Processor Background |
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42 | -------------------- |
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43 | |
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44 | The Blackfin architecture supports a simple call and return mechanism. A |
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45 | subroutine is invoked via the call (``call``) instruction. This instruction |
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46 | saves the return address in the ``RETS`` register and transfers the execution |
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47 | to the given address. |
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48 | |
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49 | It is the called funcions responsability to use the link instruction to reserve |
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50 | space on the stack for the local variables. Returning from a subroutine is |
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51 | done by using the RTS (``RTS``) instruction which loads the PC with the adress |
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52 | stored in RETS. |
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53 | |
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54 | It is is important to note that the ``call`` instruction does not automatically |
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55 | save or restore any registers. It is the responsibility of the high-level |
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56 | language compiler to define the register preservation and usage convention. |
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57 | |
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58 | Register Usage |
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59 | -------------- |
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60 | |
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61 | A called function may clobber all registers, except RETS, R4-R7, P3-P5, FP and |
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62 | SP. It may also modify the first 12 bytes in the caller's stack frame which is |
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63 | used as an argument area for the first three arguments (which are passed in |
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64 | R0...R3 but may be placed on the stack by the called function). |
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65 | |
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66 | Parameter Passing |
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67 | ----------------- |
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68 | |
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69 | RTEMS assumes that the Blackfin GCC calling convention is followed. The first |
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70 | three parameters are stored in registers R0, R1, and R2. All other parameters |
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71 | are put pushed on the stack. The result is returned through register R0. |
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72 | |
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73 | Memory Model |
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74 | ============ |
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75 | |
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76 | The Blackfin family architecutre support a single unified 4 GB byte address |
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77 | space using 32-bit addresses. It maps all resources like internal and external |
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78 | memory and IO registers into separate sections of this common address space. |
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79 | |
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80 | The Blackfin architcture supports some form of memory protection via its Memory |
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81 | Management Unit. Since the Blackfin port runs in supervisior mode this memory |
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82 | protection mechanisms are not used. |
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83 | |
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84 | Interrupt Processing |
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85 | ==================== |
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86 | |
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87 | Discussed in this chapter are the Blackfin's interrupt response and control |
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88 | mechanisms as they pertain to RTEMS. The Blackfin architecture support 16 kinds |
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89 | of interrupts broken down into Core and general-purpose interrupts. |
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90 | |
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91 | Vectoring of an Interrupt Handler |
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92 | --------------------------------- |
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93 | |
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94 | RTEMS maps levels 0 -15 directly to Blackfins event vectors EVT0 - EVT15. Since |
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95 | EVT0 - EVT6 are core events and it is suggested to use EVT15 and EVT15 for |
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96 | Software interrupts, 7 Interrupts (EVT7-EVT13) are left for periferical use. |
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97 | |
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98 | When installing an RTEMS interrupt handler RTEMS installs a generic Interrupt |
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99 | Handler which saves some context and enables nested interrupt servicing and |
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100 | then vectors to the users interrupt handler. |
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101 | |
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102 | Disabling of Interrupts by RTEMS |
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103 | -------------------------------- |
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104 | |
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105 | During interrupt disable critical sections, RTEMS disables interrupts to level |
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106 | four (4) before the execution of this section and restores them to the previous |
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107 | level upon completion of the section. RTEMS uses the instructions CLI and STI |
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108 | to enable and disable Interrupts. Emulation, Reset, NMI and Exception |
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109 | Interrupts are never disabled. |
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110 | |
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111 | Interrupt Stack |
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112 | --------------- |
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113 | |
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114 | The Blackfin Architecture works with two different kind of stacks, User and |
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115 | Supervisor Stack. Since RTEMS and its Application run in supervisor mode, all |
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116 | interrupts will use the interrupted tasks stack for execution. |
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117 | |
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118 | Default Fatal Error Processing |
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119 | ============================== |
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120 | |
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121 | The default fatal error handler for the Blackfin performs the following |
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122 | actions: |
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123 | |
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124 | - disables processor interrupts, |
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125 | |
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126 | - places the error code in *r0*, and |
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127 | |
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128 | - executes an infinite loop (``while(0);`` to |
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129 | simulate a halt processor instruction. |
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130 | |
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131 | Symmetric Multiprocessing |
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132 | ========================= |
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133 | |
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134 | SMP is not supported. |
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135 | |
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136 | Thread-Local Storage |
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137 | ==================== |
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138 | |
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139 | Thread-local storage is not implemented. |
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140 | |
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141 | Board Support Packages |
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142 | ====================== |
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143 | |
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144 | System Reset |
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145 | ------------ |
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146 | |
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147 | TBD |
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