source: rtems-docs/cpu-supplement/blackfin.rst @ f067ba3

5am
Last change on this file since f067ba3 was 6916004, checked in by Chris Johns <chrisj@…>, on Nov 9, 2016 at 1:39:16 AM

cpu-supplement: Fix header levels.

  • Property mode set to 100644
File size: 5.0 KB
RevLine 
[489740f]1.. comment SPDX-License-Identifier: CC-BY-SA-4.0
2
[f233256]3.. COMMENT: Copyright (c) 2015 University of York.
4.. COMMENT: Hesham ALMatary <hmka501@york.ac.uk>
5
[d755cbd]6Blackfin Specific Information
[6916004]7*****************************
[d755cbd]8
[f233256]9This chapter discusses the Blackfin architecture dependencies in this port of
10RTEMS.
[d755cbd]11
12**Architecture Documents**
13
[f233256]14For information on the Blackfin architecture, refer to the following documents
15available from Analog Devices.
[d755cbd]16
17TBD
18
[f233256]19- *"ADSP-BF533 Blackfin Processor Hardware Reference."* http://www.analog.com/UploadedFiles/Associated_Docs/892485982bf533_hwr.pdf
[d755cbd]20
21CPU Model Dependent Features
22============================
23
[f233256]24CPUs of the Blackfin 53X only differ in the peripherals and thus in the device
25drivers. This port does not yet support the 56X dual core variants.
[d755cbd]26
27Count Leading Zeroes Instruction
28--------------------------------
29
[f233256]30The Blackfin CPU has the BITTST instruction which could be used to speed up the
31find first bit operation.  The use of this instruction should significantly
32speed up the scheduling associated with a thread blocking.
[d755cbd]33
34Calling Conventions
35===================
36
37This section is heavily based on content taken from the Blackfin uCLinux
[f233256]38documentation wiki which is edited by Analog Devices and Arcturus Networks.
39http://docs.blackfin.uclinux.org/
[d755cbd]40
41Processor Background
42--------------------
43
[f233256]44The Blackfin architecture supports a simple call and return mechanism.  A
45subroutine is invoked via the call (``call``) instruction.  This instruction
46saves the return address in the ``RETS`` register and transfers the execution
47to the given address.
[d755cbd]48
[f233256]49It is the called funcions responsability to use the link instruction to reserve
50space on the stack for the local variables.  Returning from a subroutine is
51done by using the RTS (``RTS``) instruction which loads the PC with the adress
52stored in RETS.
[d755cbd]53
[f233256]54It is is important to note that the ``call`` instruction does not automatically
55save or restore any registers.  It is the responsibility of the high-level
56language compiler to define the register preservation and usage convention.
[d755cbd]57
58Register Usage
59--------------
60
[f233256]61A called function may clobber all registers, except RETS, R4-R7, P3-P5, FP and
62SP.  It may also modify the first 12 bytes in the caller's stack frame which is
63used as an argument area for the first three arguments (which are passed in
64R0...R3 but may be placed on the stack by the called function).
[d755cbd]65
66Parameter Passing
67-----------------
68
[f233256]69RTEMS assumes that the Blackfin GCC calling convention is followed.  The first
70three parameters are stored in registers R0, R1, and R2.  All other parameters
71are put pushed on the stack.  The result is returned through register R0.
[d755cbd]72
73Memory Model
74============
75
[f233256]76The Blackfin family architecutre support a single unified 4 GB byte address
77space using 32-bit addresses. It maps all resources like internal and external
78memory and IO registers into separate sections of this common address space.
[d755cbd]79
[f233256]80The Blackfin architcture supports some form of memory protection via its Memory
81Management Unit. Since the Blackfin port runs in supervisior mode this memory
[d755cbd]82protection mechanisms are not used.
83
84Interrupt Processing
85====================
86
[f233256]87Discussed in this chapter are the Blackfin's interrupt response and control
88mechanisms as they pertain to RTEMS. The Blackfin architecture support 16 kinds
89of interrupts broken down into Core and general-purpose interrupts.
[d755cbd]90
91Vectoring of an Interrupt Handler
92---------------------------------
93
[f233256]94RTEMS maps levels 0 -15 directly to Blackfins event vectors EVT0 - EVT15. Since
95EVT0 - EVT6 are core events and it is suggested to use EVT15 and EVT15 for
96Software interrupts, 7 Interrupts (EVT7-EVT13) are left for periferical use.
[d755cbd]97
[f233256]98When installing an RTEMS interrupt handler RTEMS installs a generic Interrupt
99Handler which saves some context and enables nested interrupt servicing and
100then vectors to the users interrupt handler.
[d755cbd]101
102Disabling of Interrupts by RTEMS
103--------------------------------
104
[f233256]105During interrupt disable critical sections, RTEMS disables interrupts to level
106four (4) before the execution of this section and restores them to the previous
107level upon completion of the section. RTEMS uses the instructions CLI and STI
108to enable and disable Interrupts. Emulation, Reset, NMI and Exception
109Interrupts are never disabled.
[d755cbd]110
111Interrupt Stack
112---------------
113
[f233256]114The Blackfin Architecture works with two different kind of stacks, User and
115Supervisor Stack. Since RTEMS and its Application run in supervisor mode, all
116interrupts will use the interrupted tasks stack for execution.
[d755cbd]117
118Default Fatal Error Processing
119==============================
120
121The default fatal error handler for the Blackfin performs the following
122actions:
123
124- disables processor interrupts,
125
126- places the error code in *r0*, and
127
128- executes an infinite loop (``while(0);`` to
129  simulate a halt processor instruction.
130
131Symmetric Multiprocessing
132=========================
133
134SMP is not supported.
135
136Thread-Local Storage
137====================
138
139Thread-local storage is not implemented.
140
141Board Support Packages
142======================
143
144System Reset
145------------
146
147TBD
Note: See TracBrowser for help on using the repository browser.