source: rtems-docs/cpu-supplement/atmel_avr.rst @ 7193f09

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1.. comment SPDX-License-Identifier: CC-BY-SA-4.0
2
3.. COMMENT: COPYRIGHT (c) 1988-2006.
4.. COMMENT: On-Line Applications Research Corporation (OAR).
5.. COMMENT: All rights reserved.
6
7Atmel AVR Specific Information
8******************************
9
10This chapter discusses the AVR architecture dependencies in this port of RTEMS.
11
12**Architecture Documents**
13
14For information on the AVR architecture, refer to the following documents
15available from Atmel.
16
17TBD
18
19- See other CPUs for documentation reference formatting examples.
20
21CPU Model Dependent Features
22============================
23
24CPUs of the AVR 53X only differ in the peripherals and thus in the device
25drivers. This port does not yet support the 56X dual core variants.
26
27Count Leading Zeroes Instruction
28--------------------------------
29
30The AVR CPU has the XXX instruction which could be used to speed up the find
31first bit operation.  The use of this instruction should significantly speed up
32the scheduling associated with a thread blocking.
33
34Calling Conventions
35===================
36
37Processor Background
38--------------------
39
40The AVR architecture supports a simple call and return mechanism.  A subroutine
41is invoked via the call (``call``) instruction.  This instruction saves the
42return address in the ``RETS`` register and transfers the execution to the
43given address.
44
45It is the called funcions responsability to use the link instruction to reserve
46space on the stack for the local variables.  Returning from a subroutine is
47done by using the RTS (``RTS``) instruction which loads the PC with the adress
48stored in RETS.
49
50It is is important to note that the ``call`` instruction does not automatically
51save or restore any registers.  It is the responsibility of the high-level
52language compiler to define the register preservation and usage convention.
53
54Register Usage
55--------------
56
57A called function may clobber all registers, except RETS, R4-R7, P3-P5, FP and
58SP.  It may also modify the first 12 bytes in the caller's stack frame which is
59used as an argument area for the first three arguments (which are passed in
60R0...R3 but may be placed on the stack by the called function).
61
62Parameter Passing
63-----------------
64
65RTEMS assumes that the AVR GCC calling convention is followed.  The first three
66parameters are stored in registers R0, R1, and R2.  All other parameters are
67put pushed on the stack.  The result is returned through register R0.
68
69Memory Model
70============
71
72The AVR family architecutre support a single unified 4 GB byte address space
73using 32-bit addresses. It maps all resources like internal and external memory
74and IO registers into separate sections of this common address space.
75
76The AVR architcture supports some form of memory protection via its Memory
77Management Unit. Since the AVR port runs in supervisior mode this memory
78protection mechanisms are not used.
79
80Interrupt Processing
81====================
82
83Discussed in this chapter are the AVR's interrupt response and control
84mechanisms as they pertain to RTEMS.
85
86Vectoring of an Interrupt Handler
87---------------------------------
88
89TBD
90
91Disabling of Interrupts by RTEMS
92--------------------------------
93
94During interrupt disable critical sections, RTEMS disables interrupts to level
95N (N) before the execution of this section and restores them to the previous
96level upon completion of the section. RTEMS uses the instructions CLI and STI
97to enable and disable Interrupts. Emulation, Reset, NMI and Exception
98Interrupts are never disabled.
99
100Interrupt Stack
101---------------
102
103The AVR Architecture works with two different kind of stacks, User and
104Supervisor Stack. Since RTEMS and its Application run in supervisor mode, all
105interrupts will use the interrupted tasks stack for execution.
106
107Default Fatal Error Processing
108==============================
109
110The default fatal error handler for the AVR performs the following
111actions:
112
113- disables processor interrupts,
114
115- places the error code in *r0*, and
116
117- executes an infinite loop (``while(0);`` to
118  simulate a halt processor instruction.
119
120Symmetric Multiprocessing
121=========================
122
123SMP is not supported.
124
125Thread-Local Storage
126====================
127
128Thread-local storage is not supported due to a broken tool chain.
129
130Board Support Packages
131======================
132
133System Reset
134------------
135
136TBD
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