1 | .. SPDX-License-Identifier: CC-BY-SA-4.0 |
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2 | |
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3 | .. Copyright (C) 1988, 2006 On-Line Applications Research Corporation (OAR) |
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4 | |
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5 | Atmel AVR Specific Information |
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6 | ****************************** |
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7 | |
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8 | This chapter discusses the AVR architecture dependencies in this port of RTEMS. |
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9 | |
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10 | **Architecture Documents** |
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11 | |
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12 | For information on the AVR architecture, refer to the following documents |
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13 | available from Atmel. |
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14 | |
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15 | TBD |
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16 | |
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17 | - See other CPUs for documentation reference formatting examples. |
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18 | |
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19 | CPU Model Dependent Features |
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20 | ============================ |
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21 | |
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22 | CPUs of the AVR 53X only differ in the peripherals and thus in the device |
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23 | drivers. This port does not yet support the 56X dual core variants. |
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24 | |
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25 | Count Leading Zeroes Instruction |
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26 | -------------------------------- |
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27 | |
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28 | The AVR CPU has the XXX instruction which could be used to speed up the find |
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29 | first bit operation. The use of this instruction should significantly speed up |
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30 | the scheduling associated with a thread blocking. |
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31 | |
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32 | Calling Conventions |
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33 | =================== |
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34 | |
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35 | Processor Background |
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36 | -------------------- |
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37 | |
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38 | The AVR architecture supports a simple call and return mechanism. A subroutine |
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39 | is invoked via the call (``call``) instruction. This instruction saves the |
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40 | return address in the ``RETS`` register and transfers the execution to the |
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41 | given address. |
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42 | |
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43 | It is the called funcions responsability to use the link instruction to reserve |
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44 | space on the stack for the local variables. Returning from a subroutine is |
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45 | done by using the RTS (``RTS``) instruction which loads the PC with the adress |
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46 | stored in RETS. |
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47 | |
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48 | It is is important to note that the ``call`` instruction does not automatically |
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49 | save or restore any registers. It is the responsibility of the high-level |
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50 | language compiler to define the register preservation and usage convention. |
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51 | |
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52 | Register Usage |
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53 | -------------- |
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54 | |
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55 | A called function may clobber all registers, except RETS, R4-R7, P3-P5, FP and |
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56 | SP. It may also modify the first 12 bytes in the caller's stack frame which is |
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57 | used as an argument area for the first three arguments (which are passed in |
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58 | R0...R3 but may be placed on the stack by the called function). |
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59 | |
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60 | Parameter Passing |
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61 | ----------------- |
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62 | |
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63 | RTEMS assumes that the AVR GCC calling convention is followed. The first three |
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64 | parameters are stored in registers R0, R1, and R2. All other parameters are |
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65 | put pushed on the stack. The result is returned through register R0. |
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66 | |
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67 | Memory Model |
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68 | ============ |
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69 | |
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70 | The AVR family architecutre support a single unified 4 GB byte address space |
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71 | using 32-bit addresses. It maps all resources like internal and external memory |
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72 | and IO registers into separate sections of this common address space. |
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73 | |
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74 | The AVR architcture supports some form of memory protection via its Memory |
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75 | Management Unit. Since the AVR port runs in supervisior mode this memory |
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76 | protection mechanisms are not used. |
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77 | |
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78 | Interrupt Processing |
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79 | ==================== |
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80 | |
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81 | Discussed in this chapter are the AVR's interrupt response and control |
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82 | mechanisms as they pertain to RTEMS. |
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83 | |
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84 | Vectoring of an Interrupt Handler |
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85 | --------------------------------- |
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86 | |
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87 | TBD |
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88 | |
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89 | Disabling of Interrupts by RTEMS |
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90 | -------------------------------- |
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91 | |
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92 | During interrupt disable critical sections, RTEMS disables interrupts to level |
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93 | N (N) before the execution of this section and restores them to the previous |
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94 | level upon completion of the section. RTEMS uses the instructions CLI and STI |
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95 | to enable and disable Interrupts. Emulation, Reset, NMI and Exception |
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96 | Interrupts are never disabled. |
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97 | |
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98 | Interrupt Stack |
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99 | --------------- |
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100 | |
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101 | The AVR Architecture works with two different kind of stacks, User and |
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102 | Supervisor Stack. Since RTEMS and its Application run in supervisor mode, all |
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103 | interrupts will use the interrupted tasks stack for execution. |
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104 | |
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105 | Default Fatal Error Processing |
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106 | ============================== |
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107 | |
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108 | The default fatal error handler for the AVR performs the following |
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109 | actions: |
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110 | |
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111 | - disables processor interrupts, |
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112 | |
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113 | - places the error code in *r0*, and |
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114 | |
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115 | - executes an infinite loop (``while(0);`` to |
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116 | simulate a halt processor instruction. |
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117 | |
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118 | Symmetric Multiprocessing |
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119 | ========================= |
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120 | |
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121 | SMP is not supported. |
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122 | |
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123 | Thread-Local Storage |
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124 | ==================== |
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125 | |
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126 | Thread-local storage is not supported due to a broken tool chain. |
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127 | |
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128 | Board Support Packages |
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129 | ====================== |
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130 | |
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131 | System Reset |
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132 | ------------ |
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133 | |
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134 | TBD |
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