source: rtems-docs/cpu-supplement/arm.rst @ 7f51440

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Last change on this file since 7f51440 was 7f51440, checked in by Sebastian Huber <sebastian.huber@…>, on 05/15/19 at 05:17:51

cpu-supplement: Update ARM multilibs

Update #3747.

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1.. SPDX-License-Identifier: CC-BY-SA-4.0
2
3.. Copyright (C) 1988, 2009 On-Line Applications Research Corporation (OAR)
4
5ARM Specific Information
6************************
7
8This chapter discusses the *ARM architecture*
9(http://en.wikipedia.org/wiki/ARM_architecture) dependencies in this port of
10RTEMS.  The ARMv4T (and compatible), ARMv7-A, ARMv7-R and ARMv7-M architecture
11versions are supported by RTEMS.  Processors with a MMU use a static
12configuration which is set up during system start.  SMP is supported.
13
14**Architecture Documents**
15
16For information on the ARM architecture refer to the *ARM Infocenter*
17(http://infocenter.arm.com/).
18
19CPU Model Dependent Features
20============================
21
22This section presents the set of features which vary across ARM implementations
23and are of importance to RTEMS.  The set of CPU model feature macros are
24defined in the file :file:`cpukit/score/cpu/arm/rtems/score/arm.h` based upon
25the particular CPU model flags specified on the compilation command line.
26
27CPU Model Name
28--------------
29
30The macro ``CPU_MODEL_NAME`` is a string which designates the architectural
31level of this CPU model.  See in :file:`cpukit/score/cpu/arm/rtems/score/arm.h`
32for the values.
33
34Count Leading Zeroes Instruction
35--------------------------------
36
37The ARMv5 and later has the count leading zeroes ``clz`` instruction which
38could be used to speed up the find first bit operation.  The use of this
39instruction should significantly speed up the scheduling associated with a
40thread blocking.  This is currently not used.
41
42Floating Point Unit
43-------------------
44
45The following floating point units are supported:
46
47- VFPv2 (for example available on ARM926EJ-S processors)
48
49- VFPv3-D32/NEON (for example available on Cortex-A processors)
50
51- VFPv3-D16 (for example available on Cortex-R processors)
52
53- FPv4-SP-D16 (for example available on Cortex-M processors)
54
55- FPv5-D16 (for example available on Cortex-M7 processors)
56
57Multilibs
58=========
59
60The following multilibs are available:
61
62#. ``.``: ARMv4T, ARM instruction set
63
64#. ``vfp/hard``: ARMv4T, ARM instruction set with hard-float ABI and VFPv2 support
65
66#. ``thumb``: ARMv4T, Thumb-1 instruction set
67
68#. ``thumb/armv6-m``: ARMv6M, subset of Thumb-2 instruction set
69
70#. ``thumb/armv7-a``: ARMv7-A, Thumb-2 instruction set
71
72#. ``thumb/armv7-a/neon/hard``: ARMv7-A, Thumb-2 instruction set with
73   hard-float ABI Neon and VFP-D32 support
74
75#. ``thumb/armv7-r``: ARMv7-R, Thumb-2 instruction set
76
77#. ``thumb/armv7-r/vfpv3-d16/hard``: ARMv7-R, Thumb-2 instruction set with
78   hard-float ABI VFP-D16 support
79
80#. ``thumb/cortex-m3``: Cortex-M3, Thumb-2 instruction set with hardware
81   integer division (SDIV/UDIV) and a fix for Cortex-M3 Errata 602117.
82
83#. ``thumb/cortex-m4``: Cortex-M4, Thumb-2 instruction set with hardware
84   integer division (SDIV/UDIV) and DSP instructions
85
86#. ``thumb/cortex-m4/fpv4-sp-d16``: Cortex-M4, Thumb-2 instruction set with
87   hardware integer division (SDIV/UDIV), DSP instructions and hard-float ABI
88   FPv4-SP support
89
90#. ``thumb/cortex-m7/fpv5-d16``: Cortex-M7, Thumb-2 instruction set with
91   hard-float ABI and FPv5-D16 support
92
93#. ``eb/thumb/armv7-r``: ARMv7-R, Big-endian Thumb-2 instruction set
94
95#. ``eb/thumb/armv7-r/vfpv3-d16/hard``: ARMv7-R, Big-endian Thumb-2 instruction
96   set with hard-float ABI VFP-D16 support
97
98Multilib 1., 2. and 3. support the legacy ARM7TDMI and ARM926EJ-S processors.
99
100Multilib 4. supports the Cortex-M0 and Cortex-M1 cores.
101
102Multilib 5. and 6. support the Cortex-A processors.
103
104Multilib 7., 8., 13. and 14. support the Cortex-R processors.  Here also
105big-endian variants are available.
106
107Use for example the following GCC options:
108
109.. code-block:: shell
110
111    -mthumb -march=armv7-a -mfpu=neon -mfloat-abi=hard -mtune=cortex-a9
112
113to build an application or BSP for the ARMv7-A architecture and tune the code
114for a Cortex-A9 processor.  It is important to select the options used for the
115multilibs. For example:
116
117.. code-block:: shell
118
119    -mthumb -mcpu=cortex-a9
120
121alone will not select the ARMv7-A multilib.
122
123Calling Conventions
124===================
125
126Please refer to the *Procedure Call Standard for the ARM Architecture*
127(http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042c/IHI0042C_aapcs.pdf).
128
129Memory Model
130============
131
132A flat 32-bit memory model is supported.  The board support package must take
133care about the MMU if necessary.
134
135Interrupt Processing
136====================
137
138The ARMv4T (and compatible) architecture has seven exception types:
139
140- Reset
141
142- Undefined
143
144- Software Interrupt (SWI)
145
146- Prefetch Abort
147
148- Data Abort
149
150- Interrupt (IRQ)
151
152- Fast Interrupt (FIQ)
153
154Of these types only the IRQ has explicit operating system support.  It is
155intentional that the FIQ is not supported by the operating system.  Without
156operating system support for the FIQ it is not necessary to disable them during
157critical sections of the system.
158
159The ARMv7-M architecture has a completely different exception model.  Here
160interrupts are disabled with a write of 0x80 to the ``basepri_max`` register.
161This means that all exceptions and interrupts with a priority value of greater
162than or equal to 0x80 are disabled.  Thus exceptions and interrupts with a
163priority value of less than 0x80 are non-maskable with respect to the operating
164system and therefore must not use operating system services.  Several support
165libraries of chip vendors implicitly shift the priority value somehow before
166the value is written to the NVIC IPR register.  This can easily lead to
167confusion.
168
169Interrupt Levels
170----------------
171
172There are exactly two interrupt levels on ARM with respect to RTEMS.  Level
173zero corresponds to interrupts enabled.  Level one corresponds to interrupts
174disabled.
175
176Interrupt Stack
177---------------
178
179The board support package must initialize the interrupt stack. The memory for
180the stacks is usually reserved in the linker script.
181
182Default Fatal Error Processing
183==============================
184
185The default fatal error handler for this architecture performs the following
186actions:
187
188- disables operating system supported interrupts (IRQ),
189
190- places the error code in ``r0``, and
191
192- executes an infinite loop to simulate a halt processor instruction.
193
194Symmetric Multiprocessing
195=========================
196
197SMP is supported on ARMv7-A.  Available platforms are
198
199- Altera Cyclone V,
200
201- NXP i.MX 7, and
202
203- Xilinx Zynq.
204
205Thread-Local Storage
206====================
207
208Thread-local storage is supported.
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