1 | .. SPDX-License-Identifier: CC-BY-SA-4.0 |
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2 | |
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3 | .. Copyright (C) 1988, 2009 On-Line Applications Research Corporation (OAR) |
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4 | |
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5 | ARM Specific Information |
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6 | ************************ |
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7 | |
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8 | This chapter discusses the *ARM architecture* |
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9 | (http://en.wikipedia.org/wiki/ARM_architecture) dependencies in this port of |
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10 | RTEMS. The ARMv4T (and compatible), ARMv7-A, ARMv7-R and ARMv7-M architecture |
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11 | versions are supported by RTEMS. Processors with a MMU use a static |
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12 | configuration which is set up during system start. SMP is supported. |
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13 | |
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14 | **Architecture Documents** |
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15 | |
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16 | For information on the ARM architecture refer to the *ARM Infocenter* |
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17 | (http://infocenter.arm.com/). |
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18 | |
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19 | CPU Model Dependent Features |
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20 | ============================ |
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21 | |
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22 | This section presents the set of features which vary across ARM implementations |
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23 | and are of importance to RTEMS. The set of CPU model feature macros are |
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24 | defined in the file :file:`cpukit/score/cpu/arm/rtems/score/arm.h` based upon |
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25 | the particular CPU model flags specified on the compilation command line. |
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26 | |
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27 | CPU Model Name |
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28 | -------------- |
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29 | |
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30 | The macro ``CPU_MODEL_NAME`` is a string which designates the architectural |
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31 | level of this CPU model. See in :file:`cpukit/score/cpu/arm/rtems/score/arm.h` |
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32 | for the values. |
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33 | |
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34 | Count Leading Zeroes Instruction |
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35 | -------------------------------- |
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36 | |
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37 | The ARMv5 and later has the count leading zeroes ``clz`` instruction which |
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38 | could be used to speed up the find first bit operation. The use of this |
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39 | instruction should significantly speed up the scheduling associated with a |
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40 | thread blocking. This is currently not used. |
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41 | |
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42 | Floating Point Unit |
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43 | ------------------- |
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44 | |
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45 | The following floating point units are supported: |
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46 | |
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47 | - VFPv2 (for example available on ARM926EJ-S processors) |
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48 | |
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49 | - VFPv3-D32/NEON (for example available on Cortex-A processors) |
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50 | |
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51 | - VFPv3-D16 (for example available on Cortex-R processors) |
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52 | |
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53 | - FPv4-SP-D16 (for example available on Cortex-M processors) |
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54 | |
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55 | - FPv5-D16 (for example available on Cortex-M7 processors) |
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56 | |
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57 | Multilibs |
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58 | ========= |
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59 | |
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60 | The following multilibs are available: |
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61 | |
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62 | #. ``.``: ARMv4T, ARM instruction set |
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63 | |
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64 | #. ``vfp/hard``: ARMv4T, ARM instruction set with hard-float ABI and VFPv2 support |
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65 | |
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66 | #. ``thumb``: ARMv4T, Thumb-1 instruction set |
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67 | |
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68 | #. ``thumb/armv6-m``: ARMv6M, subset of Thumb-2 instruction set |
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69 | |
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70 | #. ``thumb/armv7-a``: ARMv7-A, Thumb-2 instruction set |
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71 | |
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72 | #. ``thumb/armv7-a/neon/hard``: ARMv7-A, Thumb-2 instruction set with |
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73 | hard-float ABI Neon and VFP-D32 support |
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74 | |
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75 | #. ``thumb/armv7-r``: ARMv7-R, Thumb-2 instruction set |
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76 | |
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77 | #. ``thumb/armv7-r/vfpv3-d16/hard``: ARMv7-R, Thumb-2 instruction set with |
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78 | hard-float ABI VFP-D16 support |
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79 | |
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80 | #. ``thumb/cortex-m3``: Cortex-M3, Thumb-2 instruction set with hardware |
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81 | integer division (SDIV/UDIV) and a fix for Cortex-M3 Errata 602117. |
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82 | |
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83 | #. ``thumb/cortex-m4``: Cortex-M4, Thumb-2 instruction set with hardware |
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84 | integer division (SDIV/UDIV) and DSP instructions |
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85 | |
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86 | #. ``thumb/cortex-m4/fpv4-sp-d16``: Cortex-M4, Thumb-2 instruction set with |
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87 | hardware integer division (SDIV/UDIV), DSP instructions and hard-float ABI |
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88 | FPv4-SP support |
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89 | |
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90 | #. ``thumb/cortex-m7/fpv5-d16``: Cortex-M7, Thumb-2 instruction set with |
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91 | hard-float ABI and FPv5-D16 support |
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92 | |
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93 | #. ``eb/thumb/armv7-r``: ARMv7-R, Big-endian Thumb-2 instruction set |
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94 | |
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95 | #. ``eb/thumb/armv7-r/vfpv3-d16/hard``: ARMv7-R, Big-endian Thumb-2 instruction |
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96 | set with hard-float ABI VFP-D16 support |
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97 | |
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98 | Multilib 1., 2. and 3. support the legacy ARM7TDMI and ARM926EJ-S processors. |
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99 | |
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100 | Multilib 4. supports the Cortex-M0 and Cortex-M1 cores. |
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101 | |
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102 | Multilib 5. and 6. support the Cortex-A processors. |
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103 | |
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104 | Multilib 7., 8., 13. and 14. support the Cortex-R processors. Here also |
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105 | big-endian variants are available. |
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106 | |
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107 | Use for example the following GCC options: |
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108 | |
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109 | .. code-block:: shell |
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110 | |
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111 | -mthumb -march=armv7-a -mfpu=neon -mfloat-abi=hard -mtune=cortex-a9 |
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112 | |
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113 | to build an application or BSP for the ARMv7-A architecture and tune the code |
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114 | for a Cortex-A9 processor. It is important to select the options used for the |
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115 | multilibs. For example: |
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116 | |
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117 | .. code-block:: shell |
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118 | |
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119 | -mthumb -mcpu=cortex-a9 |
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120 | |
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121 | alone will not select the ARMv7-A multilib. |
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122 | |
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123 | Calling Conventions |
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124 | =================== |
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125 | |
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126 | Please refer to the *Procedure Call Standard for the ARM Architecture* |
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127 | (http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042c/IHI0042C_aapcs.pdf). |
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128 | |
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129 | Memory Model |
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130 | ============ |
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131 | |
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132 | A flat 32-bit memory model is supported. The board support package must take |
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133 | care about the MMU if necessary. |
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134 | |
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135 | Interrupt Processing |
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136 | ==================== |
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137 | |
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138 | The ARMv4T (and compatible) architecture has seven exception types: |
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139 | |
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140 | - Reset |
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141 | |
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142 | - Undefined |
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143 | |
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144 | - Software Interrupt (SWI) |
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145 | |
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146 | - Prefetch Abort |
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147 | |
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148 | - Data Abort |
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149 | |
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150 | - Interrupt (IRQ) |
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151 | |
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152 | - Fast Interrupt (FIQ) |
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153 | |
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154 | Of these types only the IRQ has explicit operating system support. It is |
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155 | intentional that the FIQ is not supported by the operating system. Without |
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156 | operating system support for the FIQ it is not necessary to disable them during |
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157 | critical sections of the system. |
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158 | |
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159 | The ARMv7-M architecture has a completely different exception model. Here |
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160 | interrupts are disabled with a write of 0x80 to the ``basepri_max`` register. |
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161 | This means that all exceptions and interrupts with a priority value of greater |
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162 | than or equal to 0x80 are disabled. Thus exceptions and interrupts with a |
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163 | priority value of less than 0x80 are non-maskable with respect to the operating |
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164 | system and therefore must not use operating system services. Several support |
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165 | libraries of chip vendors implicitly shift the priority value somehow before |
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166 | the value is written to the NVIC IPR register. This can easily lead to |
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167 | confusion. |
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168 | |
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169 | Interrupt Levels |
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170 | ---------------- |
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171 | |
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172 | There are exactly two interrupt levels on ARM with respect to RTEMS. Level |
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173 | zero corresponds to interrupts enabled. Level one corresponds to interrupts |
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174 | disabled. |
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175 | |
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176 | Interrupt Stack |
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177 | --------------- |
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178 | |
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179 | The board support package must initialize the interrupt stack. The memory for |
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180 | the stacks is usually reserved in the linker script. |
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181 | |
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182 | Default Fatal Error Processing |
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183 | ============================== |
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184 | |
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185 | The default fatal error handler for this architecture performs the following |
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186 | actions: |
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187 | |
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188 | - disables operating system supported interrupts (IRQ), |
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189 | |
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190 | - places the error code in ``r0``, and |
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191 | |
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192 | - executes an infinite loop to simulate a halt processor instruction. |
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193 | |
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194 | Symmetric Multiprocessing |
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195 | ========================= |
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196 | |
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197 | SMP is supported on ARMv7-A. Available platforms are |
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198 | |
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199 | - Altera Cyclone V, |
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200 | |
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201 | - NXP i.MX 7, and |
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202 | |
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203 | - Xilinx Zynq. |
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204 | |
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205 | Thread-Local Storage |
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206 | ==================== |
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207 | |
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208 | Thread-local storage is supported. |
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