source: rtems-docs/cpu-supplement/arm.rst @ f067ba3

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Last change on this file since f067ba3 was 87e1929, checked in by Sebastian Huber <sebastian.huber@…>, on Sep 27, 2017 at 12:55:45 PM

Mention i.MX 7 SMP support

Update #3090.

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[489740f]1.. comment SPDX-License-Identifier: CC-BY-SA-4.0
2
[f233256]3.. COMMENT: COPYRIGHT (c) 1988-2009.
4.. COMMENT: On-Line Applications Research Corporation (OAR).
5.. COMMENT: All rights reserved.
6
[d755cbd]7ARM Specific Information
[6916004]8************************
[d755cbd]9
[f233256]10This chapter discusses the *ARM architecture*
11(http://en.wikipedia.org/wiki/ARM_architecture) dependencies in this port of
12RTEMS.  The ARMv4T (and compatible), ARMv7-A, ARMv7-R and ARMv7-M architecture
13versions are supported by RTEMS.  Processors with a MMU use a static
14configuration which is set up during system start.  SMP is supported.
[d755cbd]15
16**Architecture Documents**
17
[f233256]18For information on the ARM architecture refer to the *ARM Infocenter*
19(http://infocenter.arm.com/).
[d755cbd]20
21CPU Model Dependent Features
22============================
23
[f233256]24This section presents the set of features which vary across ARM implementations
25and are of importance to RTEMS.  The set of CPU model feature macros are
26defined in the file :file:`cpukit/score/cpu/arm/rtems/score/arm.h` based upon
27the particular CPU model flags specified on the compilation command line.
[d755cbd]28
29CPU Model Name
30--------------
31
[f233256]32The macro ``CPU_MODEL_NAME`` is a string which designates the architectural
33level of this CPU model.  See in :file:`cpukit/score/cpu/arm/rtems/score/arm.h`
34for the values.
[d755cbd]35
36Count Leading Zeroes Instruction
37--------------------------------
38
39The ARMv5 and later has the count leading zeroes ``clz`` instruction which
40could be used to speed up the find first bit operation.  The use of this
41instruction should significantly speed up the scheduling associated with a
42thread blocking.  This is currently not used.
43
44Floating Point Unit
45-------------------
46
47The following floating point units are supported.
48
49- VFPv3-D32/NEON (for example available on Cortex-A processors)
50
51- VFPv3-D16 (for example available on Cortex-R processors)
52
53- FPv4-SP-D16 (for example available on Cortex-M processors)
54
55Multilibs
56=========
57
58The following multilibs are available:
59
[f233256]60#. ``.``: ARMv4T, ARM instruction set
[d755cbd]61
[f233256]62#. ``thumb``: ARMv4T, Thumb-1 instruction set
[d755cbd]63
[f233256]64#. ``thumb/armv6-m``: ARMv6M, subset of Thumb-2 instruction set
[d755cbd]65
[f233256]66#. ``thumb/armv7-a``: ARMv7-A, Thumb-2 instruction set
[d755cbd]67
[f233256]68#. ``thumb/armv7-a/neon/hard``: ARMv7-A, Thumb-2 instruction set with
69   hard-float ABI Neon and VFP-D32 support
[d755cbd]70
[f233256]71#. ``thumb/armv7-r``: ARMv7-R, Thumb-2 instruction set
[d755cbd]72
[f233256]73#. ``thumb/armv7-r/vfpv3-d16/hard``: ARMv7-R, Thumb-2 instruction set with
74   hard-float ABI VFP-D16 support
[d755cbd]75
[f233256]76#. ``thumb/armv7-m``: ARMv7-M, Thumb-2 instruction set with hardware
77   integer division (SDIV/UDIV)
[d755cbd]78
[f233256]79#. ``thumb/armv7-m/fpv4-sp-d16``: ARMv7-M, Thumb-2 instruction set with
80   hardware integer division (SDIV/UDIV) and hard-float ABI FPv4-SP support
[d755cbd]81
[f233256]82#. ``eb/thumb/armv7-r``: ARMv7-R, Big-endian Thumb-2 instruction set
[d755cbd]83
[f233256]84#. ``eb/thumb/armv7-r/vfpv3-d16/hard``: ARMv7-R, Big-endian Thumb-2 instruction
85   set with hard-float ABI VFP-D16 support
[d755cbd]86
87Multilib 1. and 2. support the standard ARM7TDMI and ARM926EJ-S targets.
88
89Multilib 3. supports the Cortex-M0 and Cortex-M1 cores.
90
91Multilib 8. supports the Cortex-M3 and Cortex-M4 cores, which have a special
92hardware integer division instruction (this is not present in the A and R
93profiles).
94
95Multilib 9. supports the Cortex-M4 cores with a floating point unit.
96
97Multilib 4. and 5. support the Cortex-A processors.
98
99Multilib 6., 7., 10. and 11. support the Cortex-R processors.  Here also
100big-endian variants are available.
101
[f233256]102Use for example the following GCC options:
103
104.. code-block:: shell
[d755cbd]105
106    -mthumb -march=armv7-a -mfpu=neon -mfloat-abi=hard -mtune=cortex-a9
107
108to build an application or BSP for the ARMv7-A architecture and tune the code
109for a Cortex-A9 processor.  It is important to select the options used for the
[f233256]110multilibs. For example:
111
112.. code-block:: shell
[d755cbd]113
114    -mthumb -mcpu=cortex-a9
115
116alone will not select the ARMv7-A multilib.
117
118Calling Conventions
119===================
120
[f233256]121Please refer to the *Procedure Call Standard for the ARM Architecture*
122(http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042c/IHI0042C_aapcs.pdf).
[d755cbd]123
124Memory Model
125============
126
127A flat 32-bit memory model is supported.  The board support package must take
128care about the MMU if necessary.
129
130Interrupt Processing
131====================
132
133The ARMv4T (and compatible) architecture has seven exception types:
134
135- Reset
136
137- Undefined
138
139- Software Interrupt (SWI)
140
141- Prefetch Abort
142
143- Data Abort
144
145- Interrupt (IRQ)
146
147- Fast Interrupt (FIQ)
148
149Of these types only the IRQ has explicit operating system support.  It is
150intentional that the FIQ is not supported by the operating system.  Without
151operating system support for the FIQ it is not necessary to disable them during
152critical sections of the system.
153
154The ARMv7-M architecture has a completely different exception model.  Here
[f233256]155interrupts are disabled with a write of 0x80 to the ``basepri_max`` register.
156This means that all exceptions and interrupts with a priority value of greater
157than or equal to 0x80 are disabled.  Thus exceptions and interrupts with a
158priority value of less than 0x80 are non-maskable with respect to the operating
159system and therefore must not use operating system services.  Several support
160libraries of chip vendors implicitly shift the priority value somehow before
161the value is written to the NVIC IPR register.  This can easily lead to
[d755cbd]162confusion.
163
164Interrupt Levels
165----------------
166
167There are exactly two interrupt levels on ARM with respect to RTEMS.  Level
168zero corresponds to interrupts enabled.  Level one corresponds to interrupts
169disabled.
170
171Interrupt Stack
172---------------
173
174The board support package must initialize the interrupt stack. The memory for
175the stacks is usually reserved in the linker script.
176
177Default Fatal Error Processing
178==============================
179
[f233256]180The default fatal error handler for this architecture performs the following
181actions:
[d755cbd]182
183- disables operating system supported interrupts (IRQ),
184
185- places the error code in ``r0``, and
186
187- executes an infinite loop to simulate a halt processor instruction.
188
189Symmetric Multiprocessing
190=========================
191
[87e1929]192SMP is supported on ARMv7-A.  Available platforms are
193
194- Altera Cyclone V,
195
196- NXP i.MX 7, and
197
198- Xilinx Zynq.
[d755cbd]199
200Thread-Local Storage
201====================
202
203Thread-local storage is supported.
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