[e52906b] | 1 | .. SPDX-License-Identifier: CC-BY-SA-4.0 |
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[489740f] | 2 | |
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[4886d60] | 3 | .. Copyright (C) 1988, 2009 On-Line Applications Research Corporation (OAR) |
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[f233256] | 4 | |
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[d755cbd] | 5 | ARM Specific Information |
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[6916004] | 6 | ************************ |
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[d755cbd] | 7 | |
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[f233256] | 8 | This chapter discusses the *ARM architecture* |
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| 9 | (http://en.wikipedia.org/wiki/ARM_architecture) dependencies in this port of |
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| 10 | RTEMS. The ARMv4T (and compatible), ARMv7-A, ARMv7-R and ARMv7-M architecture |
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| 11 | versions are supported by RTEMS. Processors with a MMU use a static |
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| 12 | configuration which is set up during system start. SMP is supported. |
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[d755cbd] | 13 | |
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| 14 | **Architecture Documents** |
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| 15 | |
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[f233256] | 16 | For information on the ARM architecture refer to the *ARM Infocenter* |
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| 17 | (http://infocenter.arm.com/). |
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[d755cbd] | 18 | |
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| 19 | CPU Model Dependent Features |
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| 20 | ============================ |
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| 21 | |
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[f233256] | 22 | This section presents the set of features which vary across ARM implementations |
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| 23 | and are of importance to RTEMS. The set of CPU model feature macros are |
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| 24 | defined in the file :file:`cpukit/score/cpu/arm/rtems/score/arm.h` based upon |
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| 25 | the particular CPU model flags specified on the compilation command line. |
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[d755cbd] | 26 | |
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| 27 | CPU Model Name |
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| 28 | -------------- |
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| 29 | |
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[f233256] | 30 | The macro ``CPU_MODEL_NAME`` is a string which designates the architectural |
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| 31 | level of this CPU model. See in :file:`cpukit/score/cpu/arm/rtems/score/arm.h` |
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| 32 | for the values. |
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[d755cbd] | 33 | |
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| 34 | Count Leading Zeroes Instruction |
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| 35 | -------------------------------- |
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| 36 | |
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[d75b31f] | 37 | The ARMv5 and later instruction sets have the count leading zeroes ``clz`` |
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| 38 | instruction which could be used to speed up the find first bit operation. The |
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| 39 | use of this instruction should significantly speed up the scheduling associated |
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| 40 | with a thread blocking. This is currently not used. |
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[d755cbd] | 41 | |
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| 42 | Floating Point Unit |
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| 43 | ------------------- |
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| 44 | |
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[c1d296a] | 45 | The following floating point units are supported: |
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| 46 | |
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| 47 | - VFPv2 (for example available on ARM926EJ-S processors) |
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[d755cbd] | 48 | |
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| 49 | - VFPv3-D32/NEON (for example available on Cortex-A processors) |
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| 50 | |
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| 51 | - VFPv3-D16 (for example available on Cortex-R processors) |
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| 52 | |
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| 53 | - FPv4-SP-D16 (for example available on Cortex-M processors) |
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| 54 | |
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[c1d296a] | 55 | - FPv5-D16 (for example available on Cortex-M7 processors) |
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| 56 | |
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[d755cbd] | 57 | Multilibs |
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| 58 | ========= |
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| 59 | |
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| 60 | The following multilibs are available: |
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| 61 | |
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[f233256] | 62 | #. ``.``: ARMv4T, ARM instruction set |
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[d755cbd] | 63 | |
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[c1d296a] | 64 | #. ``vfp/hard``: ARMv4T, ARM instruction set with hard-float ABI and VFPv2 support |
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| 65 | |
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[f233256] | 66 | #. ``thumb``: ARMv4T, Thumb-1 instruction set |
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[d755cbd] | 67 | |
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[f233256] | 68 | #. ``thumb/armv6-m``: ARMv6M, subset of Thumb-2 instruction set |
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[d755cbd] | 69 | |
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[f233256] | 70 | #. ``thumb/armv7-a``: ARMv7-A, Thumb-2 instruction set |
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[d755cbd] | 71 | |
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[f233256] | 72 | #. ``thumb/armv7-a/neon/hard``: ARMv7-A, Thumb-2 instruction set with |
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| 73 | hard-float ABI Neon and VFP-D32 support |
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[d755cbd] | 74 | |
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[f233256] | 75 | #. ``thumb/armv7-r``: ARMv7-R, Thumb-2 instruction set |
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[d755cbd] | 76 | |
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[f233256] | 77 | #. ``thumb/armv7-r/vfpv3-d16/hard``: ARMv7-R, Thumb-2 instruction set with |
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| 78 | hard-float ABI VFP-D16 support |
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[d755cbd] | 79 | |
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[7f51440] | 80 | #. ``thumb/cortex-m3``: Cortex-M3, Thumb-2 instruction set with hardware |
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| 81 | integer division (SDIV/UDIV) and a fix for Cortex-M3 Errata 602117. |
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[d755cbd] | 82 | |
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[7f51440] | 83 | #. ``thumb/cortex-m4``: Cortex-M4, Thumb-2 instruction set with hardware |
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| 84 | integer division (SDIV/UDIV) and DSP instructions |
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| 85 | |
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| 86 | #. ``thumb/cortex-m4/fpv4-sp-d16``: Cortex-M4, Thumb-2 instruction set with |
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| 87 | hardware integer division (SDIV/UDIV), DSP instructions and hard-float ABI |
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| 88 | FPv4-SP support |
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[d755cbd] | 89 | |
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[c1d296a] | 90 | #. ``thumb/cortex-m7/fpv5-d16``: Cortex-M7, Thumb-2 instruction set with |
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| 91 | hard-float ABI and FPv5-D16 support |
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| 92 | |
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[f233256] | 93 | #. ``eb/thumb/armv7-r``: ARMv7-R, Big-endian Thumb-2 instruction set |
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[d755cbd] | 94 | |
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[f233256] | 95 | #. ``eb/thumb/armv7-r/vfpv3-d16/hard``: ARMv7-R, Big-endian Thumb-2 instruction |
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| 96 | set with hard-float ABI VFP-D16 support |
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[d755cbd] | 97 | |
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[7f51440] | 98 | Multilib 1., 2. and 3. support the legacy ARM7TDMI and ARM926EJ-S processors. |
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[d755cbd] | 99 | |
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[c1d296a] | 100 | Multilib 4. supports the Cortex-M0 and Cortex-M1 cores. |
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[d755cbd] | 101 | |
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[c1d296a] | 102 | Multilib 5. and 6. support the Cortex-A processors. |
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[d755cbd] | 103 | |
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[7f51440] | 104 | Multilib 7., 8., 13. and 14. support the Cortex-R processors. Here also |
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[d755cbd] | 105 | big-endian variants are available. |
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| 106 | |
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[f233256] | 107 | Use for example the following GCC options: |
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| 108 | |
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| 109 | .. code-block:: shell |
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[d755cbd] | 110 | |
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| 111 | -mthumb -march=armv7-a -mfpu=neon -mfloat-abi=hard -mtune=cortex-a9 |
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| 112 | |
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| 113 | to build an application or BSP for the ARMv7-A architecture and tune the code |
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| 114 | for a Cortex-A9 processor. It is important to select the options used for the |
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[f233256] | 115 | multilibs. For example: |
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| 116 | |
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| 117 | .. code-block:: shell |
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[d755cbd] | 118 | |
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| 119 | -mthumb -mcpu=cortex-a9 |
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| 120 | |
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| 121 | alone will not select the ARMv7-A multilib. |
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| 122 | |
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| 123 | Calling Conventions |
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| 124 | =================== |
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| 125 | |
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[f233256] | 126 | Please refer to the *Procedure Call Standard for the ARM Architecture* |
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| 127 | (http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042c/IHI0042C_aapcs.pdf). |
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[d755cbd] | 128 | |
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| 129 | Memory Model |
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| 130 | ============ |
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| 131 | |
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| 132 | A flat 32-bit memory model is supported. The board support package must take |
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[d75b31f] | 133 | care of initializing the MMU if necessary. |
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[df8261a] | 134 | |
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| 135 | Note that architecture variants which support unaligned accesses must not use |
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| 136 | memcpy() or memset() on device memory as those functions are hand-optimized and |
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| 137 | will take advantage of unaligned accesses where available. *As per ARM* |
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| 138 | (https://developer.arm.com/documentation/ddi0406/c/Application-Level-Architecture/Application-Level-Memory-Model/Alignment-support/Unaligned-data-access-restrictions-in-ARMv7-and-ARMv6), |
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| 139 | unaligned accesses are not permitted for device memory. |
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[d755cbd] | 140 | |
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| 141 | Interrupt Processing |
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| 142 | ==================== |
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| 143 | |
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| 144 | The ARMv4T (and compatible) architecture has seven exception types: |
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| 145 | |
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| 146 | - Reset |
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| 147 | |
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| 148 | - Undefined |
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| 149 | |
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| 150 | - Software Interrupt (SWI) |
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| 151 | |
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| 152 | - Prefetch Abort |
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| 153 | |
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| 154 | - Data Abort |
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| 155 | |
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| 156 | - Interrupt (IRQ) |
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| 157 | |
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| 158 | - Fast Interrupt (FIQ) |
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| 159 | |
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| 160 | Of these types only the IRQ has explicit operating system support. It is |
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| 161 | intentional that the FIQ is not supported by the operating system. Without |
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| 162 | operating system support for the FIQ it is not necessary to disable them during |
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| 163 | critical sections of the system. |
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| 164 | |
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| 165 | The ARMv7-M architecture has a completely different exception model. Here |
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[f233256] | 166 | interrupts are disabled with a write of 0x80 to the ``basepri_max`` register. |
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| 167 | This means that all exceptions and interrupts with a priority value of greater |
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| 168 | than or equal to 0x80 are disabled. Thus exceptions and interrupts with a |
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| 169 | priority value of less than 0x80 are non-maskable with respect to the operating |
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| 170 | system and therefore must not use operating system services. Several support |
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| 171 | libraries of chip vendors implicitly shift the priority value somehow before |
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| 172 | the value is written to the NVIC IPR register. This can easily lead to |
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[d755cbd] | 173 | confusion. |
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| 174 | |
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| 175 | Interrupt Levels |
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| 176 | ---------------- |
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| 177 | |
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| 178 | There are exactly two interrupt levels on ARM with respect to RTEMS. Level |
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| 179 | zero corresponds to interrupts enabled. Level one corresponds to interrupts |
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| 180 | disabled. |
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| 181 | |
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| 182 | Interrupt Stack |
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| 183 | --------------- |
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| 184 | |
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| 185 | The board support package must initialize the interrupt stack. The memory for |
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| 186 | the stacks is usually reserved in the linker script. |
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| 187 | |
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| 188 | Default Fatal Error Processing |
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| 189 | ============================== |
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| 190 | |
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[f233256] | 191 | The default fatal error handler for this architecture performs the following |
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| 192 | actions: |
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[d755cbd] | 193 | |
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| 194 | - disables operating system supported interrupts (IRQ), |
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| 195 | |
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| 196 | - places the error code in ``r0``, and |
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| 197 | |
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| 198 | - executes an infinite loop to simulate a halt processor instruction. |
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| 199 | |
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| 200 | Symmetric Multiprocessing |
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| 201 | ========================= |
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| 202 | |
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[d75b31f] | 203 | SMP is supported on ARMv7-A. Available platforms are: |
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[87e1929] | 204 | |
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[d75b31f] | 205 | - Altera Cyclone V |
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[87e1929] | 206 | |
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[d75b31f] | 207 | - NXP i.MX 7 |
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[87e1929] | 208 | |
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[d75b31f] | 209 | - Xilinx Zynq |
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[d755cbd] | 210 | |
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| 211 | Thread-Local Storage |
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| 212 | ==================== |
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| 213 | |
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| 214 | Thread-local storage is supported. |
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