1 | .. SPDX-License-Identifier: CC-BY-SA-4.0 |
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2 | |
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3 | .. Copyright (C) 1988, 2020 On-Line Applications Research Corporation (OAR) |
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4 | |
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5 | AArch64 Specific Information |
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6 | ************************ |
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7 | |
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8 | This chapter discusses the dependencies of the |
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9 | *ARM AArch64 architecture* |
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10 | (https://en.wikipedia.org/wiki/ARM_architecture#AArch64_features) in this port |
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11 | of RTEMS. The ARMv8-A versions are supported by RTEMS. Processors with a MMU |
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12 | use a static configuration which is set up during system start. SMP is not |
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13 | supported. |
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14 | |
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15 | **Architecture Documents** |
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16 | |
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17 | For information on the ARM AArch64 architecture refer to the *ARM Infocenter* |
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18 | (http://infocenter.arm.com/). |
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19 | |
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20 | CPU Model Dependent Features |
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21 | ============================ |
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22 | |
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23 | This section presents the set of features which vary across ARM AArch64 |
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24 | implementations and are of importance to RTEMS. The set of CPU model feature |
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25 | macros are defined in the file :file:`cpukit/score/cpu/aarch64/rtems/score/aarch64.h` |
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26 | based upon the particular CPU model flags specified on the compilation command |
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27 | line. |
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28 | |
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29 | CPU Model Name |
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30 | -------------- |
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31 | |
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32 | The macro ``CPU_MODEL_NAME`` is a string which designates the architectural |
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33 | level of this CPU model. See in :file:`cpukit/score/cpu/aarch64/rtems/score/aarch64.h` |
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34 | for the values. |
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35 | |
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36 | Floating Point Unit and SIMD |
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37 | ---------------------------- |
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38 | |
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39 | The Advanced SIMD (NEON) and Floating-point instruction set extension is |
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40 | supported and expected to be present since all ARMv8-A CPUs are expected to |
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41 | support it as per the *ARMv8-A Programmer's Guide Chapter 7 introduction* |
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42 | (https://developer.arm.com/docs/den0024/a/aarch64-floating-point-and-neon). As |
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43 | such, ``CPU_HARDWARE_FP`` will always be set to ``TRUE``. |
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44 | |
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45 | Multilibs |
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46 | ========= |
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47 | |
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48 | The following multilib variants are available: |
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49 | |
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50 | #. ``ILP32``: AArch64 instruction set and registers using 32bit long int and pointers |
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51 | |
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52 | #. ``LP64``: AArch64 instruction set and registers using 64bit long int and pointers |
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53 | |
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54 | Use for example the following GCC options: |
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55 | |
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56 | .. code-block:: shell |
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57 | |
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58 | -mcpu=cortex-a53 -mabi=ilp32 |
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59 | |
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60 | to build an application or BSP for the ARMv8-A architecture and tune the code |
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61 | for a Cortex-A53 processor. It is important to select the correct ABI. |
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62 | |
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63 | Calling Conventions |
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64 | =================== |
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65 | |
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66 | Please refer to the *Procedure Call Standard for the ARM 64-bit Architecture* |
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67 | (https://github.com/ARM-software/abi-aa/releases/download/2019Q4/aapcs64.pdf). |
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68 | |
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69 | Memory Model |
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70 | ============ |
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71 | |
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72 | A flat 64-bit or 32-bit memory model is supported depending on the selected multilib |
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73 | variant. All AArch64 CPU variants support a built-in MMU for which basic initialization |
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74 | for a flat memory model is handled. |
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75 | |
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76 | Interrupt Processing |
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77 | ==================== |
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78 | |
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79 | The Reset Vector is determined using RVBAR and is Read-Only. RVBAR is set using |
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80 | configuration signals only sampled at reset. The ARMv8 architecture has four |
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81 | exception types: |
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82 | |
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83 | - Synchronous Exception |
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84 | |
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85 | - Interrupt (IRQ) |
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86 | |
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87 | - Fast Interrupt (FIQ) |
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88 | |
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89 | - System Error Exception |
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90 | |
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91 | Of these types only the synchronous and IRQ exceptions have explicit operating |
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92 | system support. It is intentional that the FIQ is not supported by the operating |
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93 | system. Without operating system support for the FIQ it is not necessary to |
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94 | disable them during critical sections of the system. |
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95 | |
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96 | Interrupt Levels |
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97 | ---------------- |
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98 | |
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99 | There are exactly two interrupt levels on ARMv8 with respect to RTEMS. Level |
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100 | zero corresponds to interrupts enabled. Level one corresponds to interrupts |
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101 | disabled. |
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102 | |
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103 | Interrupt Stack |
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104 | --------------- |
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105 | |
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106 | The board support package must initialize the interrupt stack. The memory for |
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107 | the stacks is usually reserved in the linker script. The interrupt stack pointer |
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108 | is stored in the EL0 stack pointer and is accessed by switching to SP0 mode |
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109 | at the beginning of interrupt calls and back to SPx mode after completion of |
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110 | interrupt calls using the `spsel` instruction. |
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111 | |
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112 | Default Fatal Error Processing |
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113 | ============================== |
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114 | |
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115 | The default fatal error handler for this architecture performs the following |
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116 | actions: |
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117 | |
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118 | - disables operating system supported interrupts (IRQ), |
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119 | |
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120 | - places the error code in ``x0``, and |
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121 | |
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122 | - executes an infinite loop to simulate a halt processor instruction. |
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123 | |
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124 | Symmetric Multiprocessing |
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125 | ========================= |
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126 | |
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127 | SMP is not currently supported on ARMv8-A. |
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128 | |
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129 | Thread-Local Storage |
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130 | ==================== |
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131 | |
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132 | Thread-local storage (TLS) is supported. AArch64 uses unmodified TLS variant I |
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133 | which is not explcitly stated, but can be inferred from the behavior of GCC and |
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134 | *Addenda to, and Errata in, the ABI for the Arm® Architecture* |
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135 | (https://developer.arm.com/documentation/ihi0045/g). This alters expectations |
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136 | for the size of the TLS Thread Control Block (TCB) such that, under the LP64 |
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137 | multilib variant, the TCB is 16 bytes in size instead of 8 bytes. |
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