source: rtems-docs/cpu-supplement/aarch64.rst @ ac8f461

Last change on this file since ac8f461 was ac8f461, checked in by Kinsey Moore <kinsey.moore@…>, on 11/01/21 at 18:52:52

cpu-supplement: Update AArch64 SMP details

AArch64 now supports SMP for the Xilinx ZynqMP BSP family.

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1.. SPDX-License-Identifier: CC-BY-SA-4.0
2
3.. Copyright (C) 1988, 2020 On-Line Applications Research Corporation (OAR)
4
5AArch64 Specific Information
6************************
7
8This chapter discusses the dependencies of the
9*ARM AArch64 architecture*
10(https://en.wikipedia.org/wiki/ARM_architecture#AArch64_features) in this port
11of RTEMS.  The ARMv8-A versions are supported by RTEMS.  Processors with a MMU
12use a static configuration which is set up during system start.  SMP is
13supported.
14
15**Architecture Documents**
16
17For information on the ARM AArch64 architecture refer to the *ARM Infocenter*
18(http://infocenter.arm.com/).
19
20CPU Model Dependent Features
21============================
22
23This section presents the set of features which vary across ARM AArch64
24implementations and are of importance to RTEMS.  The set of CPU model feature
25macros are defined in the file :file:`cpukit/score/cpu/aarch64/rtems/score/aarch64.h`
26based upon the particular CPU model flags specified on the compilation command
27line.
28
29CPU Model Name
30--------------
31
32The macro ``CPU_MODEL_NAME`` is a string which designates the architectural
33level of this CPU model.  See in :file:`cpukit/score/cpu/aarch64/rtems/score/aarch64.h`
34for the values.
35
36Floating Point Unit and SIMD
37----------------------------
38
39The Advanced SIMD (NEON) and Floating-point instruction set extension is
40supported and expected to be present since all ARMv8-A CPUs are expected to
41support it as per the *ARMv8-A Programmer's Guide Chapter 7 introduction*
42(https://developer.arm.com/docs/den0024/a/aarch64-floating-point-and-neon). As
43such, ``CPU_HARDWARE_FP`` will always be set to ``TRUE``.
44
45Multilibs
46=========
47
48The following multilib variants are available:
49
50#. ``ILP32``: AArch64 instruction set and registers using 32bit long int and pointers
51
52#. ``LP64``: AArch64 instruction set and registers using 64bit long int and pointers
53
54Use for example the following GCC options:
55
56.. code-block:: shell
57
58    -mcpu=cortex-a53 -mabi=ilp32
59
60to build an application or BSP for the ARMv8-A architecture and tune the code
61for a Cortex-A53 processor.  It is important to select the correct ABI.
62
63Calling Conventions
64===================
65
66Please refer to the *Procedure Call Standard for the ARM 64-bit Architecture*
67(https://github.com/ARM-software/abi-aa/releases/download/2019Q4/aapcs64.pdf).
68
69Memory Model
70============
71
72A flat 64-bit or 32-bit memory model is supported depending on the selected multilib
73variant.  All AArch64 CPU variants support a built-in MMU for which basic initialization
74for a flat memory model is handled.
75
76Interrupt Processing
77====================
78
79The Reset Vector is determined using RVBAR and is Read-Only. RVBAR is set using
80configuration signals only sampled at reset.  The ARMv8 architecture has four
81exception types:
82
83- Synchronous Exception
84
85- Interrupt (IRQ)
86
87- Fast Interrupt (FIQ)
88
89- System Error Exception
90
91Of these types only the synchronous and IRQ exceptions have explicit operating
92system support.  It is intentional that the FIQ is not supported by the operating
93system.  Without operating system support for the FIQ it is not necessary to
94disable them during critical sections of the system.
95
96Interrupt Levels
97----------------
98
99There are exactly two interrupt levels on ARMv8 with respect to RTEMS.  Level
100zero corresponds to interrupts enabled.  Level one corresponds to interrupts
101disabled.
102
103Interrupt Stack
104---------------
105
106The board support package must initialize the interrupt stack. The memory for
107the stacks is usually reserved in the linker script. The interrupt stack pointer
108is stored in the EL0 stack pointer and is accessed by switching to SP0 mode
109at the beginning of interrupt calls and back to SPx mode after completion of
110interrupt calls using the `spsel` instruction.
111
112Default Fatal Error Processing
113==============================
114
115The default fatal error handler for this architecture performs the following
116actions:
117
118- disables operating system supported interrupts (IRQ),
119
120- places the error code in ``x0``, and
121
122- executes an infinite loop to simulate a halt processor instruction.
123
124Symmetric Multiprocessing
125=========================
126
127SMP is supported on ARMv8-A.  Available platforms are:
128
129- Xilinx ZynqMP (QEMU and hardware using PSCI via ARM Trusted Firmware)
130
131Thread-Local Storage
132====================
133
134Thread-local storage (TLS) is supported. AArch64 uses unmodified TLS variant I
135which is not explcitly stated, but can be inferred from the behavior of GCC and
136*Addenda to, and Errata in, the ABI for the Arm® Architecture*
137(https://developer.arm.com/documentation/ihi0045/g). This alters expectations
138for the size of the TLS Thread Control Block (TCB) such that, under the LP64
139multilib variant, the TCB is 16 bytes in size instead of 8 bytes.
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