1 | Interrupt Manager |
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2 | ################# |
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3 | |
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4 | Introduction |
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5 | ============ |
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6 | |
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7 | Any real-time executive must provide a mechanism for |
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8 | quick response to externally generated interrupts to satisfy the |
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9 | critical time constraints of the application. The interrupt |
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10 | manager provides this mechanism for RTEMS. This manager permits |
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11 | quick interrupt response times by providing the critical ability |
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12 | to alter task execution which allows a task to be preempted upon |
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13 | exit from an ISR. The interrupt manager includes the following |
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14 | directive: |
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15 | |
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16 | - ``rtems_interrupt_catch`` - Establish an ISR |
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17 | |
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18 | - ``rtems_interrupt_disable`` - Disable Interrupts |
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19 | |
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20 | - ``rtems_interrupt_enable`` - Enable Interrupts |
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21 | |
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22 | - ``rtems_interrupt_flash`` - Flash Interrupt |
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23 | |
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24 | - ``rtems_interrupt_local_disable`` - Disable Interrupts on Current Processor |
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25 | |
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26 | - ``rtems_interrupt_local_enable`` - Enable Interrupts on Current Processor |
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27 | |
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28 | - ``rtems_interrupt_lock_initialize`` - Initialize an ISR Lock |
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29 | |
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30 | - ``rtems_interrupt_lock_acquire`` - Acquire an ISR Lock |
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31 | |
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32 | - ``rtems_interrupt_lock_release`` - Release an ISR Lock |
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33 | |
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34 | - ``rtems_interrupt_lock_acquire_isr`` - Acquire an ISR Lock from ISR |
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35 | |
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36 | - ``rtems_interrupt_lock_release_isr`` - Release an ISR Lock from ISR |
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37 | |
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38 | - ``rtems_interrupt_is_in_progress`` - Is an ISR in Progress |
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39 | |
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40 | Background |
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41 | ========== |
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42 | |
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43 | Processing an Interrupt |
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44 | ----------------------- |
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45 | .. index:: interrupt processing |
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46 | |
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47 | The interrupt manager allows the application to |
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48 | connect a function to a hardware interrupt vector. When an |
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49 | interrupt occurs, the processor will automatically vector to |
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50 | RTEMS. RTEMS saves and restores all registers which are not |
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51 | preserved by the normal C calling convention |
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52 | for the target |
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53 | processor and invokes the userâs ISR. The userâs ISR is |
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54 | responsible for processing the interrupt, clearing the interrupt |
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55 | if necessary, and device specific manipulation... index:: rtems_vector_number |
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56 | |
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57 | The ``rtems_interrupt_catch`` |
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58 | directive connects a procedure to |
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59 | an interrupt vector. The vector number is managed using |
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60 | the ``rtems_vector_number`` data type. |
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61 | |
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62 | The interrupt service routine is assumed |
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63 | to abide by these conventions and have a prototype similar to |
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64 | the following:.. index:: rtems_isr |
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65 | |
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66 | .. code:: c |
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67 | |
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68 | rtems_isr user_isr( |
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69 | rtems_vector_number vector |
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70 | ); |
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71 | |
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72 | The vector number argument is provided by RTEMS to |
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73 | allow the application to identify the interrupt source. This |
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74 | could be used to allow a single routine to service interrupts |
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75 | from multiple instances of the same device. For example, a |
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76 | single routine could service interrupts from multiple serial |
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77 | ports and use the vector number to identify which port requires |
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78 | servicing. |
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79 | |
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80 | To minimize the masking of lower or equal priority |
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81 | level interrupts, the ISR should perform the minimum actions |
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82 | required to service the interrupt. Other non-essential actions |
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83 | should be handled by application tasks. Once the userâs ISR has |
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84 | completed, it returns control to the RTEMS interrupt manager |
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85 | which will perform task dispatching and restore the registers |
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86 | saved before the ISR was invoked. |
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87 | |
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88 | The RTEMS interrupt manager guarantees that proper |
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89 | task scheduling and dispatching are performed at the conclusion |
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90 | of an ISR. A system call made by the ISR may have readied a |
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91 | task of higher priority than the interrupted task. Therefore, |
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92 | when the ISR completes, the postponed dispatch processing must |
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93 | be performed. No dispatch processing is performed as part of |
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94 | directives which have been invoked by an ISR. |
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95 | |
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96 | Applications must adhere to the following rule if |
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97 | proper task scheduling and dispatching is to be performed: |
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98 | |
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99 | - ** *The interrupt manager must be used for all ISRs which |
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100 | may be interrupted by the highest priority ISR which invokes an |
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101 | RTEMS directive.* |
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102 | |
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103 | Consider a processor which allows a numerically low |
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104 | interrupt level to interrupt a numerically greater interrupt |
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105 | level. In this example, if an RTEMS directive is used in a |
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106 | level 4 ISR, then all ISRs which execute at levels 0 through 4 |
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107 | must use the interrupt manager. |
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108 | |
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109 | Interrupts are nested whenever an interrupt occurs |
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110 | during the execution of another ISR. RTEMS supports efficient |
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111 | interrupt nesting by allowing the nested ISRs to terminate |
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112 | without performing any dispatch processing. Only when the |
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113 | outermost ISR terminates will the postponed dispatching occur. |
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114 | |
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115 | RTEMS Interrupt Levels |
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116 | ---------------------- |
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117 | .. index:: interrupt levels |
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118 | |
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119 | Many processors support multiple interrupt levels or |
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120 | priorities. The exact number of interrupt levels is processor |
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121 | dependent. RTEMS internally supports 256 interrupt levels which |
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122 | are mapped to the processorâs interrupt levels. For specific |
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123 | information on the mapping between RTEMS and the target |
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124 | processorâs interrupt levels, refer to the Interrupt Processing |
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125 | chapter of the Applications Supplement document for a specific |
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126 | target processor. |
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127 | |
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128 | Disabling of Interrupts by RTEMS |
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129 | -------------------------------- |
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130 | .. index:: disabling interrupts |
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131 | |
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132 | During the execution of directive calls, critical |
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133 | sections of code may be executed. When these sections are |
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134 | encountered, RTEMS disables all maskable interrupts before the |
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135 | execution of the section and restores them to the previous level |
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136 | upon completion of the section. RTEMS has been optimized to |
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137 | ensure that interrupts are disabled for a minimum length of |
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138 | time. The maximum length of time interrupts are disabled by |
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139 | RTEMS is processor dependent and is detailed in the Timing |
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140 | Specification chapter of the Applications Supplement document |
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141 | for a specific target processor. |
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142 | |
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143 | Non-maskable interrupts (NMI) cannot be disabled, and |
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144 | ISRs which execute at this level MUST NEVER issue RTEMS system |
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145 | calls. If a directive is invoked, unpredictable results may |
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146 | occur due to the inability of RTEMS to protect its critical |
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147 | sections. However, ISRs that make no system calls may safely |
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148 | execute as non-maskable interrupts. |
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149 | |
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150 | Operations |
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151 | ========== |
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152 | |
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153 | Establishing an ISR |
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154 | ------------------- |
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155 | |
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156 | The ``rtems_interrupt_catch`` |
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157 | directive establishes an ISR for |
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158 | the system. The address of the ISR and its associated CPU |
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159 | vector number are specified to this directive. This directive |
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160 | installs the RTEMS interrupt wrapper in the processorâs |
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161 | Interrupt Vector Table and the address of the userâs ISR in the |
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162 | RTEMSâ Vector Table. This directive returns the previous |
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163 | contents of the specified vector in the RTEMSâ Vector Table. |
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164 | |
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165 | Directives Allowed from an ISR |
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166 | ------------------------------ |
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167 | |
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168 | Using the interrupt manager ensures that RTEMS knows |
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169 | when a directive is being called from an ISR. The ISR may then |
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170 | use system calls to synchronize itself with an application task. |
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171 | The synchronization may involve messages, events or signals |
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172 | being passed by the ISR to the desired task. Directives invoked |
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173 | by an ISR must operate only on objects which reside on the local |
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174 | node. The following is a list of RTEMS system calls that may be |
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175 | made from an ISR: |
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176 | |
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177 | - Task Management |
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178 | Although it is acceptable to operate on the RTEMS_SELF task (e.g. |
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179 | the currently executing task), while in an ISR, this will refer |
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180 | to the interrupted task. Most of the time, it is an application |
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181 | implementation error to use RTEMS_SELF from an ISR. |
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182 | - rtems_task_suspend |
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183 | - rtems_task_resume |
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184 | |
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185 | - Interrupt Management |
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186 | - rtems_interrupt_enable |
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187 | - rtems_interrupt_disable |
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188 | - rtems_interrupt_flash |
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189 | - rtems_interrupt_lock_acquire |
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190 | - rtems_interrupt_lock_release |
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191 | - rtems_interrupt_lock_acquire_isr |
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192 | - rtems_interrupt_lock_release_isr |
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193 | - rtems_interrupt_is_in_progress |
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194 | - rtems_interrupt_catch |
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195 | |
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196 | - Clock Management |
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197 | - rtems_clock_set |
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198 | - rtems_clock_get |
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199 | - rtems_clock_get_tod |
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200 | - rtems_clock_get_tod_timeval |
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201 | - rtems_clock_get_seconds_since_epoch |
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202 | - rtems_clock_get_ticks_per_second |
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203 | - rtems_clock_get_ticks_since_boot |
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204 | - rtems_clock_get_uptime |
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205 | - rtems_clock_set_nanoseconds_extension |
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206 | - rtems_clock_tick |
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207 | |
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208 | - Timer Management |
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209 | - rtems_timer_cancel |
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210 | - rtems_timer_reset |
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211 | - rtems_timer_fire_after |
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212 | - rtems_timer_fire_when |
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213 | - rtems_timer_server_fire_after |
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214 | - rtems_timer_server_fire_when |
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215 | |
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216 | - Event Management |
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217 | - rtems_event_send |
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218 | - rtems_event_system_send |
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219 | - rtems_event_transient_send |
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220 | |
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221 | - Semaphore Management |
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222 | - rtems_semaphore_release |
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223 | |
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224 | - Message Management |
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225 | - rtems_message_queue_send |
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226 | - rtems_message_queue_urgent |
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227 | |
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228 | - Signal Management |
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229 | - rtems_signal_send |
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230 | |
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231 | - Dual-Ported Memory Management |
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232 | - rtems_port_external_to_internal |
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233 | - rtems_port_internal_to_external |
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234 | |
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235 | - IO Management |
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236 | The following services are safe to call from an ISR if and only if |
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237 | the device driver service invoked is also safe. The IO Manager itself |
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238 | is safe but the invoked driver entry point may or may not be. |
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239 | - rtems_io_initialize |
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240 | - rtems_io_open |
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241 | - rtems_io_close |
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242 | - rtems_io_read |
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243 | - rtems_io_write |
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244 | - rtems_io_control |
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245 | |
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246 | - Fatal Error Management |
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247 | - rtems_fatal |
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248 | - rtems_fatal_error_occurred |
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249 | |
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250 | - Multiprocessing |
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251 | - rtems_multiprocessing_announce |
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252 | |
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253 | Directives |
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254 | ========== |
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255 | |
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256 | This section details the interrupt managerâs |
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257 | directives. A subsection is dedicated to each of this managerâs |
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258 | directives and describes the calling sequence, related |
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259 | constants, usage, and status codes. |
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260 | |
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261 | INTERRUPT_CATCH - Establish an ISR |
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262 | ---------------------------------- |
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263 | .. index:: establish an ISR |
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264 | .. index:: install an ISR |
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265 | |
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266 | **CALLING SEQUENCE:** |
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267 | |
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268 | .. index:: rtems_interrupt_catch |
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269 | |
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270 | .. code:: c |
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271 | |
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272 | rtems_status_code rtems_interrupt_catch( |
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273 | rtems_isr_entry new_isr_handler, |
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274 | rtems_vector_number vector, |
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275 | rtems_isr_entry \*old_isr_handler |
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276 | ); |
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277 | |
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278 | **DIRECTIVE STATUS CODES:** |
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279 | |
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280 | ``RTEMS_SUCCESSFUL`` - ISR established successfully |
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281 | ``RTEMS_INVALID_NUMBER`` - illegal vector number |
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282 | ``RTEMS_INVALID_ADDRESS`` - illegal ISR entry point or invalid ``old_isr_handler`` |
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283 | |
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284 | **DESCRIPTION:** |
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285 | |
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286 | This directive establishes an interrupt service |
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287 | routine (ISR) for the specified interrupt vector number. The``new_isr_handler`` parameter specifies the entry point of the ISR. |
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288 | The entry point of the previous ISR for the specified vector is |
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289 | returned in ``old_isr_handler``. |
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290 | |
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291 | To release an interrupt vector, pass the old handlerâs address obtained |
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292 | when the vector was first capture. |
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293 | |
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294 | **NOTES:** |
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295 | |
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296 | This directive will not cause the calling task to be preempted. |
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297 | |
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298 | INTERRUPT_DISABLE - Disable Interrupts |
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299 | -------------------------------------- |
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300 | .. index:: disable interrupts |
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301 | |
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302 | **CALLING SEQUENCE:** |
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303 | |
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304 | .. index:: rtems_interrupt_disable |
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305 | |
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306 | .. code:: c |
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307 | |
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308 | void rtems_interrupt_disable( |
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309 | rtems_interrupt_level level |
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310 | ); |
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311 | /* this is implemented as a macro and sets level as a side-effect \*/ |
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312 | |
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313 | **DIRECTIVE STATUS CODES:** |
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314 | |
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315 | NONE |
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316 | |
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317 | **DESCRIPTION:** |
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318 | |
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319 | This directive disables all maskable interrupts and returns |
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320 | the previous ``level``. A later invocation of the``rtems_interrupt_enable`` directive should be used to |
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321 | restore the interrupt level. |
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322 | |
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323 | **NOTES:** |
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324 | |
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325 | This directive will not cause the calling task to be preempted. |
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326 | |
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327 | *This directive is implemented as a macro which modifies the ``level`` |
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328 | parameter.* |
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329 | |
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330 | This directive is only available on uni-processor configurations. The |
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331 | directive ``rtems_interrupt_local_disable`` is available on all |
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332 | configurations. |
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333 | |
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334 | INTERRUPT_ENABLE - Enable Interrupts |
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335 | ------------------------------------ |
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336 | .. index:: enable interrupts |
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337 | |
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338 | **CALLING SEQUENCE:** |
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339 | |
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340 | .. index:: rtems_interrupt_enable |
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341 | |
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342 | .. code:: c |
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343 | |
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344 | void rtems_interrupt_enable( |
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345 | rtems_interrupt_level level |
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346 | ); |
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347 | |
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348 | **DIRECTIVE STATUS CODES:** |
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349 | |
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350 | NONE |
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351 | |
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352 | **DESCRIPTION:** |
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353 | |
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354 | This directive enables maskable interrupts to the ``level`` |
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355 | which was returned by a previous call to``rtems_interrupt_disable``. |
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356 | Immediately prior to invoking this directive, maskable interrupts should |
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357 | be disabled by a call to ``rtems_interrupt_disable`` |
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358 | and will be enabled when this directive returns to the caller. |
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359 | |
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360 | **NOTES:** |
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361 | |
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362 | This directive will not cause the calling task to be preempted. |
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363 | |
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364 | This directive is only available on uni-processor configurations. The |
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365 | directive ``rtems_interrupt_local_enable`` is available on all |
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366 | configurations. |
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367 | |
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368 | INTERRUPT_FLASH - Flash Interrupts |
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369 | ---------------------------------- |
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370 | .. index:: flash interrupts |
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371 | |
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372 | **CALLING SEQUENCE:** |
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373 | |
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374 | .. index:: rtems_interrupt_flash |
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375 | |
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376 | .. code:: c |
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377 | |
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378 | void rtems_interrupt_flash( |
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379 | rtems_interrupt_level level |
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380 | ); |
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381 | |
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382 | **DIRECTIVE STATUS CODES:** |
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383 | |
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384 | NONE |
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385 | |
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386 | **DESCRIPTION:** |
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387 | |
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388 | This directive temporarily enables maskable interrupts to the ``level`` |
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389 | which was returned by a previous call to``rtems_interrupt_disable``. |
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390 | Immediately prior to invoking this directive, maskable interrupts should |
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391 | be disabled by a call to ``rtems_interrupt_disable`` |
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392 | and will be redisabled when this directive returns to the caller. |
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393 | |
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394 | **NOTES:** |
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395 | |
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396 | This directive will not cause the calling task to be preempted. |
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397 | |
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398 | This directive is only available on uni-processor configurations. The |
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399 | directives ``rtems_interrupt_local_disable`` and``rtems_interrupt_local_enable`` is available on all |
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400 | configurations. |
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401 | |
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402 | INTERRUPT_LOCAL_DISABLE - Disable Interrupts on Current Processor |
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403 | ----------------------------------------------------------------- |
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404 | .. index:: disable interrupts |
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405 | |
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406 | **CALLING SEQUENCE:** |
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407 | |
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408 | .. index:: rtems_interrupt_local_disable |
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409 | |
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410 | .. code:: c |
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411 | |
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412 | void rtems_interrupt_local_disable( |
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413 | rtems_interrupt_level level |
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414 | ); |
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415 | /* this is implemented as a macro and sets level as a side-effect \*/ |
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416 | |
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417 | **DIRECTIVE STATUS CODES:** |
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418 | |
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419 | NONE |
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420 | |
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421 | **DESCRIPTION:** |
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422 | |
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423 | This directive disables all maskable interrupts and returns |
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424 | the previous ``level``. A later invocation of the``rtems_interrupt_local_enable`` directive should be used to |
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425 | restore the interrupt level. |
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426 | |
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427 | **NOTES:** |
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428 | |
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429 | This directive will not cause the calling task to be preempted. |
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430 | |
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431 | *This directive is implemented as a macro which modifies the ``level`` |
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432 | parameter.* |
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433 | |
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434 | On SMP configurations this will not ensure system wide mutual exclusion. Use |
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435 | interrupt locks instead. |
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436 | |
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437 | INTERRUPT_LOCAL_ENABLE - Enable Interrupts on Current Processor |
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438 | --------------------------------------------------------------- |
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439 | .. index:: enable interrupts |
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440 | |
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441 | **CALLING SEQUENCE:** |
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442 | |
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443 | .. index:: rtems_interrupt_local_enable |
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444 | |
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445 | .. code:: c |
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446 | |
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447 | void rtems_interrupt_local_enable( |
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448 | rtems_interrupt_level level |
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449 | ); |
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450 | |
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451 | **DIRECTIVE STATUS CODES:** |
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452 | |
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453 | NONE |
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454 | |
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455 | **DESCRIPTION:** |
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456 | |
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457 | This directive enables maskable interrupts to the ``level`` |
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458 | which was returned by a previous call to``rtems_interrupt_local_disable``. |
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459 | Immediately prior to invoking this directive, maskable interrupts should |
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460 | be disabled by a call to ``rtems_interrupt_local_disable`` |
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461 | and will be enabled when this directive returns to the caller. |
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462 | |
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463 | **NOTES:** |
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464 | |
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465 | This directive will not cause the calling task to be preempted. |
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466 | |
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467 | INTERRUPT_LOCK_INITIALIZE - Initialize an ISR Lock |
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468 | -------------------------------------------------- |
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469 | |
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470 | **CALLING SEQUENCE:** |
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471 | |
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472 | .. index:: rtems_interrupt_lock_initialize |
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473 | |
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474 | .. code:: c |
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475 | |
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476 | void rtems_interrupt_lock_initialize( |
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477 | rtems_interrupt_lock \*lock |
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478 | ); |
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479 | |
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480 | **DIRECTIVE STATUS CODES:** |
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481 | |
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482 | NONE |
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483 | |
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484 | **DESCRIPTION:** |
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485 | |
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486 | Initializes an interrupt lock. |
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487 | |
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488 | **NOTES:** |
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489 | |
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490 | Concurrent initialization leads to unpredictable results. |
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491 | |
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492 | INTERRUPT_LOCK_ACQUIRE - Acquire an ISR Lock |
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493 | -------------------------------------------- |
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494 | |
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495 | **CALLING SEQUENCE:** |
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496 | |
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497 | .. index:: rtems_interrupt_lock_acquire |
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498 | |
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499 | .. code:: c |
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500 | |
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501 | void rtems_interrupt_lock_acquire( |
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502 | rtems_interrupt_lock \*lock, |
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503 | rtems_interrupt_level level |
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504 | ); |
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505 | |
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506 | **DIRECTIVE STATUS CODES:** |
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507 | |
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508 | NONE |
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509 | |
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510 | **DESCRIPTION:** |
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511 | |
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512 | Interrupts will be disabled. On SMP configurations this directive acquires a |
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513 | SMP lock. |
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514 | |
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515 | **NOTES:** |
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516 | |
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517 | This directive will not cause the calling thread to be preempted. This |
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518 | directive can be used in thread and interrupt context. |
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519 | |
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520 | INTERRUPT_LOCK_RELEASE - Release an ISR Lock |
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521 | -------------------------------------------- |
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522 | |
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523 | **CALLING SEQUENCE:** |
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524 | |
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525 | .. index:: rtems_interrupt_lock_release |
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526 | |
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527 | .. code:: c |
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528 | |
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529 | void rtems_interrupt_lock_release( |
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530 | rtems_interrupt_lock \*lock, |
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531 | rtems_interrupt_level level |
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532 | ); |
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533 | |
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534 | **DIRECTIVE STATUS CODES:** |
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535 | |
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536 | NONE |
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537 | |
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538 | **DESCRIPTION:** |
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539 | |
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540 | The interrupt status will be restored. On SMP configurations this directive |
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541 | releases a SMP lock. |
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542 | |
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543 | **NOTES:** |
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544 | |
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545 | This directive will not cause the calling thread to be preempted. This |
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546 | directive can be used in thread and interrupt context. |
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547 | |
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548 | INTERRUPT_LOCK_ACQUIRE_ISR - Acquire an ISR Lock from ISR |
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549 | --------------------------------------------------------- |
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550 | |
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551 | **CALLING SEQUENCE:** |
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552 | |
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553 | .. index:: rtems_interrupt_lock_acquire_isr |
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554 | |
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555 | .. code:: c |
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556 | |
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557 | void rtems_interrupt_lock_acquire_isr( |
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558 | rtems_interrupt_lock \*lock, |
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559 | rtems_interrupt_level level |
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560 | ); |
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561 | |
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562 | **DIRECTIVE STATUS CODES:** |
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563 | |
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564 | NONE |
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565 | |
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566 | **DESCRIPTION:** |
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567 | |
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568 | The interrupt status will remain unchanged. On SMP configurations this |
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569 | directive acquires a SMP lock. |
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570 | |
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571 | In case the corresponding interrupt service routine can be interrupted by |
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572 | higher priority interrupts and these interrupts enter the critical section |
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573 | protected by this lock, then the result is unpredictable. |
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574 | |
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575 | **NOTES:** |
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576 | |
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577 | This directive should be called from the corresponding interrupt service |
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578 | routine. |
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579 | |
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580 | INTERRUPT_LOCK_RELEASE_ISR - Release an ISR Lock from ISR |
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581 | --------------------------------------------------------- |
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582 | |
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583 | **CALLING SEQUENCE:** |
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584 | |
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585 | .. index:: rtems_interrupt_lock_release_isr |
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586 | |
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587 | .. code:: c |
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588 | |
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589 | void rtems_interrupt_lock_release_isr( |
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590 | rtems_interrupt_lock \*lock, |
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591 | rtems_interrupt_level level |
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592 | ); |
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593 | |
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594 | **DIRECTIVE STATUS CODES:** |
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595 | |
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596 | NONE |
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597 | |
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598 | **DESCRIPTION:** |
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599 | |
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600 | The interrupt status will remain unchanged. On SMP configurations this |
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601 | directive releases a SMP lock. |
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602 | |
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603 | **NOTES:** |
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604 | |
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605 | This directive should be called from the corresponding interrupt service |
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606 | routine. |
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607 | |
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608 | INTERRUPT_IS_IN_PROGRESS - Is an ISR in Progress |
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609 | ------------------------------------------------ |
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610 | .. index:: is interrupt in progress |
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611 | |
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612 | **CALLING SEQUENCE:** |
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613 | |
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614 | .. index:: rtems_interrupt_is_in_progress |
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615 | |
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616 | .. code:: c |
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617 | |
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618 | bool rtems_interrupt_is_in_progress( void ); |
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619 | |
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620 | **DIRECTIVE STATUS CODES:** |
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621 | |
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622 | NONE |
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623 | |
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624 | **DESCRIPTION:** |
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625 | |
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626 | This directive returns ``TRUE`` if the processor is currently |
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627 | servicing an interrupt and ``FALSE`` otherwise. A return value |
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628 | of ``TRUE`` indicates that the caller is an interrupt service |
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629 | routine, *NOT* a task. The directives available to an interrupt |
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630 | service routine are restricted. |
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631 | |
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632 | **NOTES:** |
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633 | |
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634 | This directive will not cause the calling task to be preempted. |
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635 | |
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636 | .. COMMENT: COPYRIGHT (c) 1988-2008 |
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637 | |
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638 | .. COMMENT: On-Line Applications Research Corporation (OAR). |
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639 | |
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640 | .. COMMENT: All rights reserved. |
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641 | |
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