source: rtems-docs/ada_user/interrupt_manager.rst @ 1a1be7f

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1Interrupt Manager
2#################
3
4Introduction
5============
6
7Any real-time executive must provide a mechanism for
8quick response to externally generated interrupts to satisfy the
9critical time constraints of the application.  The interrupt
10manager provides this mechanism for RTEMS.  This manager permits
11quick interrupt response times by providing the critical ability
12to alter task execution which allows a task to be preempted upon
13exit from an ISR.  The interrupt manager includes the following
14directive:
15
16- ``rtems.interrupt_catch`` - Establish an ISR
17
18- ``rtems.interrupt_disable`` - Disable Interrupts
19
20- ``rtems.interrupt_enable`` - Enable Interrupts
21
22- ``rtems.interrupt_flash`` - Flash Interrupt
23
24- ``rtems.interrupt_local_disable`` - Disable Interrupts on Current Processor
25
26- ``rtems.interrupt_local_enable`` - Enable Interrupts on Current Processor
27
28- ``rtems.interrupt_lock_initialize`` - Initialize an ISR Lock
29
30- ``rtems.interrupt_lock_acquire`` - Acquire an ISR Lock
31
32- ``rtems.interrupt_lock_release`` - Release an ISR Lock
33
34- ``rtems.interrupt_lock_acquire_isr`` - Acquire an ISR Lock from ISR
35
36- ``rtems.interrupt_lock_release_isr`` - Release an ISR Lock from ISR
37
38- ``rtems.interrupt_is_in_progress`` - Is an ISR in Progress
39
40Background
41==========
42
43Processing an Interrupt
44-----------------------
45.. index:: interrupt processing
46
47The interrupt manager allows the application to
48connect a function to a hardware interrupt vector.  When an
49interrupt occurs, the processor will automatically vector to
50RTEMS.  RTEMS saves and restores all registers which are not
51preserved by the normal Ada calling convention
52for the target
53processor and invokes the user’s ISR.  The user’s ISR is
54responsible for processing the interrupt, clearing the interrupt
55if necessary, and device specific manipulation... index:: rtems_vector_number
56
57The ``rtems.interrupt_catch``
58directive connects a procedure to
59an interrupt vector.  The vector number is managed using
60the ``rtems.vector_number`` data type.
61
62The interrupt service routine is assumed
63to abide by these conventions and have a prototype similar to
64the following:
65
66.. code:: c
67
68    NOT SUPPORTED FROM Ada BINDING
69
70The vector number argument is provided by RTEMS to
71allow the application to identify the interrupt source.  This
72could be used to allow a single routine to service interrupts
73from multiple instances of the same device.  For example, a
74single routine could service interrupts from multiple serial
75ports and use the vector number to identify which port requires
76servicing.
77
78To minimize the masking of lower or equal priority
79level interrupts, the ISR should perform the minimum actions
80required to service the interrupt.  Other non-essential actions
81should be handled by application tasks.  Once the user’s ISR has
82completed, it returns control to the RTEMS interrupt manager
83which will perform task dispatching and restore the registers
84saved before the ISR was invoked.
85
86The RTEMS interrupt manager guarantees that proper
87task scheduling and dispatching are performed at the conclusion
88of an ISR.  A system call made by the ISR may have readied a
89task of higher priority than the interrupted task.  Therefore,
90when the ISR completes, the postponed dispatch processing must
91be performed.  No dispatch processing is performed as part of
92directives which have been invoked by an ISR.
93
94Applications must adhere to the following rule if
95proper task scheduling and dispatching is to be performed:
96
97- ** *The interrupt manager must be used for all ISRs which
98  may be interrupted by the highest priority ISR which invokes an
99  RTEMS directive.*
100
101Consider a processor which allows a numerically low
102interrupt level to interrupt a numerically greater interrupt
103level.  In this example, if an RTEMS directive is used in a
104level 4 ISR, then all ISRs which execute at levels 0 through 4
105must use the interrupt manager.
106
107Interrupts are nested whenever an interrupt occurs
108during the execution of another ISR.  RTEMS supports efficient
109interrupt nesting by allowing the nested ISRs to terminate
110without performing any dispatch processing.  Only when the
111outermost ISR terminates will the postponed dispatching occur.
112
113RTEMS Interrupt Levels
114----------------------
115.. index:: interrupt levels
116
117Many processors support multiple interrupt levels or
118priorities.  The exact number of interrupt levels is processor
119dependent.  RTEMS internally supports 256 interrupt levels which
120are mapped to the processor’s interrupt levels.  For specific
121information on the mapping between RTEMS and the target
122processor’s interrupt levels, refer to the Interrupt Processing
123chapter of the Applications Supplement document for a specific
124target processor.
125
126Disabling of Interrupts by RTEMS
127--------------------------------
128.. index:: disabling interrupts
129
130During the execution of directive calls, critical
131sections of code may be executed.  When these sections are
132encountered, RTEMS disables all maskable interrupts before the
133execution of the section and restores them to the previous level
134upon completion of the section.  RTEMS has been optimized to
135ensure that interrupts are disabled for a minimum length of
136time.  The maximum length of time interrupts are disabled by
137RTEMS is processor dependent and is detailed in the Timing
138Specification chapter of the Applications Supplement document
139for a specific target processor.
140
141Non-maskable interrupts (NMI) cannot be disabled, and
142ISRs which execute at this level MUST NEVER issue RTEMS system
143calls.  If a directive is invoked, unpredictable results may
144occur due to the inability of RTEMS to protect its critical
145sections.  However, ISRs that make no system calls may safely
146execute as non-maskable interrupts.
147
148Operations
149==========
150
151Establishing an ISR
152-------------------
153
154The ``rtems.interrupt_catch``
155directive establishes an ISR for
156the system.  The address of the ISR and its associated CPU
157vector number are specified to this directive.  This directive
158installs the RTEMS interrupt wrapper in the processor’s
159Interrupt Vector Table and the address of the user’s ISR in the
160RTEMS’ Vector Table.  This directive returns the previous
161contents of the specified vector in the RTEMS’ Vector Table.
162
163Directives Allowed from an ISR
164------------------------------
165
166Using the interrupt manager ensures that RTEMS knows
167when a directive is being called from an ISR.  The ISR may then
168use system calls to synchronize itself with an application task.
169The synchronization may involve messages, events or signals
170being passed by the ISR to the desired task.  Directives invoked
171by an ISR must operate only on objects which reside on the local
172node.  The following is a list of RTEMS system calls that may be
173made from an ISR:
174
175- Task Management
176  Although it is acceptable to operate on the RTEMS_SELF task (e.g.
177  the currently executing task), while in an ISR, this will refer
178  to the interrupted task.  Most of the time, it is an application
179  implementation error to use RTEMS_SELF from an ISR.
180  - rtems_task_suspend
181  - rtems_task_resume
182
183- Interrupt Management
184  - rtems_interrupt_enable
185  - rtems_interrupt_disable
186  - rtems_interrupt_flash
187  - rtems_interrupt_lock_acquire
188  - rtems_interrupt_lock_release
189  - rtems_interrupt_lock_acquire_isr
190  - rtems_interrupt_lock_release_isr
191  - rtems_interrupt_is_in_progress
192  - rtems_interrupt_catch
193
194- Clock Management
195  - rtems_clock_set
196  - rtems_clock_get
197  - rtems_clock_get_tod
198  - rtems_clock_get_tod_timeval
199  - rtems_clock_get_seconds_since_epoch
200  - rtems_clock_get_ticks_per_second
201  - rtems_clock_get_ticks_since_boot
202  - rtems_clock_get_uptime
203  - rtems_clock_set_nanoseconds_extension
204  - rtems_clock_tick
205
206- Timer Management
207  - rtems_timer_cancel
208  - rtems_timer_reset
209  - rtems_timer_fire_after
210  - rtems_timer_fire_when
211  - rtems_timer_server_fire_after
212  - rtems_timer_server_fire_when
213
214- Event Management
215  - rtems_event_send
216  - rtems_event_system_send
217  - rtems_event_transient_send
218
219- Semaphore Management
220  - rtems_semaphore_release
221
222- Message Management
223  - rtems_message_queue_send
224  - rtems_message_queue_urgent
225
226- Signal Management
227  - rtems_signal_send
228
229- Dual-Ported Memory Management
230  - rtems_port_external_to_internal
231  - rtems_port_internal_to_external
232
233- IO Management
234  The following services are safe to call from an ISR if and only if
235  the device driver service invoked is also safe.  The IO Manager itself
236  is safe but the invoked driver entry point may or may not be.
237  - rtems_io_initialize
238  - rtems_io_open
239  - rtems_io_close
240  - rtems_io_read
241  - rtems_io_write
242  - rtems_io_control
243
244- Fatal Error Management
245  - rtems_fatal
246  - rtems_fatal_error_occurred
247
248- Multiprocessing
249  - rtems_multiprocessing_announce
250
251Directives
252==========
253
254This section details the interrupt manager’s
255directives.  A subsection is dedicated to each of this manager’s
256directives and describes the calling sequence, related
257constants, usage, and status codes.
258
259INTERRUPT_CATCH - Establish an ISR
260----------------------------------
261.. index:: establish an ISR
262.. index:: install an ISR
263
264**CALLING SEQUENCE:**
265
266.. code:: c
267
268    NOT SUPPORTED FROM Ada BINDING
269
270**DIRECTIVE STATUS CODES:**
271
272``RTEMS.SUCCESSFUL`` - ISR established successfully
273``RTEMS.INVALID_NUMBER`` - illegal vector number
274``RTEMS.INVALID_ADDRESS`` - illegal ISR entry point or invalid ``old_isr_handler``
275
276**DESCRIPTION:**
277
278This directive establishes an interrupt service
279routine (ISR) for the specified interrupt vector number.  The``new_isr_handler`` parameter specifies the entry point of the ISR.
280The entry point of the previous ISR for the specified vector is
281returned in ``old_isr_handler``.
282
283To release an interrupt vector, pass the old handler’s address obtained
284when the vector was first capture.
285
286**NOTES:**
287
288This directive will not cause the calling task to be preempted.
289
290INTERRUPT_DISABLE - Disable Interrupts
291--------------------------------------
292.. index:: disable interrupts
293
294**CALLING SEQUENCE:**
295
296.. code:: c
297
298    function Interrupt_Disable return RTEMS.ISR_Level;
299
300**DIRECTIVE STATUS CODES:**
301
302NONE
303
304**DESCRIPTION:**
305
306This directive disables all maskable interrupts and returns
307the previous ``level``.  A later invocation of the``rtems.interrupt_enable`` directive should be used to
308restore the interrupt level.
309
310**NOTES:**
311
312This directive will not cause the calling task to be preempted.
313
314This directive is only available on uni-processor configurations.  The
315directive ``rtems.interrupt_local_disable`` is available on all
316configurations.
317
318INTERRUPT_ENABLE - Enable Interrupts
319------------------------------------
320.. index:: enable interrupts
321
322**CALLING SEQUENCE:**
323
324.. code:: c
325
326    procedure Interrupt_Enable (
327    Level : in     RTEMS.ISR_Level
328    );
329
330**DIRECTIVE STATUS CODES:**
331
332NONE
333
334**DESCRIPTION:**
335
336This directive enables maskable interrupts to the ``level``
337which was returned by a previous call to``rtems.interrupt_disable``.
338Immediately prior to invoking this directive, maskable interrupts should
339be disabled by a call to ``rtems.interrupt_disable``
340and will be enabled when this directive returns to the caller.
341
342**NOTES:**
343
344This directive will not cause the calling task to be preempted.
345
346This directive is only available on uni-processor configurations.  The
347directive ``rtems.interrupt_local_enable`` is available on all
348configurations.
349
350INTERRUPT_FLASH - Flash Interrupts
351----------------------------------
352.. index:: flash interrupts
353
354**CALLING SEQUENCE:**
355
356.. code:: c
357
358    procedure Interrupt_Flash (
359    Level : in     RTEMS.ISR_Level
360    );
361
362**DIRECTIVE STATUS CODES:**
363
364NONE
365
366**DESCRIPTION:**
367
368This directive temporarily enables maskable interrupts to the ``level``
369which was returned by a previous call to``rtems.interrupt_disable``.
370Immediately prior to invoking this directive, maskable interrupts should
371be disabled by a call to ``rtems.interrupt_disable``
372and will be redisabled when this directive returns to the caller.
373
374**NOTES:**
375
376This directive will not cause the calling task to be preempted.
377
378This directive is only available on uni-processor configurations.  The
379directives ``rtems.interrupt_local_disable`` and``rtems.interrupt_local_enable`` is available on all
380configurations.
381
382INTERRUPT_LOCAL_DISABLE - Disable Interrupts on Current Processor
383-----------------------------------------------------------------
384.. index:: disable interrupts
385
386**CALLING SEQUENCE:**
387
388**DIRECTIVE STATUS CODES:**
389
390NONE
391
392**DESCRIPTION:**
393
394This directive disables all maskable interrupts and returns
395the previous ``level``.  A later invocation of the``rtems.interrupt_local_enable`` directive should be used to
396restore the interrupt level.
397
398**NOTES:**
399
400This directive will not cause the calling task to be preempted.
401
402On SMP configurations this will not ensure system wide mutual exclusion.  Use
403interrupt locks instead.
404
405INTERRUPT_LOCAL_ENABLE - Enable Interrupts on Current Processor
406---------------------------------------------------------------
407.. index:: enable interrupts
408
409**CALLING SEQUENCE:**
410
411**DIRECTIVE STATUS CODES:**
412
413NONE
414
415**DESCRIPTION:**
416
417This directive enables maskable interrupts to the ``level``
418which was returned by a previous call to``rtems.interrupt_local_disable``.
419Immediately prior to invoking this directive, maskable interrupts should
420be disabled by a call to ``rtems.interrupt_local_disable``
421and will be enabled when this directive returns to the caller.
422
423**NOTES:**
424
425This directive will not cause the calling task to be preempted.
426
427INTERRUPT_LOCK_INITIALIZE - Initialize an ISR Lock
428--------------------------------------------------
429
430**CALLING SEQUENCE:**
431
432**DIRECTIVE STATUS CODES:**
433
434NONE
435
436**DESCRIPTION:**
437
438Initializes an interrupt lock.
439
440**NOTES:**
441
442Concurrent initialization leads to unpredictable results.
443
444INTERRUPT_LOCK_ACQUIRE - Acquire an ISR Lock
445--------------------------------------------
446
447**CALLING SEQUENCE:**
448
449**DIRECTIVE STATUS CODES:**
450
451NONE
452
453**DESCRIPTION:**
454
455Interrupts will be disabled.  On SMP configurations this directive acquires a
456SMP lock.
457
458**NOTES:**
459
460This directive will not cause the calling thread to be preempted.  This
461directive can be used in thread and interrupt context.
462
463INTERRUPT_LOCK_RELEASE - Release an ISR Lock
464--------------------------------------------
465
466**CALLING SEQUENCE:**
467
468**DIRECTIVE STATUS CODES:**
469
470NONE
471
472**DESCRIPTION:**
473
474The interrupt status will be restored.  On SMP configurations this directive
475releases a SMP lock.
476
477**NOTES:**
478
479This directive will not cause the calling thread to be preempted.  This
480directive can be used in thread and interrupt context.
481
482INTERRUPT_LOCK_ACQUIRE_ISR - Acquire an ISR Lock from ISR
483---------------------------------------------------------
484
485**CALLING SEQUENCE:**
486
487**DIRECTIVE STATUS CODES:**
488
489NONE
490
491**DESCRIPTION:**
492
493The interrupt status will remain unchanged.  On SMP configurations this
494directive acquires a SMP lock.
495
496In case the corresponding interrupt service routine can be interrupted by
497higher priority interrupts and these interrupts enter the critical section
498protected by this lock, then the result is unpredictable.
499
500**NOTES:**
501
502This directive should be called from the corresponding interrupt service
503routine.
504
505INTERRUPT_LOCK_RELEASE_ISR - Release an ISR Lock from ISR
506---------------------------------------------------------
507
508**CALLING SEQUENCE:**
509
510**DIRECTIVE STATUS CODES:**
511
512NONE
513
514**DESCRIPTION:**
515
516The interrupt status will remain unchanged.  On SMP configurations this
517directive releases a SMP lock.
518
519**NOTES:**
520
521This directive should be called from the corresponding interrupt service
522routine.
523
524INTERRUPT_IS_IN_PROGRESS - Is an ISR in Progress
525------------------------------------------------
526.. index:: is interrupt in progress
527
528**CALLING SEQUENCE:**
529
530.. code:: c
531
532    function Interrupt_Is_In_Progress return RTEMS.Boolean;
533
534**DIRECTIVE STATUS CODES:**
535
536NONE
537
538**DESCRIPTION:**
539
540This directive returns ``TRUE`` if the processor is currently
541servicing an interrupt and ``FALSE`` otherwise.  A return value
542of ``TRUE`` indicates that the caller is an interrupt service
543routine, *NOT* a task.  The directives available to an interrupt
544service routine are restricted.
545
546**NOTES:**
547
548This directive will not cause the calling task to be preempted.
549
550.. COMMENT: COPYRIGHT (c) 1988-2008
551
552.. COMMENT: On-Line Applications Research Corporation (OAR).
553
554.. COMMENT: All rights reserved.
555
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