1 | /* mio_io.c WinSystems support module file for the PCM-MIO RTEMS driver |
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2 | * |
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3 | * $Id$ |
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4 | * |
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5 | * This file implements the hardware access routines as implemented for RTEMS. |
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6 | * This is very likely close to what is required with no OS. |
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7 | */ |
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8 | |
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9 | /* #define DEBUG 1 */ |
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10 | |
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11 | #include "mio_io.h" |
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12 | |
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13 | #include <stdio.h> |
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14 | #include <fcntl.h> /* open */ |
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15 | #include <unistd.h> /* exit */ |
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16 | #include <sys/ioctl.h> /* ioctl */ |
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17 | #include <stdlib.h> /* for exit */ |
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18 | |
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19 | #include <rtems.h> |
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20 | #include <i386_io.h> |
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21 | |
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22 | /* |
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23 | * These are configured by the initialization call. |
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24 | */ |
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25 | |
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26 | /* IRQ source or 0 ==> polled */ |
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27 | static unsigned short irq = 0; |
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28 | /* This holds the base addresses of the board */ |
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29 | static unsigned short base_port = 0; |
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30 | |
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31 | /* Function prototypes for local functions */ |
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32 | int get_buffered_int( |
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33 | unsigned long long *timestamp |
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34 | ); |
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35 | void init_io(unsigned short io_address); |
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36 | void clr_int(int bit_number); |
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37 | int get_int(void); |
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38 | |
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39 | /* RTEMS Ids for Wait Queues */ |
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40 | rtems_id wq_a2d_1; |
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41 | rtems_id wq_a2d_2; |
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42 | rtems_id wq_dac_1; |
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43 | rtems_id wq_dac_2; |
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44 | rtems_id wq_dio; |
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45 | |
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46 | void interruptible_sleep_on( |
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47 | rtems_id *id |
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48 | ); |
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49 | void wake_up_interruptible( |
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50 | rtems_id *id |
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51 | ); |
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52 | |
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53 | /////////////////////////////////////////////////////////////////////////////// |
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54 | // |
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55 | // MIO_READ_IRQ_ASSIGNED |
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56 | // |
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57 | ////////////////////////////////////////////////////////////////////////////// |
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58 | |
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59 | int mio_read_irq_assigned(void) |
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60 | { |
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61 | mio_error_code = MIO_SUCCESS; |
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62 | |
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63 | if (check_handle()) /* Check for chip available */ |
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64 | return -1; |
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65 | |
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66 | /* All of our programming of the hardware is handled at this level so that |
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67 | all of the routines that need to shove and IRQ value into hardware will |
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68 | use this call. |
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69 | */ |
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70 | |
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71 | return (irq & 0xff); |
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72 | } |
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73 | |
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74 | /////////////////////////////////////////////////////////////////////////////// |
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75 | // |
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76 | // READ_DIO_BYTE |
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77 | // |
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78 | ////////////////////////////////////////////////////////////////////////////// |
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79 | |
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80 | unsigned char read_dio_byte(int offset) |
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81 | { |
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82 | unsigned char byte_val; |
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83 | unsigned char offset_val; |
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84 | |
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85 | mio_error_code = MIO_SUCCESS; |
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86 | |
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87 | if (check_handle()) /* Check for chip available */ |
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88 | return -1; |
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89 | |
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90 | /* All bit operations are handled at this level so we need only |
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91 | read and write bytes from the actual hardware. |
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92 | */ |
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93 | |
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94 | offset_val = offset & 0xff; |
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95 | byte_val = inb(base_port + 0x10 + offset_val); |
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96 | return (byte_val & 0xff); |
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97 | } |
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98 | |
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99 | /////////////////////////////////////////////////////////////////////////////// |
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100 | // |
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101 | // MIO_READ_REG |
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102 | // |
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103 | ////////////////////////////////////////////////////////////////////////////// |
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104 | |
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105 | unsigned char mio_read_reg(int offset) |
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106 | { |
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107 | unsigned char byte_val; |
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108 | unsigned char offset_val; |
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109 | |
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110 | mio_error_code = MIO_SUCCESS; |
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111 | |
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112 | if (check_handle()) /* Check for chip available */ |
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113 | return -1; |
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114 | |
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115 | |
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116 | /* This is a catchall register read routine that allows reading of |
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117 | ANY of the registers on the PCM-MIO. It is used primarily for |
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118 | retreiving control and access values in the hardware. |
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119 | */ |
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120 | |
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121 | offset_val = offset & 0xff; |
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122 | byte_val = inb(base_port + offset_val); |
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123 | return (byte_val & 0xff); |
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124 | } |
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125 | |
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126 | /////////////////////////////////////////////////////////////////////////////// |
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127 | // |
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128 | // MIO_WRITE_REG |
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129 | // |
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130 | ////////////////////////////////////////////////////////////////////////////// |
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131 | |
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132 | int mio_write_reg(int offset, unsigned char value) |
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133 | { |
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134 | unsigned char byte_val; |
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135 | unsigned char offset_val; |
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136 | |
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137 | mio_error_code = MIO_SUCCESS; |
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138 | |
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139 | if (check_handle()) /* Check for chip available */ |
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140 | return -1; |
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141 | |
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142 | /* This function like the previous allow unlimited |
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143 | write access to ALL of the registers on the PCM-MIO |
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144 | */ |
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145 | |
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146 | offset_val = offset & 0xff; |
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147 | byte_val = value; |
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148 | outb(byte_val, base_port + offset_val); |
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149 | |
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150 | return 0; |
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151 | } |
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152 | |
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153 | |
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154 | /////////////////////////////////////////////////////////////////////////////// |
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155 | // |
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156 | // WRITE_DIO_BYTE |
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157 | // |
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158 | ////////////////////////////////////////////////////////////////////////////// |
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159 | |
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160 | int write_dio_byte(int offset, unsigned char value) |
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161 | { |
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162 | unsigned char byte_val; |
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163 | unsigned char offset_val; |
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164 | |
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165 | mio_error_code = MIO_SUCCESS; |
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166 | |
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167 | if (check_handle()) /* Check for chip available */ |
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168 | return -1; |
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169 | |
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170 | /* All bit operations for the DIO are handled at this level |
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171 | and we need the driver to allow access to the actual |
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172 | DIO registers to update the value. |
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173 | */ |
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174 | |
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175 | offset_val = offset & 0xff; |
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176 | byte_val = value; |
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177 | outb(byte_val, base_port + 0x10 + offset_val); |
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178 | |
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179 | return 0; |
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180 | } |
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181 | |
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182 | |
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183 | /////////////////////////////////////////////////////////////////////////////// |
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184 | // |
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185 | // WRITE_DAC_COMMAND |
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186 | // |
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187 | ////////////////////////////////////////////////////////////////////////////// |
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188 | |
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189 | int write_dac_command(int dac_num,unsigned char value) |
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190 | { |
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191 | unsigned char byte_val; |
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192 | unsigned char offset_val; |
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193 | |
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194 | mio_error_code = MIO_SUCCESS; |
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195 | |
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196 | if (check_handle()) /* Check for chip available */ |
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197 | return -1; |
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198 | |
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199 | byte_val = dac_num & 0xff; /* This is the DAC number */ |
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200 | offset_val = value; /* This is the data value */ |
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201 | if (byte_val) |
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202 | outb(offset_val,base_port + 0x0e); |
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203 | else |
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204 | outb(offset_val,base_port + 0x0a); |
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205 | |
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206 | return 0; |
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207 | } |
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208 | |
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209 | /////////////////////////////////////////////////////////////////////////////// |
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210 | // |
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211 | // WRITE_ADC_COMMAND |
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212 | // |
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213 | ////////////////////////////////////////////////////////////////////////////// |
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214 | |
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215 | int write_adc_command(int adc_num,unsigned char value) |
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216 | { |
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217 | unsigned char byte_val; |
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218 | unsigned char offset_val; |
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219 | |
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220 | mio_error_code = MIO_SUCCESS; |
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221 | |
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222 | if (check_handle()) /* Check for chip available */ |
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223 | return -1; |
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224 | |
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225 | byte_val = adc_num & 0xff; /* This is the ADC number */ |
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226 | offset_val = value; /* This is the data value */ |
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227 | |
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228 | if(byte_val) |
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229 | outb(offset_val,base_port + 0x06); |
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230 | else |
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231 | outb(offset_val,base_port + 0x02); |
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232 | return 0; |
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233 | } |
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234 | |
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235 | /////////////////////////////////////////////////////////////////////////////// |
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236 | // |
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237 | // WRITE_DAC_DATA |
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238 | // |
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239 | ////////////////////////////////////////////////////////////////////////////// |
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240 | |
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241 | int write_dac_data(int dac_num, unsigned short value) |
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242 | { |
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243 | unsigned short word_val; |
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244 | unsigned char byte_val; |
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245 | |
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246 | mio_error_code = MIO_SUCCESS; |
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247 | |
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248 | if (check_handle()) /* Check for chip available */ |
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249 | return -1; |
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250 | |
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251 | byte_val = dac_num; |
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252 | word_val = value; |
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253 | |
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254 | if(byte_val) /* DAC 1 */ |
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255 | outw(word_val,base_port+0x0c); |
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256 | else |
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257 | outw(word_val,base_port+8); |
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258 | |
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259 | return 0; |
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260 | } |
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261 | |
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262 | /////////////////////////////////////////////////////////////////////////////// |
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263 | // |
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264 | // DAC_READ_STATUS |
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265 | // |
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266 | ////////////////////////////////////////////////////////////////////////////// |
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267 | |
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268 | unsigned char dac_read_status(int dac_num) |
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269 | { |
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270 | mio_error_code = MIO_SUCCESS; |
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271 | |
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272 | if (check_handle()) /* Check for chip available */ |
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273 | return -1; |
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274 | |
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275 | if (dac_num) |
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276 | return inb(base_port + 0x0f); |
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277 | |
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278 | return inb(base_port + 0x0b); |
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279 | } |
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280 | |
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281 | /////////////////////////////////////////////////////////////////////////////// |
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282 | // |
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283 | // ADC_READ_STATUS |
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284 | // |
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285 | ////////////////////////////////////////////////////////////////////////////// |
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286 | |
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287 | unsigned char adc_read_status(int adc_num) |
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288 | { |
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289 | mio_error_code = MIO_SUCCESS; |
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290 | |
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291 | if (check_handle()) /* Check for chip available */ |
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292 | return -1; |
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293 | |
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294 | if (adc_num) |
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295 | return inb(base_port + 7); |
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296 | return inb(base_port + 3); |
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297 | } |
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298 | |
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299 | /////////////////////////////////////////////////////////////////////////////// |
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300 | // |
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301 | // ADC_READ_CONVERSION_DATA |
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302 | // |
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303 | ////////////////////////////////////////////////////////////////////////////// |
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304 | |
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305 | unsigned short adc_read_conversion_data(int channel) |
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306 | { |
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307 | int adc_num; |
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308 | |
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309 | mio_error_code = MIO_SUCCESS; |
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310 | |
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311 | if (check_handle()) /* Check for chip available */ |
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312 | return -1; |
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313 | |
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314 | if (channel > 7) |
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315 | adc_num = 1; |
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316 | else |
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317 | adc_num = 0; |
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318 | |
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319 | if (adc_num) |
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320 | return inw(base_port + 4); |
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321 | |
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322 | return inw(base_port); |
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323 | } |
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324 | |
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325 | |
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326 | int dio_get_int_with_timestamp( |
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327 | unsigned long long *timestamp |
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328 | ) |
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329 | { |
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330 | if (check_handle()) /* Check for chip available */ |
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331 | return -1; |
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332 | |
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333 | return get_buffered_int(timestamp) & 0xff; |
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334 | } |
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335 | |
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336 | int dio_get_int(void) |
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337 | { |
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338 | return dio_get_int_with_timestamp(NULL); |
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339 | } |
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340 | |
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341 | int wait_adc_int(int adc_num) |
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342 | { |
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343 | if (check_handle()) /* Check for chip available */ |
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344 | return -1; |
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345 | |
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346 | if (adc_num) { |
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347 | interruptible_sleep_on(&wq_a2d_1); |
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348 | } else { |
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349 | interruptible_sleep_on(&wq_a2d_2); |
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350 | } |
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351 | |
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352 | return 0; |
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353 | } |
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354 | |
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355 | |
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356 | int wait_dac_int(int dac_num) |
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357 | { |
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358 | if (check_handle()) /* Check for chip available */ |
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359 | return -1; |
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360 | |
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361 | if (dac_num) { |
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362 | interruptible_sleep_on(&wq_dac_1); |
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363 | } else { |
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364 | interruptible_sleep_on(&wq_dac_2); |
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365 | } |
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366 | |
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367 | return 0; |
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368 | } |
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369 | |
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370 | |
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371 | int wait_dio_int(void) |
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372 | { |
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373 | int i; |
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374 | |
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375 | if (check_handle()) /* Check for chip available */ |
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376 | return -1; |
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377 | |
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378 | if((i = get_buffered_int(NULL))) |
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379 | return i; |
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380 | |
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381 | interruptible_sleep_on(&wq_dio); |
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382 | |
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383 | i = get_buffered_int(NULL); |
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384 | |
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385 | return i; |
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386 | } |
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387 | |
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388 | |
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389 | static int handle = 0; /* XXX move to lower */ |
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390 | |
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391 | int check_handle(void) |
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392 | { |
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393 | if (handle > 0) /* If it's already a valid handle */ |
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394 | return 0; |
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395 | |
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396 | if (handle == -1) /* If it's already been tried */ |
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397 | { |
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398 | mio_error_code = MIO_OPEN_ERROR; |
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399 | sprintf(mio_error_string,"MIO - Unable to open device PCMMIO"); |
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400 | return -1; |
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401 | } |
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402 | |
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403 | /* |
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404 | * 0 ==> not initialized |
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405 | * 1+ ==> valid file handle, thus initialized |
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406 | * -1 ==> already attempted to open |
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407 | */ |
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408 | handle = 1; |
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409 | return 0; |
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410 | |
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411 | /* if an error happens, go here */ |
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412 | mio_error_code = MIO_OPEN_ERROR; |
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413 | sprintf(mio_error_string,"MIO - Unable to open device PCMMIO"); |
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414 | handle = -1; |
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415 | return -1; |
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416 | } |
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417 | |
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418 | /* |
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419 | * RTEMS barrier create helper |
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420 | */ |
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421 | void pcmmio_barrier_create( |
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422 | rtems_name name, |
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423 | rtems_id *id |
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424 | ) |
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425 | { |
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426 | rtems_status_code rc; |
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427 | |
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428 | rc = rtems_barrier_create( name, RTEMS_BARRIER_MANUAL_RELEASE, 0, id ); |
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429 | if ( rc == RTEMS_SUCCESSFUL ) |
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430 | return; |
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431 | |
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432 | printk( "Unable to create PCMMIO Barrier\n" ); |
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433 | exit(1); |
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434 | } |
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435 | |
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436 | void interruptible_sleep_on( |
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437 | rtems_id *id |
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438 | ) |
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439 | { |
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440 | rtems_status_code rc; |
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441 | |
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442 | rc = rtems_barrier_wait(*id, 0); |
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443 | } |
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444 | |
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445 | void wake_up_interruptible( |
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446 | rtems_id *id |
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447 | ) |
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448 | { |
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449 | rtems_status_code rc; |
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450 | uint32_t unblocked; |
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451 | |
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452 | rc = rtems_barrier_release(*id, &unblocked); |
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453 | } |
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454 | |
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455 | /* |
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456 | * RTEMS specific interrupt handler |
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457 | */ |
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458 | #include <bsp/irq.h> |
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459 | |
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460 | void common_handler(void); |
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461 | |
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462 | void pcmmio_irq_handler( |
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463 | rtems_irq_hdl_param param |
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464 | ) |
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465 | { |
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466 | common_handler(); |
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467 | } |
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468 | |
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469 | static void pcmmio_irq_disable(const rtems_irq_connect_data *irq) |
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470 | { |
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471 | BSP_irq_disable_at_i8259s(irq->name - BSP_IRQ_VECTOR_BASE); |
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472 | } |
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473 | static void pcmmio_irq_enable(const rtems_irq_connect_data *irq) |
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474 | { |
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475 | BSP_irq_enable_at_i8259s(irq->name - BSP_IRQ_VECTOR_BASE); |
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476 | } |
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477 | |
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478 | static int pcmmio_irq_is_on(const rtems_irq_connect_data *irq) |
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479 | { |
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480 | return BSP_irq_enabled_at_i8259s( irq->name ); |
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481 | } |
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482 | |
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483 | rtems_irq_connect_data pcmmio_irq = { |
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484 | 0, // name |
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485 | pcmmio_irq_handler, // handler |
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486 | NULL, // parameter |
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487 | pcmmio_irq_enable, // enable IRQ |
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488 | pcmmio_irq_disable, // disable IRQ |
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489 | pcmmio_irq_is_on, // is IRQ enabled |
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490 | }; |
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491 | |
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492 | /* |
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493 | * RTEMS specific initialization routine |
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494 | */ |
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495 | void pcmmio_initialize( |
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496 | unsigned short _base_port, |
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497 | unsigned short _irq |
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498 | ) |
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499 | { |
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500 | /* hardware configuration information */ |
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501 | base_port = _base_port; |
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502 | irq = _irq; |
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503 | |
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504 | /* Create RTEMS Objects */ |
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505 | pcmmio_barrier_create( rtems_build_name( 'a', '2', 'd', '1' ), &wq_a2d_1 ); |
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506 | pcmmio_barrier_create( rtems_build_name( 'd', 'a', 'c', '1' ), &wq_dac_1 ); |
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507 | pcmmio_barrier_create( rtems_build_name( 'd', 'a', 'c', '2' ), &wq_dac_2 ); |
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508 | pcmmio_barrier_create( rtems_build_name( 'd', 'i', 'o', ' ' ), &wq_dio ); |
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509 | |
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510 | /* install IRQ handler */ |
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511 | if ( irq ) { |
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512 | int status = 0; |
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513 | pcmmio_irq.name = irq; |
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514 | #if defined(BSP_SHARED_HANDLER_SUPPORT) |
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515 | BSP_install_rtems_shared_irq_handler( &pcmmio_irq ); |
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516 | #else |
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517 | printk( "PCMMIO Installing IRQ handler as non-shared\n" ); |
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518 | BSP_install_rtems_irq_handler( &pcmmio_irq ); |
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519 | #endif |
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520 | if ( !status ) { |
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521 | printk("Error installing PCMMIO interrupt handler!\n" ); |
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522 | rtems_fatal_error_occurred( status ); |
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523 | } |
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524 | } |
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525 | } |
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526 | |
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527 | #include <libcpu/cpuModel.h> /* for rdtsc */ |
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528 | |
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529 | /* |
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530 | * From this point down, we should be able to share easily with the Linux |
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531 | * driver but I haven't gone to the trouble to do surgery on it. I have |
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532 | * no way to test it. |
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533 | */ |
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534 | |
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535 | /* We will buffer up the transition interrupts and will pass them on |
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536 | to waiting applications |
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537 | */ |
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538 | |
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539 | #define MAX_INTS 1024 |
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540 | |
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541 | typedef struct { |
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542 | unsigned char line; |
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543 | unsigned long long timestamp; |
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544 | } DIO_Int_t; |
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545 | |
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546 | static DIO_Int_t int_buffer[MAX_INTS]; |
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547 | static int inptr = 0; |
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548 | static int outptr = 0; |
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549 | |
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550 | /* real copy is in mio_io.c */ |
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551 | extern unsigned char adc2_port_image; |
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552 | |
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553 | /* This is the common interrupt handler. It is called by the |
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554 | * actual hardware ISR. |
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555 | */ |
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556 | |
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557 | void common_handler(void) |
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558 | { |
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559 | unsigned char status; |
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560 | unsigned char int_num; |
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561 | |
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562 | /* Read the interrupt ID register from ADC2 */ |
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563 | |
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564 | adc2_port_image = adc2_port_image | 0x20; |
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565 | outb(adc2_port_image,base_port + 0x0f); |
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566 | |
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567 | status = inb(base_port + 0x0f); |
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568 | if (status & 1) { |
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569 | /* Clear ADC1 interrupt */ |
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570 | inb(base_port+1); /* Clear interrupt */ |
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571 | |
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572 | /* Wake up any holding processes */ |
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573 | wake_up_interruptible(&wq_a2d_1); |
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574 | } |
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575 | |
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576 | if (status & 2) { |
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577 | /* Clear ADC1 interrupt */ |
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578 | inb(base_port+5); /* Clear interrupt */ |
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579 | |
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580 | /* Wake up anybody waiting for ADC1 */ |
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581 | wake_up_interruptible(&wq_a2d_2); |
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582 | } |
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583 | |
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584 | if (status & 4) { |
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585 | /* Clear DAC1 interrupt */ |
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586 | inb(base_port+9); /* Clear interrupt */ |
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587 | |
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588 | /* Wake up if you're waiting on DAC1 */ |
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589 | wake_up_interruptible(&wq_dac_1); |
---|
590 | } |
---|
591 | |
---|
592 | if (status & 8) { |
---|
593 | |
---|
594 | /* DIO interrupt. Find out which bit */ |
---|
595 | int_num = get_int(); |
---|
596 | if (int_num) { |
---|
597 | #ifdef DEBUG |
---|
598 | printk("<1>Buffering DIO interrupt on bit %d\n",int_num); |
---|
599 | #endif |
---|
600 | |
---|
601 | /* |
---|
602 | * Buffer the interrupt |
---|
603 | * |
---|
604 | * NOTE: No need to worry about disabling interrupts, |
---|
605 | * we are in interrupts. |
---|
606 | */ |
---|
607 | |
---|
608 | int_buffer[inptr].timestamp = rdtsc(); |
---|
609 | int_buffer[inptr].line = int_num; |
---|
610 | inptr++; |
---|
611 | if (inptr == MAX_INTS) |
---|
612 | inptr = 0; |
---|
613 | |
---|
614 | /* Clear the interrupt */ |
---|
615 | clr_int(int_num); |
---|
616 | } |
---|
617 | |
---|
618 | /* Wake up anybody waiting for a DIO interrupt */ |
---|
619 | wake_up_interruptible(&wq_dio); |
---|
620 | } |
---|
621 | |
---|
622 | if (status & 0x10) { |
---|
623 | /* Clear DAC2 Interrupt */ |
---|
624 | inb(base_port+0x0d); /* Clear interrupt */ |
---|
625 | |
---|
626 | /* Wake up DAC2 holding processes */ |
---|
627 | wake_up_interruptible(&wq_dac_2); |
---|
628 | } |
---|
629 | |
---|
630 | /* Reset the access to the interrupt ID register */ |
---|
631 | adc2_port_image = adc2_port_image & 0xdf; |
---|
632 | outb(adc2_port_image,base_port+0x0f); |
---|
633 | } |
---|
634 | |
---|
635 | |
---|
636 | void clr_int(int bit_number) |
---|
637 | { |
---|
638 | unsigned short port; |
---|
639 | unsigned short temp; |
---|
640 | unsigned short mask; |
---|
641 | unsigned short dio_port; |
---|
642 | |
---|
643 | dio_port = base_port + 0x10; |
---|
644 | |
---|
645 | /* Also adjust bit number */ |
---|
646 | --bit_number; |
---|
647 | |
---|
648 | /* Calculate the I/O address based upon bit number */ |
---|
649 | port = (bit_number / 8) + dio_port + 8; |
---|
650 | |
---|
651 | /* Calculate a bit mask based upon the specified bit number */ |
---|
652 | mask = (1 << (bit_number % 8)); |
---|
653 | |
---|
654 | /* Turn on page 2 access */ |
---|
655 | outb(0x80,dio_port+7); |
---|
656 | |
---|
657 | /* Get the current state of the interrupt enable register */ |
---|
658 | temp = inb(port); |
---|
659 | |
---|
660 | /* Temporarily clear only our enable. This clears the interrupt */ |
---|
661 | temp = temp & ~mask; /* Clear the enable for this bit */ |
---|
662 | |
---|
663 | /* Now update the interrupt enable register */ |
---|
664 | outb(temp,port); |
---|
665 | |
---|
666 | /* Re-enable our interrupt bit */ |
---|
667 | temp = temp | mask; |
---|
668 | outb(temp,port); |
---|
669 | |
---|
670 | /* Set access back to page 0 */ |
---|
671 | outb(0x00,dio_port+7); |
---|
672 | } |
---|
673 | |
---|
674 | int get_int(void) |
---|
675 | { |
---|
676 | int temp; |
---|
677 | int x; |
---|
678 | unsigned short dio_port; |
---|
679 | |
---|
680 | dio_port = base_port + 0x10; |
---|
681 | |
---|
682 | /* Read the master interrupt pending register, |
---|
683 | mask off undefined bits */ |
---|
684 | temp = inb(dio_port+6) & 0x07; |
---|
685 | |
---|
686 | /* If there are no pending interrupts, return 0 */ |
---|
687 | if ((temp & 7) == 0) |
---|
688 | return 0; |
---|
689 | |
---|
690 | /* There is something pending, now we need to identify it */ |
---|
691 | |
---|
692 | /* Set access to page 3 for interrupt id register */ |
---|
693 | outb(0xc0, dio_port + 7); |
---|
694 | |
---|
695 | /* Read the interrupt ID register for port 0 */ |
---|
696 | temp = inb(dio_port+8); |
---|
697 | |
---|
698 | /* See if any bit set, if so return the bit number */ |
---|
699 | if (temp != 0) { |
---|
700 | for (x=0; x<=7; x++) { |
---|
701 | if (temp & (1 << x)) { |
---|
702 | outb(0,dio_port+7); |
---|
703 | return(x+1); |
---|
704 | } |
---|
705 | } |
---|
706 | } |
---|
707 | |
---|
708 | /* None in port 0, read port 1 interrupt ID register */ |
---|
709 | temp = inb(dio_port+9); |
---|
710 | |
---|
711 | /* See if any bit set, if so return the bit number */ |
---|
712 | if (temp != 0) { |
---|
713 | for (x=0; x<=7; x++) { |
---|
714 | if (temp & (1 << x)) { |
---|
715 | outb(0,dio_port+7); |
---|
716 | return(x+9); |
---|
717 | } |
---|
718 | } |
---|
719 | } |
---|
720 | |
---|
721 | /* Lastly, read the status of port 2 interrupt ID register */ |
---|
722 | temp = inb(dio_port+0x0a); |
---|
723 | |
---|
724 | /* If any pending, return the appropriate bit number */ |
---|
725 | if (temp != 0) { |
---|
726 | for (x=0; x<=7; x++) { |
---|
727 | if (temp & (1 << x)) { |
---|
728 | outb(0,dio_port+7); |
---|
729 | return(x+17); |
---|
730 | } |
---|
731 | } |
---|
732 | } |
---|
733 | |
---|
734 | /* We should never get here unless the hardware is seriously |
---|
735 | misbehaving, but just to be sure, we'll turn the page access |
---|
736 | back to 0 and return a 0 for no interrupt found |
---|
737 | */ |
---|
738 | outb(0,dio_port+7); |
---|
739 | return 0; |
---|
740 | } |
---|
741 | |
---|
742 | int get_buffered_int( |
---|
743 | unsigned long long *timestamp |
---|
744 | ) |
---|
745 | { |
---|
746 | rtems_interrupt_level level; |
---|
747 | int line; |
---|
748 | |
---|
749 | if (irq == 0) { |
---|
750 | line = get_int(); |
---|
751 | if (line) |
---|
752 | clr_int(line); |
---|
753 | return line; |
---|
754 | } |
---|
755 | |
---|
756 | line = 0; |
---|
757 | |
---|
758 | rtems_interrupt_disable( level ); |
---|
759 | if (outptr != inptr) { |
---|
760 | if ( timestamp ) |
---|
761 | *timestamp = int_buffer[outptr].timestamp; |
---|
762 | line = int_buffer[outptr].line; |
---|
763 | outptr++; |
---|
764 | if (outptr == MAX_INTS) |
---|
765 | outptr = 0; |
---|
766 | } |
---|
767 | rtems_interrupt_enable( level ); |
---|
768 | |
---|
769 | return line; |
---|
770 | } |
---|