[6f4d6bd] | 1 | /* mio_io.c WinSystems support module file for the PCM-MIO RTEMS driver */ |
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[c99627b] | 2 | /* |
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[6f4d6bd] | 3 | * $Id$ |
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| 4 | * |
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| 5 | * This file implements the hardware access routines as implemented for RTEMS. |
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| 6 | * This is very likely close to what is required with no OS. |
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| 7 | */ |
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[c99627b] | 8 | |
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| 9 | /* #define DEBUG 1 */ |
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| 10 | |
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| 11 | #include "mio_io.h" |
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| 12 | |
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| 13 | #include <stdio.h> |
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| 14 | #include <fcntl.h> /* open */ |
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| 15 | #include <unistd.h> /* exit */ |
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| 16 | #include <sys/ioctl.h> /* ioctl */ |
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[2fc4157] | 17 | #include <stdlib.h> /* for exit */ |
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[c99627b] | 18 | |
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[2fc4157] | 19 | #include <rtems.h> |
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[6f4d6bd] | 20 | #include <i386_io.h> |
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| 21 | |
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| 22 | /* |
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[2fc4157] | 23 | * These are configured by the initialization call. |
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[6f4d6bd] | 24 | */ |
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| 25 | |
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| 26 | /* IRQ source or 0 ==> polled */ |
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| 27 | static unsigned short irq = 0; |
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| 28 | /* This holds the base addresses of the board */ |
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| 29 | static unsigned short base_port = 0; |
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| 30 | |
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| 31 | /* Function prototypes for local functions */ |
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| 32 | int get_buffered_int(void); |
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| 33 | void init_io(unsigned short io_address); |
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| 34 | void clr_int(int bit_number); |
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| 35 | int get_int(void); |
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[c99627b] | 36 | |
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[2fc4157] | 37 | /* RTEMS Ids for Wait Queues */ |
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| 38 | rtems_id wq_a2d_1; |
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| 39 | rtems_id wq_a2d_2; |
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| 40 | rtems_id wq_dac_1; |
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| 41 | rtems_id wq_dac_2; |
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| 42 | rtems_id wq_dio; |
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| 43 | |
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| 44 | void interruptible_sleep_on( |
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| 45 | rtems_id *id |
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| 46 | ); |
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| 47 | void wake_up_interruptible( |
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| 48 | rtems_id *id |
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| 49 | ); |
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| 50 | |
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[c99627b] | 51 | /////////////////////////////////////////////////////////////////////////////// |
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| 52 | // |
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[6f4d6bd] | 53 | // MIO_READ_IRQ_ASSIGNED |
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[c99627b] | 54 | // |
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| 55 | ////////////////////////////////////////////////////////////////////////////// |
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| 56 | |
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| 57 | int mio_read_irq_assigned(void) |
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| 58 | { |
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[6f4d6bd] | 59 | mio_error_code = MIO_SUCCESS; |
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[c99627b] | 60 | |
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[6f4d6bd] | 61 | if (check_handle()) /* Check for chip available */ |
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| 62 | return -1; |
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[c99627b] | 63 | |
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| 64 | |
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[6f4d6bd] | 65 | /* All of our programming of the hardware is handled at this level so that |
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| 66 | all of the routines that need to shove and IRQ value into hardware will |
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| 67 | use this call. |
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| 68 | */ |
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[c99627b] | 69 | |
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[6f4d6bd] | 70 | return (irq & 0xff); |
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[c99627b] | 71 | } |
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| 72 | |
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| 73 | /////////////////////////////////////////////////////////////////////////////// |
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| 74 | // |
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[6f4d6bd] | 75 | // READ_DIO_BYTE |
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[c99627b] | 76 | // |
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| 77 | ////////////////////////////////////////////////////////////////////////////// |
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| 78 | |
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| 79 | unsigned char read_dio_byte(int offset) |
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| 80 | { |
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[6f4d6bd] | 81 | unsigned char byte_val; |
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| 82 | unsigned char offset_val; |
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[c99627b] | 83 | |
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[6f4d6bd] | 84 | mio_error_code = MIO_SUCCESS; |
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[c99627b] | 85 | |
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[6f4d6bd] | 86 | if (check_handle()) /* Check for chip available */ |
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| 87 | return -1; |
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[c99627b] | 88 | |
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[6f4d6bd] | 89 | /* All bit operations are handled at this level so we need only |
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| 90 | read and write bytes from the actual hardware. |
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| 91 | */ |
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[c99627b] | 92 | |
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[6f4d6bd] | 93 | offset_val = offset & 0xff; |
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| 94 | byte_val = inb(base_port + 0x10 + offset_val); |
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| 95 | return (byte_val & 0xff); |
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[c99627b] | 96 | } |
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| 97 | |
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| 98 | /////////////////////////////////////////////////////////////////////////////// |
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| 99 | // |
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[6f4d6bd] | 100 | // MIO_READ_REG |
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[c99627b] | 101 | // |
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| 102 | ////////////////////////////////////////////////////////////////////////////// |
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| 103 | |
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| 104 | unsigned char mio_read_reg(int offset) |
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| 105 | { |
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[6f4d6bd] | 106 | unsigned char byte_val; |
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| 107 | unsigned char offset_val; |
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[c99627b] | 108 | |
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[6f4d6bd] | 109 | mio_error_code = MIO_SUCCESS; |
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[c99627b] | 110 | |
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[6f4d6bd] | 111 | if (check_handle()) /* Check for chip available */ |
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| 112 | return -1; |
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[c99627b] | 113 | |
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| 114 | |
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[6f4d6bd] | 115 | /* This is a catchall register read routine that allows reading of |
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| 116 | ANY of the registers on the PCM-MIO. It is used primarily for |
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| 117 | retreiving control and access values in the hardware. |
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[c99627b] | 118 | */ |
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| 119 | |
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[6f4d6bd] | 120 | offset_val = offset & 0xff; |
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| 121 | byte_val = inb(base_port + offset_val); |
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| 122 | return (byte_val & 0xff); |
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[c99627b] | 123 | } |
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| 124 | |
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| 125 | /////////////////////////////////////////////////////////////////////////////// |
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| 126 | // |
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[6f4d6bd] | 127 | // MIO_WRITE_REG |
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[c99627b] | 128 | // |
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| 129 | ////////////////////////////////////////////////////////////////////////////// |
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| 130 | |
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| 131 | int mio_write_reg(int offset, unsigned char value) |
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| 132 | { |
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[6f4d6bd] | 133 | unsigned char byte_val; |
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| 134 | unsigned char offset_val; |
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[c99627b] | 135 | |
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[6f4d6bd] | 136 | mio_error_code = MIO_SUCCESS; |
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[c99627b] | 137 | |
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[6f4d6bd] | 138 | if (check_handle()) /* Check for chip available */ |
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| 139 | return -1; |
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[c99627b] | 140 | |
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[6f4d6bd] | 141 | /* This function like the previous allow unlimited |
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| 142 | write access to ALL of the registers on the PCM-MIO |
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[c99627b] | 143 | */ |
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| 144 | |
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[6f4d6bd] | 145 | offset_val = offset & 0xff; |
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| 146 | byte_val = value; |
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| 147 | outb(byte_val, base_port + offset_val); |
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| 148 | |
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| 149 | return 0; |
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[c99627b] | 150 | } |
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| 151 | |
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| 152 | |
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| 153 | /////////////////////////////////////////////////////////////////////////////// |
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| 154 | // |
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[6f4d6bd] | 155 | // WRITE_DIO_BYTE |
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[c99627b] | 156 | // |
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| 157 | ////////////////////////////////////////////////////////////////////////////// |
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| 158 | |
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| 159 | int write_dio_byte(int offset, unsigned char value) |
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| 160 | { |
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[6f4d6bd] | 161 | unsigned char byte_val; |
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| 162 | unsigned char offset_val; |
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[c99627b] | 163 | |
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[6f4d6bd] | 164 | mio_error_code = MIO_SUCCESS; |
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[c99627b] | 165 | |
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[6f4d6bd] | 166 | if (check_handle()) /* Check for chip available */ |
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| 167 | return -1; |
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[c99627b] | 168 | |
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[6f4d6bd] | 169 | /* All bit operations for the DIO are handled at this level |
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| 170 | and we need the driver to allow access to the actual |
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| 171 | DIO registers to update the value. |
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| 172 | */ |
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[c99627b] | 173 | |
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[6f4d6bd] | 174 | offset_val = offset & 0xff; |
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| 175 | byte_val = value; |
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| 176 | outb(byte_val, base_port + 0x10 + offset_val); |
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[c99627b] | 177 | |
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[6f4d6bd] | 178 | return 0; |
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[c99627b] | 179 | } |
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| 180 | |
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| 181 | |
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| 182 | /////////////////////////////////////////////////////////////////////////////// |
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| 183 | // |
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[6f4d6bd] | 184 | // WRITE_DAC_COMMAND |
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[c99627b] | 185 | // |
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| 186 | ////////////////////////////////////////////////////////////////////////////// |
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| 187 | |
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| 188 | int write_dac_command(int dac_num,unsigned char value) |
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| 189 | { |
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[6f4d6bd] | 190 | unsigned char byte_val; |
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| 191 | unsigned char offset_val; |
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[c99627b] | 192 | |
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[6f4d6bd] | 193 | mio_error_code = MIO_SUCCESS; |
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[c99627b] | 194 | |
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[6f4d6bd] | 195 | if (check_handle()) /* Check for chip available */ |
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| 196 | return -1; |
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[c99627b] | 197 | |
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[6f4d6bd] | 198 | byte_val = dac_num & 0xff; /* This is the DAC number */ |
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| 199 | offset_val = value; /* This is the data value */ |
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| 200 | if (byte_val) |
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| 201 | outb(offset_val,base_port + 0x0e); |
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| 202 | else |
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| 203 | outb(offset_val,base_port + 0x0a); |
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[c99627b] | 204 | |
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[6f4d6bd] | 205 | return 0; |
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[c99627b] | 206 | } |
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| 207 | |
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| 208 | /////////////////////////////////////////////////////////////////////////////// |
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| 209 | // |
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[6f4d6bd] | 210 | // WRITE_ADC_COMMAND |
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[c99627b] | 211 | // |
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| 212 | ////////////////////////////////////////////////////////////////////////////// |
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| 213 | |
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| 214 | int write_adc_command(int adc_num,unsigned char value) |
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| 215 | { |
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[6f4d6bd] | 216 | unsigned char byte_val; |
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| 217 | unsigned char offset_val; |
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[c99627b] | 218 | |
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[6f4d6bd] | 219 | mio_error_code = MIO_SUCCESS; |
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[c99627b] | 220 | |
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[6f4d6bd] | 221 | if (check_handle()) /* Check for chip available */ |
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| 222 | return -1; |
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[c99627b] | 223 | |
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[6f4d6bd] | 224 | byte_val = adc_num & 0xff; /* This is the ADC number */ |
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| 225 | offset_val = value; /* This is the data value */ |
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[c99627b] | 226 | |
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[6f4d6bd] | 227 | if(byte_val) |
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| 228 | outb(offset_val,base_port + 0x06); |
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| 229 | else |
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| 230 | outb(offset_val,base_port + 0x02); |
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| 231 | return 0; |
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[c99627b] | 232 | } |
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| 233 | |
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| 234 | /////////////////////////////////////////////////////////////////////////////// |
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| 235 | // |
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[6f4d6bd] | 236 | // WRITE_DAC_DATA |
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[c99627b] | 237 | // |
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| 238 | ////////////////////////////////////////////////////////////////////////////// |
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| 239 | |
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| 240 | int write_dac_data(int dac_num, unsigned short value) |
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| 241 | { |
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[6f4d6bd] | 242 | unsigned short word_val; |
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| 243 | unsigned char byte_val; |
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[c99627b] | 244 | |
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[6f4d6bd] | 245 | mio_error_code = MIO_SUCCESS; |
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[c99627b] | 246 | |
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[6f4d6bd] | 247 | if (check_handle()) /* Check for chip available */ |
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| 248 | return -1; |
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[c99627b] | 249 | |
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[6f4d6bd] | 250 | byte_val = dac_num; |
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| 251 | word_val = value; |
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[c99627b] | 252 | |
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[6f4d6bd] | 253 | if(byte_val) /* DAC 1 */ |
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| 254 | outw(word_val,base_port+0x0c); |
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| 255 | else |
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| 256 | outw(word_val,base_port+8); |
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| 257 | |
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| 258 | return 0; |
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[c99627b] | 259 | } |
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| 260 | |
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| 261 | /////////////////////////////////////////////////////////////////////////////// |
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| 262 | // |
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[6f4d6bd] | 263 | // DAC_READ_STATUS |
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[c99627b] | 264 | // |
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| 265 | ////////////////////////////////////////////////////////////////////////////// |
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| 266 | |
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| 267 | unsigned char dac_read_status(int dac_num) |
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| 268 | { |
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[6f4d6bd] | 269 | mio_error_code = MIO_SUCCESS; |
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[c99627b] | 270 | |
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[6f4d6bd] | 271 | if (check_handle()) /* Check for chip available */ |
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| 272 | return -1; |
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[c99627b] | 273 | |
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[6f4d6bd] | 274 | if (dac_num) |
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| 275 | return inb(base_port + 0x0f); |
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[c99627b] | 276 | |
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[6f4d6bd] | 277 | return inb(base_port + 0x0b); |
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[c99627b] | 278 | } |
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| 279 | |
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| 280 | /////////////////////////////////////////////////////////////////////////////// |
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| 281 | // |
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[6f4d6bd] | 282 | // ADC_READ_STATUS |
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[c99627b] | 283 | // |
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| 284 | ////////////////////////////////////////////////////////////////////////////// |
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| 285 | |
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| 286 | unsigned char adc_read_status(int adc_num) |
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| 287 | { |
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[6f4d6bd] | 288 | mio_error_code = MIO_SUCCESS; |
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[c99627b] | 289 | |
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[6f4d6bd] | 290 | if (check_handle()) /* Check for chip available */ |
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| 291 | return -1; |
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[c99627b] | 292 | |
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[6f4d6bd] | 293 | if (adc_num) |
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| 294 | return inb(base_port + 7); |
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| 295 | return inb(base_port + 3); |
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[c99627b] | 296 | } |
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| 297 | |
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| 298 | /////////////////////////////////////////////////////////////////////////////// |
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| 299 | // |
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[6f4d6bd] | 300 | // ADC_READ_CONVERSION_DATA |
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[c99627b] | 301 | // |
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| 302 | ////////////////////////////////////////////////////////////////////////////// |
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| 303 | |
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| 304 | unsigned short adc_read_conversion_data(int channel) |
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| 305 | { |
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| 306 | int adc_num; |
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| 307 | |
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[6f4d6bd] | 308 | mio_error_code = MIO_SUCCESS; |
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[c99627b] | 309 | |
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[6f4d6bd] | 310 | if (check_handle()) /* Check for chip available */ |
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| 311 | return -1; |
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[c99627b] | 312 | |
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[6f4d6bd] | 313 | if (channel > 7) |
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| 314 | adc_num = 1; |
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| 315 | else |
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| 316 | adc_num = 0; |
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[c99627b] | 317 | |
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[6f4d6bd] | 318 | if (adc_num) |
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| 319 | return inw(base_port + 4); |
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| 320 | |
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| 321 | return inw(base_port); |
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[c99627b] | 322 | } |
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| 323 | |
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| 324 | |
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| 325 | int dio_get_int(void) |
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| 326 | { |
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[6f4d6bd] | 327 | if (check_handle()) /* Check for chip available */ |
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| 328 | return -1; |
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[c99627b] | 329 | |
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[6f4d6bd] | 330 | return get_buffered_int() & 0xff; |
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[c99627b] | 331 | |
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| 332 | } |
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| 333 | |
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| 334 | int wait_adc_int(int adc_num) |
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| 335 | { |
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[6f4d6bd] | 336 | if (check_handle()) /* Check for chip available */ |
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| 337 | return -1; |
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[c99627b] | 338 | |
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[2fc4157] | 339 | if (adc_num) { |
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| 340 | interruptible_sleep_on(&wq_a2d_1); |
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| 341 | } else { |
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| 342 | interruptible_sleep_on(&wq_a2d_2); |
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| 343 | } |
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[c99627b] | 344 | |
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[2fc4157] | 345 | return 0; |
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[c99627b] | 346 | } |
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| 347 | |
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| 348 | |
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| 349 | int wait_dac_int(int dac_num) |
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| 350 | { |
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[6f4d6bd] | 351 | if (check_handle()) /* Check for chip available */ |
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| 352 | return -1; |
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[c99627b] | 353 | |
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[2fc4157] | 354 | if (dac_num) { |
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| 355 | interruptible_sleep_on(&wq_dac_1); |
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| 356 | } else { |
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| 357 | interruptible_sleep_on(&wq_dac_2); |
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| 358 | } |
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[c99627b] | 359 | |
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[2fc4157] | 360 | return 0; |
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[c99627b] | 361 | } |
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| 362 | |
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| 363 | |
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| 364 | int wait_dio_int(void) |
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| 365 | { |
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[2fc4157] | 366 | int i; |
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[6f4d6bd] | 367 | |
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| 368 | if (check_handle()) /* Check for chip available */ |
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| 369 | return -1; |
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[c99627b] | 370 | |
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[2fc4157] | 371 | if((i = get_buffered_int())) |
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| 372 | return i; |
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| 373 | |
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| 374 | interruptible_sleep_on(&wq_dio); |
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[c99627b] | 375 | |
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[2fc4157] | 376 | i = get_buffered_int(); |
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[c99627b] | 377 | |
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[2fc4157] | 378 | return i; |
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[6f4d6bd] | 379 | } |
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[c99627b] | 380 | |
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| 381 | |
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[2fc4157] | 382 | static int handle = 0; /* XXX move to lower */ |
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| 383 | |
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[6f4d6bd] | 384 | int check_handle(void) |
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| 385 | { |
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| 386 | if (handle > 0) /* If it's already a valid handle */ |
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| 387 | return 0; |
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| 388 | |
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| 389 | if (handle == -1) /* If it's already been tried */ |
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| 390 | { |
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| 391 | mio_error_code = MIO_OPEN_ERROR; |
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| 392 | sprintf(mio_error_string,"MIO - Unable to open device PCMMIO"); |
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| 393 | return -1; |
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| 394 | } |
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| 395 | |
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| 396 | /* |
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| 397 | * 0 ==> not initialized |
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| 398 | * 1+ ==> valid file handle, thus initialized |
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| 399 | * -1 ==> already attempted to open |
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| 400 | */ |
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| 401 | handle = 1; |
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| 402 | return 0; |
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| 403 | |
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| 404 | /* if an error happens, go here */ |
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| 405 | mio_error_code = MIO_OPEN_ERROR; |
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| 406 | sprintf(mio_error_string,"MIO - Unable to open device PCMMIO"); |
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| 407 | handle = -1; |
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| 408 | return -1; |
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[c99627b] | 409 | } |
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| 410 | |
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[2fc4157] | 411 | /* |
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| 412 | * RTEMS barrier create helper |
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| 413 | */ |
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| 414 | void pcmmio_barrier_create( |
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| 415 | rtems_name name, |
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| 416 | rtems_id *id |
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| 417 | ) |
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| 418 | { |
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| 419 | rtems_status_code rc; |
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| 420 | |
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| 421 | rc = rtems_barrier_create( name, RTEMS_BARRIER_MANUAL_RELEASE, 0, id ); |
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| 422 | if ( rc == RTEMS_SUCCESSFUL ) |
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| 423 | return; |
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| 424 | |
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| 425 | printk( "Unable to create PCMMIO Barrier\n" ); |
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| 426 | exit(1); |
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| 427 | } |
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| 428 | |
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| 429 | void interruptible_sleep_on( |
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| 430 | rtems_id *id |
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| 431 | ) |
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| 432 | { |
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| 433 | rtems_status_code rc; |
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| 434 | |
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| 435 | rc = rtems_barrier_wait(*id, 0); |
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| 436 | } |
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| 437 | |
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| 438 | void wake_up_interruptible( |
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| 439 | rtems_id *id |
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| 440 | ) |
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| 441 | { |
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| 442 | rtems_status_code rc; |
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| 443 | uint32_t unblocked; |
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| 444 | |
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| 445 | rc = rtems_barrier_release(*id, &unblocked); |
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| 446 | } |
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| 447 | |
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[da59d43] | 448 | /* |
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| 449 | * RTEMS specific interrupt handler |
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| 450 | */ |
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| 451 | #include <bsp/irq.h> |
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| 452 | |
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| 453 | void common_handler(void); |
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| 454 | |
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| 455 | void pcmmio_interrupt_handler( |
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| 456 | rtems_irq_hdl_param param |
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| 457 | ) |
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| 458 | { |
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| 459 | } |
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| 460 | |
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| 461 | rtems_irq_connect_data pcmmio_irq = { |
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| 462 | 0, // name |
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| 463 | pcmmio_interrupt_handler, // handler |
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| 464 | NULL, // parameter |
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| 465 | NULL, // enable IRQ |
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| 466 | NULL, // disable IRQ |
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| 467 | NULL, // is IRQ enabled |
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| 468 | }; |
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| 469 | |
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[2fc4157] | 470 | /* |
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| 471 | * RTEMS specific initialization routine |
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| 472 | */ |
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| 473 | void pcmmio_initialize( |
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| 474 | unsigned short _base_port, |
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| 475 | unsigned short _irq |
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| 476 | ) |
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| 477 | { |
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| 478 | /* hardware configuration information */ |
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| 479 | base_port = _base_port; |
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| 480 | irq = _irq; |
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| 481 | |
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| 482 | /* Create RTEMS Objects */ |
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| 483 | pcmmio_barrier_create( rtems_build_name( 'a', '2', 'd', '1' ), &wq_a2d_1 ); |
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| 484 | pcmmio_barrier_create( rtems_build_name( 'd', 'a', 'c', '1' ), &wq_dac_1 ); |
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| 485 | pcmmio_barrier_create( rtems_build_name( 'd', 'a', 'c', '2' ), &wq_dac_2 ); |
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| 486 | pcmmio_barrier_create( rtems_build_name( 'd', 'i', 'o', ' ' ), &wq_dio ); |
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[da59d43] | 487 | |
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| 488 | /* install IRQ handler */ |
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| 489 | if ( irq ) { |
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| 490 | pcmmio_irq.name = irq; |
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| 491 | BSP_install_rtems_irq_handler( &pcmmio_irq ); |
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| 492 | } |
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[2fc4157] | 493 | } |
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| 494 | |
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[c99627b] | 495 | |
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[6f4d6bd] | 496 | /* |
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| 497 | * From this point down, we should be able to share easily with the Linux |
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| 498 | * driver but I haven't gone to the trouble to do surgery on it. I have |
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| 499 | * no way to test it. |
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| 500 | */ |
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[c99627b] | 501 | |
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[6f4d6bd] | 502 | /* We will buffer up the transition interrupts and will pass them on |
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| 503 | to waiting applications |
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| 504 | */ |
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| 505 | |
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| 506 | #define MAX_INTS 1024 |
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| 507 | |
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| 508 | static unsigned char int_buffer[MAX_INTS]; |
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| 509 | static int inptr = 0; |
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| 510 | static int outptr = 0; |
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| 511 | |
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[2fc4157] | 512 | static unsigned char adc2_port_image; |
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| 513 | |
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| 514 | /* This is the common interrupt handler. It is called by the |
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| 515 | * actual hardware ISR. |
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| 516 | */ |
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| 517 | |
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| 518 | void common_handler(void) |
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| 519 | { |
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| 520 | unsigned char status; |
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| 521 | unsigned char int_num; |
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| 522 | |
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| 523 | /* Read the interrupt ID register from ADC2 */ |
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| 524 | |
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| 525 | adc2_port_image = adc2_port_image | 0x20; |
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| 526 | outb(adc2_port_image,base_port + 0x0f); |
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| 527 | |
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| 528 | status = inb(base_port + 0x0f); |
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| 529 | if (status & 1) { |
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| 530 | /* Clear ADC1 interrupt */ |
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| 531 | inb(base_port+1); /* Clear interrupt */ |
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| 532 | |
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| 533 | /* Wake up any holding processes */ |
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| 534 | wake_up_interruptible(&wq_a2d_1); |
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| 535 | } |
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| 536 | |
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| 537 | if (status & 2) { |
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| 538 | /* Clear ADC1 interrupt */ |
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| 539 | inb(base_port+5); /* Clear interrupt */ |
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| 540 | |
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| 541 | /* Wake up anybody waiting for ADC1 */ |
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| 542 | wake_up_interruptible(&wq_a2d_2); |
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| 543 | } |
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| 544 | |
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| 545 | if (status & 4) { |
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| 546 | /* Clear DAC1 interrupt */ |
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| 547 | inb(base_port+9); /* Clear interrupt */ |
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| 548 | |
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| 549 | /* Wake up if you're waiting on DAC1 */ |
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| 550 | wake_up_interruptible(&wq_dac_1); |
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| 551 | } |
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| 552 | |
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| 553 | if (status & 8) { |
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| 554 | |
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| 555 | /* DIO interrupt. Find out which bit */ |
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| 556 | int_num = get_int(); |
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| 557 | if (int_num) { |
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| 558 | #ifdef DEBUG |
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| 559 | printk("<1>Buffering DIO interrupt on bit %d\n",int_num); |
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| 560 | #endif |
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| 561 | |
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| 562 | /* Buffer the interrupt */ |
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| 563 | |
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| 564 | int_buffer[inptr++] = int_num; |
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| 565 | if (inptr == MAX_INTS) |
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| 566 | inptr = 0; |
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| 567 | |
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| 568 | /* Clear the interrupt */ |
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| 569 | clr_int(int_num); |
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| 570 | } |
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| 571 | |
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| 572 | /* Wake up anybody waiting for a DIO interrupt */ |
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| 573 | wake_up_interruptible(&wq_dio); |
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| 574 | } |
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| 575 | |
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| 576 | if (status & 0x10) { |
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| 577 | /* Clear DAC2 Interrupt */ |
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| 578 | inb(base_port+0x0d); /* Clear interrupt */ |
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| 579 | |
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| 580 | /* Wake up DAC2 holding processes */ |
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| 581 | wake_up_interruptible(&wq_dac_2); |
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| 582 | } |
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| 583 | |
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| 584 | /* Reset the access to the interrupt ID register */ |
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| 585 | adc2_port_image = adc2_port_image & 0xdf; |
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| 586 | outb(adc2_port_image,base_port+0x0f); |
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| 587 | } |
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| 588 | |
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| 589 | |
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[6f4d6bd] | 590 | void clr_int(int bit_number) |
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[c99627b] | 591 | { |
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[6f4d6bd] | 592 | unsigned short port; |
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| 593 | unsigned short temp; |
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| 594 | unsigned short mask; |
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| 595 | unsigned short dio_port; |
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| 596 | |
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| 597 | dio_port = base_port + 0x10; |
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| 598 | |
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| 599 | /* Also adjust bit number */ |
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| 600 | --bit_number; |
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| 601 | |
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| 602 | /* Calculate the I/O address based upon bit number */ |
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| 603 | port = (bit_number / 8) + dio_port + 8; |
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[c99627b] | 604 | |
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[6f4d6bd] | 605 | /* Calculate a bit mask based upon the specified bit number */ |
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| 606 | mask = (1 << (bit_number % 8)); |
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[c99627b] | 607 | |
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[6f4d6bd] | 608 | /* Turn on page 2 access */ |
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| 609 | outb(0x80,dio_port+7); |
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[c99627b] | 610 | |
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[6f4d6bd] | 611 | /* Get the current state of the interrupt enable register */ |
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| 612 | temp = inb(port); |
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[c99627b] | 613 | |
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[6f4d6bd] | 614 | /* Temporarily clear only our enable. This clears the interrupt */ |
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| 615 | temp = temp & ~mask; /* Clear the enable for this bit */ |
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[c99627b] | 616 | |
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[6f4d6bd] | 617 | /* Now update the interrupt enable register */ |
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| 618 | outb(temp,port); |
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[c99627b] | 619 | |
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[6f4d6bd] | 620 | /* Re-enable our interrupt bit */ |
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| 621 | temp = temp | mask; |
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| 622 | outb(temp,port); |
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[c99627b] | 623 | |
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[6f4d6bd] | 624 | /* Set access back to page 0 */ |
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| 625 | outb(0x00,dio_port+7); |
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[c99627b] | 626 | } |
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| 627 | |
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[6f4d6bd] | 628 | int get_int(void) |
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| 629 | { |
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| 630 | int temp; |
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| 631 | int x; |
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| 632 | unsigned short dio_port; |
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| 633 | |
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| 634 | dio_port = base_port + 0x10; |
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| 635 | |
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| 636 | /* Read the master interrupt pending register, |
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| 637 | mask off undefined bits */ |
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| 638 | temp = inb(dio_port+6) & 0x07; |
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| 639 | |
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| 640 | /* If there are no pending interrupts, return 0 */ |
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| 641 | if ((temp & 7) == 0) |
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| 642 | return 0; |
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| 643 | |
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| 644 | /* There is something pending, now we need to identify it */ |
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| 645 | |
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| 646 | /* Set access to page 3 for interrupt id register */ |
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| 647 | outb(0xc0, dio_port + 7); |
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| 648 | |
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| 649 | /* Read the interrupt ID register for port 0 */ |
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| 650 | temp = inb(dio_port+8); |
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| 651 | |
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| 652 | /* See if any bit set, if so return the bit number */ |
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| 653 | if (temp != 0) { |
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| 654 | for (x=0; x<=7; x++) { |
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| 655 | if (temp & (1 << x)) { |
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| 656 | outb(0,dio_port+7); |
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| 657 | return(x+1); |
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| 658 | } |
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| 659 | } |
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| 660 | } |
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| 661 | |
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| 662 | /* None in port 0, read port 1 interrupt ID register */ |
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| 663 | temp = inb(dio_port+9); |
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| 664 | |
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| 665 | /* See if any bit set, if so return the bit number */ |
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| 666 | if (temp != 0) { |
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| 667 | for (x=0; x<=7; x++) { |
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| 668 | if (temp & (1 << x)) { |
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| 669 | outb(0,dio_port+7); |
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| 670 | return(x+9); |
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| 671 | } |
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| 672 | } |
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| 673 | } |
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| 674 | |
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| 675 | /* Lastly, read the statur of port 2 interrupt ID register */ |
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| 676 | temp = inb(dio_port+0x0a); |
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| 677 | |
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| 678 | /* If any pending, return the appropriate bit number */ |
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| 679 | if (temp != 0) { |
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| 680 | for (x=0; x<=7; x++) { |
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| 681 | if (temp & (1 << x)) { |
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| 682 | outb(0,dio_port+7); |
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| 683 | return(x+17); |
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| 684 | } |
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| 685 | } |
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| 686 | } |
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| 687 | |
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| 688 | /* We should never get here unless the hardware is seriously |
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| 689 | misbehaving, but just to be sure, we'll turn the page access |
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| 690 | back to 0 and return a 0 for no interrupt found |
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| 691 | */ |
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| 692 | outb(0,dio_port+7); |
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| 693 | return 0; |
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| 694 | } |
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| 695 | |
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| 696 | |
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| 697 | int get_buffered_int(void) |
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| 698 | { |
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| 699 | int temp; |
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| 700 | |
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| 701 | if (irq == 0) { |
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| 702 | temp = get_int(); |
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| 703 | if (temp) |
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| 704 | clr_int(temp); |
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| 705 | return temp; |
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| 706 | } |
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| 707 | |
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| 708 | if (outptr != inptr) { |
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| 709 | temp = int_buffer[outptr++]; |
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| 710 | if (outptr == MAX_INTS) |
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| 711 | outptr = 0; |
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| 712 | return temp; |
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| 713 | } |
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| 714 | |
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| 715 | return 0; |
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| 716 | } |
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