source: libbsdport/bsd_eth_drivers/if_re/if_rlreg.h @ 89376b7

B_20100615baselibbsdport-4-10-branch initial
Last change on this file since 89376b7 was 89376b7, checked in by Joel Sherrill <joel.sherrill@…>, on Feb 19, 2009 at 7:55:40 PM

Initial import.

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1/*-
2 * Copyright (c) 1997, 1998-2003
3 *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 *    must display the following acknowledgement:
15 *      This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 *    may be used to endorse or promote products derived from this software
18 *    without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.51.2.14.2.1 2008/10/02 02:57:24 kensmith Exp $
33 */
34
35/*
36 * RealTek 8129/8139 register offsets
37 */
38#define RL_IDR0         0x0000          /* ID register 0 (station addr) */
39#define RL_IDR1         0x0001          /* Must use 32-bit accesses (?) */
40#define RL_IDR2         0x0002
41#define RL_IDR3         0x0003
42#define RL_IDR4         0x0004
43#define RL_IDR5         0x0005
44                                        /* 0006-0007 reserved */
45#define RL_MAR0         0x0008          /* Multicast hash table */
46#define RL_MAR1         0x0009
47#define RL_MAR2         0x000A
48#define RL_MAR3         0x000B
49#define RL_MAR4         0x000C
50#define RL_MAR5         0x000D
51#define RL_MAR6         0x000E
52#define RL_MAR7         0x000F
53
54#define RL_TXSTAT0      0x0010          /* status of TX descriptor 0 */
55#define RL_TXSTAT1      0x0014          /* status of TX descriptor 1 */
56#define RL_TXSTAT2      0x0018          /* status of TX descriptor 2 */
57#define RL_TXSTAT3      0x001C          /* status of TX descriptor 3 */
58
59#define RL_TXADDR0      0x0020          /* address of TX descriptor 0 */
60#define RL_TXADDR1      0x0024          /* address of TX descriptor 1 */
61#define RL_TXADDR2      0x0028          /* address of TX descriptor 2 */
62#define RL_TXADDR3      0x002C          /* address of TX descriptor 3 */
63
64#define RL_RXADDR               0x0030  /* RX ring start address */
65#define RL_RX_EARLY_BYTES       0x0034  /* RX early byte count */
66#define RL_RX_EARLY_STAT        0x0036  /* RX early status */
67#define RL_COMMAND      0x0037          /* command register */
68#define RL_CURRXADDR    0x0038          /* current address of packet read */
69#define RL_CURRXBUF     0x003A          /* current RX buffer address */
70#define RL_IMR          0x003C          /* interrupt mask register */
71#define RL_ISR          0x003E          /* interrupt status register */
72#define RL_TXCFG        0x0040          /* transmit config */
73#define RL_RXCFG        0x0044          /* receive config */
74#define RL_TIMERCNT     0x0048          /* timer count register */
75#define RL_MISSEDPKT    0x004C          /* missed packet counter */
76#define RL_EECMD        0x0050          /* EEPROM command register */
77#define RL_CFG0         0x0051          /* config register #0 */
78#define RL_CFG1         0x0052          /* config register #1 */
79                                        /* 0053-0057 reserved */   
80#define RL_MEDIASTAT    0x0058          /* media status register (8139) */
81                                        /* 0059-005A reserved */
82#define RL_MII          0x005A          /* 8129 chip only */
83#define RL_HALTCLK      0x005B
84#define RL_MULTIINTR    0x005C          /* multiple interrupt */
85#define RL_PCIREV       0x005E          /* PCI revision value */
86                                        /* 005F reserved */
87#define RL_TXSTAT_ALL   0x0060          /* TX status of all descriptors */
88
89/* Direct PHY access registers only available on 8139 */
90#define RL_BMCR         0x0062          /* PHY basic mode control */
91#define RL_BMSR         0x0064          /* PHY basic mode status */
92#define RL_ANAR         0x0066          /* PHY autoneg advert */
93#define RL_LPAR         0x0068          /* PHY link partner ability */
94#define RL_ANER         0x006A          /* PHY autoneg expansion */
95
96#define RL_DISCCNT      0x006C          /* disconnect counter */
97#define RL_FALSECAR     0x006E          /* false carrier counter */
98#define RL_NWAYTST      0x0070          /* NWAY test register */
99#define RL_RX_ER        0x0072          /* RX_ER counter */
100#define RL_CSCFG        0x0074          /* CS configuration register */
101
102/*
103 * When operating in special C+ mode, some of the registers in an
104 * 8139C+ chip have different definitions. These are also used for
105 * the 8169 gigE chip.
106 */
107#define RL_DUMPSTATS_LO         0x0010  /* counter dump command register */
108#define RL_DUMPSTATS_HI         0x0014  /* counter dump command register */
109#define RL_TXLIST_ADDR_LO       0x0020  /* 64 bits, 256 byte alignment */
110#define RL_TXLIST_ADDR_HI       0x0024  /* 64 bits, 256 byte alignment */
111#define RL_TXLIST_ADDR_HPRIO_LO 0x0028  /* 64 bits, 256 byte alignment */
112#define RL_TXLIST_ADDR_HPRIO_HI 0x002C  /* 64 bits, 256 byte alignment */
113#define RL_CFG2                 0x0053
114#define RL_TIMERINT             0x0054  /* interrupt on timer expire */
115#define RL_TXSTART              0x00D9  /* 8 bits */
116#define RL_CPLUS_CMD            0x00E0  /* 16 bits */
117#define RL_RXLIST_ADDR_LO       0x00E4  /* 64 bits, 256 byte alignment */
118#define RL_RXLIST_ADDR_HI       0x00E8  /* 64 bits, 256 byte alignment */
119#define RL_EARLY_TX_THRESH      0x00EC  /* 8 bits */
120
121/*
122 * Registers specific to the 8169 gigE chip
123 */
124#define RL_TIMERINT_8169        0x0058  /* different offset than 8139 */
125#define RL_PHYAR                0x0060
126#define RL_TBICSR               0x0064
127#define RL_TBI_ANAR             0x0068
128#define RL_TBI_LPAR             0x006A
129#define RL_GMEDIASTAT           0x006C  /* 8 bits */
130#define RL_MAXRXPKTLEN          0x00DA  /* 16 bits, chip multiplies by 8 */
131#define RL_GTXSTART             0x0038  /* 16 bits */
132
133/*
134 * TX config register bits
135 */
136#define RL_TXCFG_CLRABRT        0x00000001      /* retransmit aborted pkt */
137#define RL_TXCFG_MAXDMA         0x00000700      /* max DMA burst size */
138#define RL_TXCFG_CRCAPPEND      0x00010000      /* CRC append (0 = yes) */
139#define RL_TXCFG_LOOPBKTST      0x00060000      /* loopback test */
140#define RL_TXCFG_IFG2           0x00080000      /* 8169 only */
141#define RL_TXCFG_IFG            0x03000000      /* interframe gap */
142#define RL_TXCFG_HWREV          0x7CC00000
143
144#define RL_LOOPTEST_OFF         0x00000000
145#define RL_LOOPTEST_ON          0x00020000
146#define RL_LOOPTEST_ON_CPLUS    0x00060000
147
148/* Known revision codes. */
149
150#define RL_HWREV_8169           0x00000000
151#define RL_HWREV_8110S          0x00800000
152#define RL_HWREV_8169S          0x04000000
153#define RL_HWREV_8169_8110SB    0x10000000
154#define RL_HWREV_8169_8110SC    0x18000000
155#define RL_HWREV_8168_SPIN1     0x30000000
156#define RL_HWREV_8100E          0x30800000
157#define RL_HWREV_8101E          0x34000000
158#define RL_HWREV_8168_SPIN2     0x38000000
159#define RL_HWREV_8168_SPIN3     0x38400000
160#define RL_HWREV_8139           0x60000000
161#define RL_HWREV_8139A          0x70000000
162#define RL_HWREV_8139AG         0x70800000
163#define RL_HWREV_8139B          0x78000000
164#define RL_HWREV_8130           0x7C000000
165#define RL_HWREV_8139C          0x74000000
166#define RL_HWREV_8139D          0x74400000
167#define RL_HWREV_8139CPLUS      0x74800000
168#define RL_HWREV_8101           0x74c00000
169#define RL_HWREV_8100           0x78800000
170
171#define RL_TXDMA_16BYTES        0x00000000
172#define RL_TXDMA_32BYTES        0x00000100
173#define RL_TXDMA_64BYTES        0x00000200
174#define RL_TXDMA_128BYTES       0x00000300
175#define RL_TXDMA_256BYTES       0x00000400
176#define RL_TXDMA_512BYTES       0x00000500
177#define RL_TXDMA_1024BYTES      0x00000600
178#define RL_TXDMA_2048BYTES      0x00000700
179
180/*
181 * Transmit descriptor status register bits.
182 */
183#define RL_TXSTAT_LENMASK       0x00001FFF
184#define RL_TXSTAT_OWN           0x00002000
185#define RL_TXSTAT_TX_UNDERRUN   0x00004000
186#define RL_TXSTAT_TX_OK         0x00008000
187#define RL_TXSTAT_EARLY_THRESH  0x003F0000
188#define RL_TXSTAT_COLLCNT       0x0F000000
189#define RL_TXSTAT_CARR_HBEAT    0x10000000
190#define RL_TXSTAT_OUTOFWIN      0x20000000
191#define RL_TXSTAT_TXABRT        0x40000000
192#define RL_TXSTAT_CARRLOSS      0x80000000
193
194/*
195 * Interrupt status register bits.
196 */
197#define RL_ISR_RX_OK            0x0001
198#define RL_ISR_RX_ERR           0x0002
199#define RL_ISR_TX_OK            0x0004
200#define RL_ISR_TX_ERR           0x0008
201#define RL_ISR_RX_OVERRUN       0x0010
202#define RL_ISR_PKT_UNDERRUN     0x0020
203#define RL_ISR_LINKCHG          0x0020  /* 8169 only */
204#define RL_ISR_FIFO_OFLOW       0x0040  /* 8139 only */
205#define RL_ISR_TX_DESC_UNAVAIL  0x0080  /* C+ only */
206#define RL_ISR_SWI              0x0100  /* C+ only */
207#define RL_ISR_CABLE_LEN_CHGD   0x2000
208#define RL_ISR_PCS_TIMEOUT      0x4000  /* 8129 only */
209#define RL_ISR_TIMEOUT_EXPIRED  0x4000
210#define RL_ISR_SYSTEM_ERR       0x8000
211
212#define RL_INTRS        \
213        (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|         \
214        RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW|        \
215        RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR)
216
217#ifdef RE_TX_MODERATION
218#define RL_INTRS_CPLUS  \
219        (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|                      \
220        RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW|        \
221        RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
222#else
223#define RL_INTRS_CPLUS  \
224        (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK|         \
225        RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW|        \
226        RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
227#endif
228
229/*
230 * Media status register. (8139 only)
231 */
232#define RL_MEDIASTAT_RXPAUSE    0x01
233#define RL_MEDIASTAT_TXPAUSE    0x02
234#define RL_MEDIASTAT_LINK       0x04
235#define RL_MEDIASTAT_SPEED10    0x08
236#define RL_MEDIASTAT_RXFLOWCTL  0x40    /* duplex mode */
237#define RL_MEDIASTAT_TXFLOWCTL  0x80    /* duplex mode */
238
239/*
240 * Receive config register.
241 */
242#define RL_RXCFG_RX_ALLPHYS     0x00000001      /* accept all nodes */
243#define RL_RXCFG_RX_INDIV       0x00000002      /* match filter */
244#define RL_RXCFG_RX_MULTI       0x00000004      /* accept all multicast */
245#define RL_RXCFG_RX_BROAD       0x00000008      /* accept all broadcast */
246#define RL_RXCFG_RX_RUNT        0x00000010
247#define RL_RXCFG_RX_ERRPKT      0x00000020
248#define RL_RXCFG_WRAP           0x00000080
249#define RL_RXCFG_MAXDMA         0x00000700
250#define RL_RXCFG_BUFSZ          0x00001800
251#define RL_RXCFG_FIFOTHRESH     0x0000E000
252#define RL_RXCFG_EARLYTHRESH    0x07000000
253
254#define RL_RXDMA_16BYTES        0x00000000
255#define RL_RXDMA_32BYTES        0x00000100
256#define RL_RXDMA_64BYTES        0x00000200
257#define RL_RXDMA_128BYTES       0x00000300
258#define RL_RXDMA_256BYTES       0x00000400
259#define RL_RXDMA_512BYTES       0x00000500
260#define RL_RXDMA_1024BYTES      0x00000600
261#define RL_RXDMA_UNLIMITED      0x00000700
262
263#define RL_RXBUF_8              0x00000000
264#define RL_RXBUF_16             0x00000800
265#define RL_RXBUF_32             0x00001000
266#define RL_RXBUF_64             0x00001800
267
268#define RL_RXFIFO_16BYTES       0x00000000
269#define RL_RXFIFO_32BYTES       0x00002000
270#define RL_RXFIFO_64BYTES       0x00004000
271#define RL_RXFIFO_128BYTES      0x00006000
272#define RL_RXFIFO_256BYTES      0x00008000
273#define RL_RXFIFO_512BYTES      0x0000A000
274#define RL_RXFIFO_1024BYTES     0x0000C000
275#define RL_RXFIFO_NOTHRESH      0x0000E000
276
277/*
278 * Bits in RX status header (included with RX'ed packet
279 * in ring buffer).
280 */
281#define RL_RXSTAT_RXOK          0x00000001
282#define RL_RXSTAT_ALIGNERR      0x00000002
283#define RL_RXSTAT_CRCERR        0x00000004
284#define RL_RXSTAT_GIANT         0x00000008
285#define RL_RXSTAT_RUNT          0x00000010
286#define RL_RXSTAT_BADSYM        0x00000020
287#define RL_RXSTAT_BROAD         0x00002000
288#define RL_RXSTAT_INDIV         0x00004000
289#define RL_RXSTAT_MULTI         0x00008000
290#define RL_RXSTAT_LENMASK       0xFFFF0000
291
292#define RL_RXSTAT_UNFINISHED    0xFFF0          /* DMA still in progress */
293/*
294 * Command register.
295 */
296#define RL_CMD_EMPTY_RXBUF      0x0001
297#define RL_CMD_TX_ENB           0x0004
298#define RL_CMD_RX_ENB           0x0008
299#define RL_CMD_RESET            0x0010
300
301/*
302 * EEPROM control register
303 */
304#define RL_EE_DATAOUT           0x01    /* Data out */
305#define RL_EE_DATAIN            0x02    /* Data in */
306#define RL_EE_CLK               0x04    /* clock */
307#define RL_EE_SEL               0x08    /* chip select */
308#define RL_EE_MODE              (0x40|0x80)
309
310#define RL_EEMODE_OFF           0x00
311#define RL_EEMODE_AUTOLOAD      0x40
312#define RL_EEMODE_PROGRAM       0x80
313#define RL_EEMODE_WRITECFG      (0x80|0x40)
314
315/* 9346 EEPROM commands */
316#define RL_9346_ADDR_LEN        6       /* 93C46 1K: 128x16 */
317#define RL_9356_ADDR_LEN        8       /* 93C56 2K: 256x16 */
318
319#define RL_9346_WRITE          0x5
320#define RL_9346_READ           0x6
321#define RL_9346_ERASE          0x7
322#define RL_9346_EWEN           0x4
323#define RL_9346_EWEN_ADDR      0x30
324#define RL_9456_EWDS           0x4
325#define RL_9346_EWDS_ADDR      0x00
326
327#define RL_EECMD_WRITE          0x140
328#define RL_EECMD_READ_6BIT      0x180
329#define RL_EECMD_READ_8BIT      0x600
330#define RL_EECMD_ERASE          0x1c0
331
332#define RL_EE_ID                0x00
333#define RL_EE_PCI_VID           0x01
334#define RL_EE_PCI_DID           0x02
335/* Location of station address inside EEPROM */
336#define RL_EE_EADDR             0x07
337
338/*
339 * MII register (8129 only)
340 */
341#define RL_MII_CLK              0x01
342#define RL_MII_DATAIN           0x02
343#define RL_MII_DATAOUT          0x04
344#define RL_MII_DIR              0x80    /* 0 == input, 1 == output */
345
346/*
347 * Config 0 register
348 */
349#define RL_CFG0_ROM0            0x01
350#define RL_CFG0_ROM1            0x02
351#define RL_CFG0_ROM2            0x04
352#define RL_CFG0_PL0             0x08
353#define RL_CFG0_PL1             0x10
354#define RL_CFG0_10MBPS          0x20    /* 10 Mbps internal mode */
355#define RL_CFG0_PCS             0x40
356#define RL_CFG0_SCR             0x80
357
358/*
359 * Config 1 register
360 */
361#define RL_CFG1_PWRDWN          0x01
362#define RL_CFG1_SLEEP           0x02
363#define RL_CFG1_IOMAP           0x04
364#define RL_CFG1_MEMMAP          0x08
365#define RL_CFG1_RSVD            0x10
366#define RL_CFG1_DRVLOAD         0x20
367#define RL_CFG1_LED0            0x40
368#define RL_CFG1_FULLDUPLEX      0x40    /* 8129 only */
369#define RL_CFG1_LED1            0x80
370
371/*
372 * 8139C+ register definitions
373 */
374
375/* RL_DUMPSTATS_LO register */
376
377#define RL_DUMPSTATS_START      0x00000008
378
379/* Transmit start register */
380
381#define RL_TXSTART_SWI          0x01    /* generate TX interrupt */
382#define RL_TXSTART_START        0x40    /* start normal queue transmit */
383#define RL_TXSTART_HPRIO_START  0x80    /* start hi prio queue transmit */
384
385/*
386 * Config 2 register, 8139C+/8169/8169S/8110S only
387 */
388#define RL_CFG2_BUSFREQ         0x07
389#define RL_CFG2_BUSWIDTH        0x08
390#define RL_CFG2_AUXPWRSTS       0x10
391
392#define RL_BUSFREQ_33MHZ        0x00
393#define RL_BUSFREQ_66MHZ        0x01
394                                       
395#define RL_BUSWIDTH_32BITS      0x00
396#define RL_BUSWIDTH_64BITS      0x08
397
398/* C+ mode command register */
399
400#define RL_CPLUSCMD_TXENB       0x0001  /* enable C+ transmit mode */
401#define RL_CPLUSCMD_RXENB       0x0002  /* enable C+ receive mode */
402#define RL_CPLUSCMD_PCI_MRW     0x0008  /* enable PCI multi-read/write */
403#define RL_CPLUSCMD_PCI_DAC     0x0010  /* PCI dual-address cycle only */
404#define RL_CPLUSCMD_RXCSUM_ENB  0x0020  /* enable RX checksum offload */
405#define RL_CPLUSCMD_VLANSTRIP   0x0040  /* enable VLAN tag stripping */
406
407/* C+ early transmit threshold */
408
409#define RL_EARLYTXTHRESH_CNT    0x003F  /* byte count times 8 */ 
410
411/*
412 * Gigabit PHY access register (8169 only)
413 */
414
415#define RL_PHYAR_PHYDATA        0x0000FFFF
416#define RL_PHYAR_PHYREG         0x001F0000
417#define RL_PHYAR_BUSY           0x80000000
418
419/*
420 * Gigabit media status (8169 only)
421 */
422#define RL_GMEDIASTAT_FDX       0x01    /* full duplex */
423#define RL_GMEDIASTAT_LINK      0x02    /* link up */
424#define RL_GMEDIASTAT_10MBPS    0x04    /* 10mps link */
425#define RL_GMEDIASTAT_100MBPS   0x08    /* 100mbps link */
426#define RL_GMEDIASTAT_1000MBPS  0x10    /* gigE link */
427#define RL_GMEDIASTAT_RXFLOW    0x20    /* RX flow control on */
428#define RL_GMEDIASTAT_TXFLOW    0x40    /* TX flow control on */
429#define RL_GMEDIASTAT_TBI       0x80    /* TBI enabled */
430
431/*
432 * The RealTek doesn't use a fragment-based descriptor mechanism.
433 * Instead, there are only four register sets, each or which represents
434 * one 'descriptor.' Basically, each TX descriptor is just a contiguous
435 * packet buffer (32-bit aligned!) and we place the buffer addresses in
436 * the registers so the chip knows where they are.
437 *
438 * We can sort of kludge together the same kind of buffer management
439 * used in previous drivers, but we have to do buffer copies almost all
440 * the time, so it doesn't really buy us much.
441 *
442 * For reception, there's just one large buffer where the chip stores
443 * all received packets.
444 */
445
446#define RL_RX_BUF_SZ            RL_RXBUF_64
447#define RL_RXBUFLEN             (1 << ((RL_RX_BUF_SZ >> 11) + 13))
448#define RL_TX_LIST_CNT          4
449#define RL_MIN_FRAMELEN         60
450#define RL_TXTHRESH(x)          ((x) << 11)
451#define RL_TX_THRESH_INIT       96
452#define RL_RX_FIFOTHRESH        RL_RXFIFO_NOTHRESH
453#define RL_RX_MAXDMA            RL_RXDMA_UNLIMITED
454#define RL_TX_MAXDMA            RL_TXDMA_2048BYTES
455
456#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ)
457#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA)
458
459#define RL_ETHER_ALIGN  2
460
461struct rl_chain_data {
462        uint16_t                cur_rx;
463        uint8_t                 *rl_rx_buf;
464        uint8_t                 *rl_rx_buf_ptr;
465        bus_dmamap_t            rl_rx_dmamap;
466
467        struct mbuf             *rl_tx_chain[RL_TX_LIST_CNT];
468        bus_dmamap_t            rl_tx_dmamap[RL_TX_LIST_CNT];
469        uint8_t                 last_tx;
470        uint8_t                 cur_tx;
471};
472
473#define RL_INC(x)               (x = (x + 1) % RL_TX_LIST_CNT)
474#define RL_CUR_TXADDR(x)        ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0)
475#define RL_CUR_TXSTAT(x)        ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0)
476#define RL_CUR_TXMBUF(x)        (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx])
477#define RL_CUR_DMAMAP(x)        (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx])
478#define RL_LAST_TXADDR(x)       ((x->rl_cdata.last_tx * 4) + RL_TXADDR0)
479#define RL_LAST_TXSTAT(x)       ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0)
480#define RL_LAST_TXMBUF(x)       (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx])
481#define RL_LAST_DMAMAP(x)       (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx])
482
483struct rl_type {
484        uint16_t                rl_vid;
485        uint16_t                rl_did;
486        int                     rl_basetype;
487        char                    *rl_name;
488};
489
490struct rl_hwrev {
491        uint32_t                rl_rev;
492        int                     rl_type;
493        char                    *rl_desc;
494};
495
496struct rl_mii_frame {
497        uint8_t         mii_stdelim;
498        uint8_t         mii_opcode;
499        uint8_t         mii_phyaddr;
500        uint8_t         mii_regaddr;
501        uint8_t         mii_turnaround;
502        uint16_t        mii_data;
503};
504
505/*
506 * MII constants
507 */
508#define RL_MII_STARTDELIM       0x01
509#define RL_MII_READOP           0x02
510#define RL_MII_WRITEOP          0x01
511#define RL_MII_TURNAROUND       0x02
512
513#define RL_8129                 1
514#define RL_8139                 2
515#define RL_8139CPLUS            3
516#define RL_8169                 4
517
518#define RL_ISCPLUS(x)           ((x)->rl_type == RL_8139CPLUS ||        \
519                                 (x)->rl_type == RL_8169)
520
521/*
522 * The 8139C+ and 8160 gigE chips support descriptor-based TX
523 * and RX. In fact, they even support TCP large send. Descriptors
524 * must be allocated in contiguous blocks that are aligned on a
525 * 256-byte boundary. The rings can hold a maximum of 64 descriptors.
526 */
527
528/*
529 * RX/TX descriptor definition. When large send mode is enabled, the
530 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and
531 * the checksum offload bits are disabled. The structure layout is
532 * the same for RX and TX descriptors
533 */
534
535struct rl_desc {
536        uint32_t                rl_cmdstat;
537        uint32_t                rl_vlanctl;
538        uint32_t                rl_bufaddr_lo;
539        uint32_t                rl_bufaddr_hi;
540};
541
542#define RL_TDESC_CMD_FRAGLEN    0x0000FFFF
543#define RL_TDESC_CMD_TCPCSUM    0x00010000      /* TCP checksum enable */
544#define RL_TDESC_CMD_UDPCSUM    0x00020000      /* UDP checksum enable */
545#define RL_TDESC_CMD_IPCSUM     0x00040000      /* IP header checksum enable */
546#define RL_TDESC_CMD_MSSVAL     0x07FF0000      /* Large send MSS value */
547#define RL_TDESC_CMD_LGSEND     0x08000000      /* TCP large send enb */
548#define RL_TDESC_CMD_EOF        0x10000000      /* end of frame marker */
549#define RL_TDESC_CMD_SOF        0x20000000      /* start of frame marker */
550#define RL_TDESC_CMD_EOR        0x40000000      /* end of ring marker */
551#define RL_TDESC_CMD_OWN        0x80000000      /* chip owns descriptor */
552
553#define RL_TDESC_VLANCTL_TAG    0x00020000      /* Insert VLAN tag */
554#define RL_TDESC_VLANCTL_DATA   0x0000FFFF      /* TAG data */
555
556/*
557 * Error bits are valid only on the last descriptor of a frame
558 * (i.e. RL_TDESC_CMD_EOF == 1)
559 */
560
561#define RL_TDESC_STAT_COLCNT    0x000F0000      /* collision count */
562#define RL_TDESC_STAT_EXCESSCOL 0x00100000      /* excessive collisions */
563#define RL_TDESC_STAT_LINKFAIL  0x00200000      /* link faulure */
564#define RL_TDESC_STAT_OWINCOL   0x00400000      /* out-of-window collision */
565#define RL_TDESC_STAT_TXERRSUM  0x00800000      /* transmit error summary */
566#define RL_TDESC_STAT_UNDERRUN  0x02000000      /* TX underrun occured */
567#define RL_TDESC_STAT_OWN       0x80000000
568
569/*
570 * RX descriptor cmd/vlan definitions
571 */
572
573#define RL_RDESC_CMD_EOR        0x40000000
574#define RL_RDESC_CMD_OWN        0x80000000
575#define RL_RDESC_CMD_BUFLEN     0x00001FFF
576
577#define RL_RDESC_STAT_OWN       0x80000000
578#define RL_RDESC_STAT_EOR       0x40000000
579#define RL_RDESC_STAT_SOF       0x20000000
580#define RL_RDESC_STAT_EOF       0x10000000
581#define RL_RDESC_STAT_FRALIGN   0x08000000      /* frame alignment error */
582#define RL_RDESC_STAT_MCAST     0x04000000      /* multicast pkt received */
583#define RL_RDESC_STAT_UCAST     0x02000000      /* unicast pkt received */
584#define RL_RDESC_STAT_BCAST     0x01000000      /* broadcast pkt received */
585#define RL_RDESC_STAT_BUFOFLOW  0x00800000      /* out of buffer space */
586#define RL_RDESC_STAT_FIFOOFLOW 0x00400000      /* FIFO overrun */
587#define RL_RDESC_STAT_GIANT     0x00200000      /* pkt > 4096 bytes */
588#define RL_RDESC_STAT_RXERRSUM  0x00100000      /* RX error summary */
589#define RL_RDESC_STAT_RUNT      0x00080000      /* runt packet received */
590#define RL_RDESC_STAT_CRCERR    0x00040000      /* CRC error */
591#define RL_RDESC_STAT_PROTOID   0x00030000      /* Protocol type */
592#define RL_RDESC_STAT_IPSUMBAD  0x00008000      /* IP header checksum bad */
593#define RL_RDESC_STAT_UDPSUMBAD 0x00004000      /* UDP checksum bad */
594#define RL_RDESC_STAT_TCPSUMBAD 0x00002000      /* TCP checksum bad */
595#define RL_RDESC_STAT_FRAGLEN   0x00001FFF      /* RX'ed frame/frag len */
596#define RL_RDESC_STAT_GFRAGLEN  0x00003FFF      /* RX'ed frame/frag len */
597#define RL_RDESC_STAT_ERRS      (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \
598                                 RL_RDESC_STAT_CRCERR)
599
600#define RL_RDESC_VLANCTL_TAG    0x00010000      /* VLAN tag available
601                                                   (rl_vlandata valid)*/
602#define RL_RDESC_VLANCTL_DATA   0x0000FFFF      /* TAG data */
603
604#define RL_PROTOID_NONIP        0x00000000
605#define RL_PROTOID_TCPIP        0x00010000
606#define RL_PROTOID_UDPIP        0x00020000
607#define RL_PROTOID_IP           0x00030000
608#define RL_TCPPKT(x)            (((x) & RL_RDESC_STAT_PROTOID) == \
609                                 RL_PROTOID_TCPIP)
610#define RL_UDPPKT(x)            (((x) & RL_RDESC_STAT_PROTOID) == \
611                                 RL_PROTOID_UDPIP)
612
613/*
614 * Statistics counter structure (8139C+ and 8169 only)
615 */
616struct rl_stats {
617        uint32_t                rl_tx_pkts_lo;
618        uint32_t                rl_tx_pkts_hi;
619        uint32_t                rl_tx_errs_lo;
620        uint32_t                rl_tx_errs_hi;
621        uint32_t                rl_tx_errs;
622        uint16_t                rl_missed_pkts;
623        uint16_t                rl_rx_framealign_errs;
624        uint32_t                rl_tx_onecoll;
625        uint32_t                rl_tx_multicolls;
626        uint32_t                rl_rx_ucasts_hi;
627        uint32_t                rl_rx_ucasts_lo;
628        uint32_t                rl_rx_bcasts_lo;
629        uint32_t                rl_rx_bcasts_hi;
630        uint32_t                rl_rx_mcasts;
631        uint16_t                rl_tx_aborts;
632        uint16_t                rl_rx_underruns;
633};
634
635/*
636 * Rx/Tx descriptor parameters (8139C+ and 8169 only)
637 *
638 * Tx/Rx count must be equal.  Shared code like re_dma_map_desc assumes this.
639 * Buffers must be a multiple of 8 bytes.  Currently limit to 64 descriptors
640 * due to the 8139C+.  We need to put the number of descriptors in the ring
641 * structure and use that value instead.
642 */
643#if !defined(__i386__) && !defined(__amd64__)
644#define RE_FIXUP_RX     1
645#endif
646
647#define RL_TX_DESC_CNT          64
648#define RL_TX_DESC_THLD         4
649#define RL_RX_DESC_CNT          RL_TX_DESC_CNT
650
651#define RL_RX_LIST_SZ           (RL_RX_DESC_CNT * sizeof(struct rl_desc))
652#define RL_TX_LIST_SZ           (RL_TX_DESC_CNT * sizeof(struct rl_desc))
653#define RL_RING_ALIGN           256
654#define RL_IFQ_MAXLEN           512
655#define RL_DESC_INC(x)          (x = (x + 1) % RL_TX_DESC_CNT)
656#define RL_OWN(x)               (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN)
657#define RL_RXBYTES(x)           (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask)
658#define RL_PKTSZ(x)             ((x)/* >> 3*/)
659#ifdef RE_FIXUP_RX
660#define RE_ETHER_ALIGN  sizeof(uint64_t)
661#define RE_RX_DESC_BUFLEN       (MCLBYTES - RE_ETHER_ALIGN)
662#else
663#define RE_ETHER_ALIGN  0
664#define RE_RX_DESC_BUFLEN       MCLBYTES
665#endif
666
667#define RL_ADDR_LO(y)           ((uint64_t) (y) & 0xFFFFFFFF)
668#define RL_ADDR_HI(y)           ((uint64_t) (y) >> 32)
669
670/* see comment in dev/re/if_re.c */
671#define RL_JUMBO_FRAMELEN       7440
672#define RL_JUMBO_MTU            (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
673
674struct rl_softc;
675
676struct rl_dmaload_arg {
677        int                     rl_idx;
678        int                     rl_maxsegs;
679        uint32_t                rl_flags;
680        struct rl_desc          *rl_ring;
681};
682
683struct rl_list_data {
684        struct mbuf             *rl_tx_mbuf[RL_TX_DESC_CNT];
685        struct mbuf             *rl_rx_mbuf[RL_RX_DESC_CNT];
686        int                     rl_tx_prodidx;
687        int                     rl_rx_prodidx;
688        int                     rl_tx_considx;
689        int                     rl_tx_free;
690        bus_dmamap_t            rl_tx_dmamap[RL_TX_DESC_CNT];
691        bus_dmamap_t            rl_rx_dmamap[RL_RX_DESC_CNT];
692        bus_dma_tag_t           rl_mtag;        /* mbuf mapping tag */
693        bus_dma_tag_t           rl_stag;        /* stats mapping tag */
694        bus_dmamap_t            rl_smap;        /* stats map */
695        struct rl_stats         *rl_stats;
696        bus_addr_t              rl_stats_addr;
697        bus_dma_tag_t           rl_rx_list_tag;
698        bus_dmamap_t            rl_rx_list_map;
699        struct rl_desc          *rl_rx_list;
700        bus_addr_t              rl_rx_list_addr;
701        bus_dma_tag_t           rl_tx_list_tag;
702        bus_dmamap_t            rl_tx_list_map;
703        struct rl_desc          *rl_tx_list;
704        bus_addr_t              rl_tx_list_addr;
705};
706
707struct rl_softc {
708        struct ifnet            *rl_ifp;        /* interface info */
709        bus_space_handle_t      rl_bhandle;     /* bus space handle */
710        bus_space_tag_t         rl_btag;        /* bus space tag */
711        device_t                rl_dev;
712        struct resource         *rl_res;
713        struct resource         *rl_irq;
714        void                    *rl_intrhand;
715        device_t                rl_miibus;
716        bus_dma_tag_t           rl_parent_tag;
717        bus_dma_tag_t           rl_tag;
718        uint8_t                 rl_type;
719        int                     rl_eecmd_read;
720        int                     rl_eewidth;
721        uint8_t                 rl_stats_no_timeout;
722        int                     rl_txthresh;
723        struct rl_chain_data    rl_cdata;
724        struct rl_list_data     rl_ldata;
725        struct callout          rl_stat_callout;
726        int                     rl_watchdog_timer;
727        struct mtx              rl_mtx;
728        struct mbuf             *rl_head;
729        struct mbuf             *rl_tail;
730        uint32_t                rl_hwrev;
731        uint32_t                rl_rxlenmask;
732        int                     rl_testmode;
733        int                     rl_if_flags;
734        int                     suspended;      /* 0 = normal  1 = suspended */
735#ifdef DEVICE_POLLING
736        int                     rxcycles;
737#endif
738
739        struct task             rl_txtask;
740        struct task             rl_inttask;
741
742        struct mtx              rl_intlock;
743        int                     rl_txstart;
744        int                     rl_link;
745};
746
747#define RL_LOCK(_sc)            mtx_lock(&(_sc)->rl_mtx)
748#define RL_UNLOCK(_sc)          mtx_unlock(&(_sc)->rl_mtx)
749#define RL_LOCK_ASSERT(_sc)     mtx_assert(&(_sc)->rl_mtx, MA_OWNED)
750
751/*
752 * register space access macros
753 */
754#define CSR_WRITE_STREAM_4(sc, reg, val)        \
755        bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val)
756#define CSR_WRITE_4(sc, reg, val)       \
757        bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val)
758#define CSR_WRITE_2(sc, reg, val)       \
759        bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val)
760#define CSR_WRITE_1(sc, reg, val)       \
761        bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val)
762
763#define CSR_READ_4(sc, reg)             \
764        bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg)
765#define CSR_READ_2(sc, reg)             \
766        bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg)
767#define CSR_READ_1(sc, reg)             \
768        bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg)
769
770#define CSR_SETBIT_1(sc, offset, val)           \
771        CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
772
773#define CSR_CLRBIT_1(sc, offset, val)           \
774        CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
775
776#define CSR_SETBIT_2(sc, offset, val)           \
777        CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
778
779#define CSR_CLRBIT_2(sc, offset, val)           \
780        CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
781
782#define CSR_SETBIT_4(sc, offset, val)           \
783        CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val))
784
785#define CSR_CLRBIT_4(sc, offset, val)           \
786        CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val))
787
788#define RL_TIMEOUT              1000
789
790/*
791 * General constants that are fun to know.
792 *
793 * RealTek PCI vendor ID
794 */
795#define RT_VENDORID                             0x10EC
796
797/*
798 * RealTek chip device IDs.
799 */
800#define RT_DEVICEID_8139D                       0x8039
801#define RT_DEVICEID_8129                        0x8129
802#define RT_DEVICEID_8101E                       0x8136
803#define RT_DEVICEID_8138                        0x8138
804#define RT_DEVICEID_8139                        0x8139
805#define RT_DEVICEID_8169SC                      0x8167
806#define RT_DEVICEID_8168                        0x8168
807#define RT_DEVICEID_8169                        0x8169
808#define RT_DEVICEID_8100                        0x8100
809
810#define RT_REVID_8139CPLUS                      0x20
811
812/*
813 * Accton PCI vendor ID
814 */
815#define ACCTON_VENDORID                         0x1113
816
817/*
818 * Accton MPX 5030/5038 device ID.
819 */
820#define ACCTON_DEVICEID_5030                    0x1211
821
822/*
823 * Nortel PCI vendor ID
824 */
825#define NORTEL_VENDORID                         0x126C
826
827/*
828 * Delta Electronics Vendor ID.
829 */
830#define DELTA_VENDORID                          0x1500
831
832/*
833 * Delta device IDs.
834 */
835#define DELTA_DEVICEID_8139                     0x1360
836
837/*
838 * Addtron vendor ID.
839 */
840#define ADDTRON_VENDORID                        0x4033
841
842/*
843 * Addtron device IDs.
844 */
845#define ADDTRON_DEVICEID_8139                   0x1360
846
847/*
848 * D-Link vendor ID.
849 */
850#define DLINK_VENDORID                          0x1186
851
852/*
853 * D-Link DFE-530TX+ device ID
854 */
855#define DLINK_DEVICEID_530TXPLUS                0x1300
856
857/*
858 * D-Link DFE-5280T device ID
859 */
860#define DLINK_DEVICEID_528T                     0x4300
861
862/*
863 * D-Link DFE-690TXD device ID
864 */
865#define DLINK_DEVICEID_690TXD                   0x1340
866
867/*
868 * Corega K.K vendor ID
869 */
870#define COREGA_VENDORID                         0x1259
871
872/*
873 * Corega FEther CB-TXD device ID
874 */
875#define COREGA_DEVICEID_FETHERCBTXD             0xa117
876
877/*
878 * Corega FEtherII CB-TXD device ID
879 */
880#define COREGA_DEVICEID_FETHERIICBTXD           0xa11e
881
882/*
883 * Corega CG-LAPCIGT device ID
884 */
885#define COREGA_DEVICEID_CGLAPCIGT               0xc107
886
887/*
888 * Linksys vendor ID
889 */
890#define LINKSYS_VENDORID                        0x1737
891
892/*
893 * Linksys EG1032 device ID
894 */
895#define LINKSYS_DEVICEID_EG1032                 0x1032
896
897/*
898 * Linksys EG1032 rev 3 sub-device ID
899 */
900#define LINKSYS_SUBDEVICE_EG1032_REV3           0x0024
901
902/*
903 * Peppercon vendor ID
904 */
905#define PEPPERCON_VENDORID                      0x1743
906
907/*
908 * Peppercon ROL-F device ID
909 */
910#define PEPPERCON_DEVICEID_ROLF                 0x8139
911
912/*
913 * Planex Communications, Inc. vendor ID
914 */
915#define PLANEX_VENDORID                         0x14ea
916
917/*
918 * Planex FNW-3603-TX device ID
919 */
920#define PLANEX_DEVICEID_FNW3603TX               0xab06
921
922/*
923 * Planex FNW-3800-TX device ID
924 */
925#define PLANEX_DEVICEID_FNW3800TX               0xab07
926
927/*
928 * LevelOne vendor ID
929 */
930#define LEVEL1_VENDORID                         0x018A
931
932/*
933 * LevelOne FPC-0106TX devide ID
934 */
935#define LEVEL1_DEVICEID_FPC0106TX               0x0106
936
937/*
938 * Compaq vendor ID
939 */
940#define CP_VENDORID                             0x021B
941
942/*
943 * Edimax vendor ID
944 */
945#define EDIMAX_VENDORID                         0x13D1
946
947/*
948 * Edimax EP-4103DL cardbus device ID
949 */
950#define EDIMAX_DEVICEID_EP4103DL                0xAB06
951
952/* US Robotics vendor ID */
953
954#define USR_VENDORID            0x16EC
955
956/* US Robotics 997902 device ID */
957
958#define USR_DEVICEID_997902     0x0116
959
960/*
961 * PCI low memory base and low I/O base register, and
962 * other PCI registers.
963 */
964
965#define RL_PCI_VENDOR_ID        0x00
966#define RL_PCI_DEVICE_ID        0x02
967#define RL_PCI_COMMAND          0x04
968#define RL_PCI_STATUS           0x06
969#define RL_PCI_CLASSCODE        0x09
970#define RL_PCI_LATENCY_TIMER    0x0D
971#define RL_PCI_HEADER_TYPE      0x0E
972#define RL_PCI_LOIO             0x10
973#define RL_PCI_LOMEM            0x14
974#define RL_PCI_BIOSROM          0x30
975#define RL_PCI_INTLINE          0x3C
976#define RL_PCI_INTPIN           0x3D
977#define RL_PCI_MINGNT           0x3E
978#define RL_PCI_MINLAT           0x0F
979#define RL_PCI_RESETOPT         0x48
980#define RL_PCI_EEPROM_DATA      0x4C
981
982#define RL_PCI_CAPID            0x50 /* 8 bits */
983#define RL_PCI_NEXTPTR          0x51 /* 8 bits */
984#define RL_PCI_PWRMGMTCAP       0x52 /* 16 bits */
985#define RL_PCI_PWRMGMTCTRL      0x54 /* 16 bits */
986
987#define RL_PSTATE_MASK          0x0003
988#define RL_PSTATE_D0            0x0000
989#define RL_PSTATE_D1            0x0002
990#define RL_PSTATE_D2            0x0002
991#define RL_PSTATE_D3            0x0003
992#define RL_PME_EN               0x0010
993#define RL_PME_STATUS           0x8000
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