Ticket #87: score603e_g1.diff

File score603e_g1.diff, 22.7 KB (added by Joel Sherrill, on Dec 3, 2006 at 1:31:12 PM)

score603e_g1.diff

  • c/src/lib/libbsp/powerpc/score603e/ChangeLog

    ? c/src/lib/libbsp/powerpc/score603e/gre
    ? c/src/lib/libbsp/powerpc/score603e/grep
    RCS file: /usr1/CVS/rtems/c/src/lib/libbsp/powerpc/score603e/ChangeLog,v
    retrieving revision 1.17
    diff -u -r1.17 ChangeLog
     
     12001-11-28      Joel Sherrill <joel@OARcorp.com>,
     2
     3        This was tracked as PR87.
     4        * README, configure.ac, include/Makefile.am, include/bsp.h,
     5        start/start.S, startup/FPGA.c, startup/Makefile.am, tod/Makefile.am:
     6        Eliminated conditional code for generation 1 boards as these are
     7        no longer available.
     8        * include/gen1.h, startup/82378zb.c, tod/tod_g1.c: Deleted.
     9
    1102001-11-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    211
    312        * Makefile.am: Add @exceptions@ to SUBDIRS.
  • c/src/lib/libbsp/powerpc/score603e/README

    RCS file: /usr1/CVS/rtems/c/src/lib/libbsp/powerpc/score603e/README,v
    retrieving revision 1.1
    diff -u -r1.1 README
     
    33#
    44
    55BSP NAME:           score603e
    6 BOARD:              VISTA SCORE 603e Generation I and II
     6BOARD:              VISTA SCORE 603e Generation II and beyond
    77BUS:                N/A
    88CPU FAMILY:         ppc
    99CPU:                PowerPC 603e
     
    1717TIMERS:             PPC internal Timebase register
    1818  RESOLUTION:         
    1919SERIAL PORTS:       2 Z85C30s
    20 REAL-TIME CLOCK:    Generation  I: SGSM48T18
    21                     Generation II: ICM7170AIBG
     20REAL-TIME CLOCK:    Generation II and beyond: ICM7170AIBG
    2221DMA:                none
    2322VIDEO:              none
    2423SCSI:               none
     
    5150initialization from the SDS debugger and a jump to flash
    5251location 0x04001200.
    5352
    54 The compiler option SCORE603E_GENERATION is set to 1 or 2,
    55 for the generation to be produced.
     53The SCORE603e first generation board is no longer available,
     54does not appear to be in use by any RTEMS users, and thus
     55is no longer supported.
  • c/src/lib/libbsp/powerpc/score603e/configure.ac

    RCS file: /usr1/CVS/rtems/c/src/lib/libbsp/powerpc/score603e/configure.ac,v
    retrieving revision 1.2
    diff -u -r1.2 configure.ac
     
    2020RTEMS_CHECK_BSP_CACHE(RTEMS_BSP)
    2121RTEMS_CANONICAL_HOST
    2222
    23 ## bsp-specific options
    24 RTEMS_BSPOPTS_SET([SCORE603E_GENERATION],[*],[2])
    25 RTEMS_BSPOPTS_HELP([SCORE603E_GENERATION],
    26 [FIXME: Missing explanation])
    27 
    2823RTEMS_BSPOPTS_SET([CONSOLE_USE_INTERRUPTS],[*],[0])
    2924RTEMS_BSPOPTS_HELP([CONSOLE_USE_INTERRUPTS],
    3025[whether using console interrupts])
     
    7772 NOTE: Vectors are actually at 0xFFF00000 but file starts at offset.])
    7873
    7974AM_CONFIG_HEADER(include/bspopts.h)
    80 
    81 AM_CONDITIONAL(SCORE603E_GENERATION_1, test "${SCORE603E_GENERATION}" = "1")
    8275
    8376RTEMS_PROJECT_ROOT
    8477
  • c/src/lib/libbsp/powerpc/score603e/include/Makefile.am

    RCS file: /usr1/CVS/rtems/c/src/lib/libbsp/powerpc/score603e/include/Makefile.am,v
    retrieving revision 1.6
    diff -u -r1.6 Makefile.am
     
    44
    55AUTOMAKE_OPTIONS = foreign 1.4
    66
    7 include_HEADERS = bsp.h coverhd.h gen1.h gen2.h tod.h bspopts.h
     7include_HEADERS = bsp.h coverhd.h gen2.h tod.h bspopts.h
    88
    99$(PROJECT_INCLUDE):
    1010        $(mkinstalldirs) $@
  • c/src/lib/libbsp/powerpc/score603e/include/bsp.h

    RCS file: /usr1/CVS/rtems/c/src/lib/libbsp/powerpc/score603e/include/bsp.h,v
    retrieving revision 1.4
    diff -u -r1.4 bsp.h
     
    4444#include <clockdrv.h>
    4545#include <iosupp.h>
    4646
     47/*
     48 *  We no longer support the first generation board.
     49 */
    4750
    48 #if (SCORE603E_GENERATION == 1)
    49 #include <gen1.h>
    50 #elif (SCORE603E_GENERATION == 2)
    5151#include <gen2.h>
    52 #else
    53 #error "Unknown Generation of  Score603e"
    54 #endif
    55 
    5652
    5753/*
    5854 * The following macro calculates the Baud constant. For the Z8530 chip.
  • /

    RCS file: gen1.h
    diff -N gen1.h
    old new  
    1 /*  Gen1.h
    2  *
    3  *  This include file contains all Generation 1 board addreses
    4  *
    5  *  COPYRIGHT (c) 1989-1997.
    6  *  On-Line Applications Research Corporation (OAR).
    7  *
    8  *  The license and distribution terms for this file may in
    9  *  the file LICENSE in this distribution or at
    10  *  http://www.OARcorp.com/rtems/license.html.
    11  *
    12  *  $Id:
    13  */
    14 
    15 #ifndef __SCORE_GENERATION_1_h
    16 #define __SCORE_GENERATION_1_h
    17 
    18 #ifdef __cplusplus
    19 extern "C" {
    20 #endif
    21 
    22 #include <rtems.h>
    23 
    24 /*
    25  * ISA/PCI I/O space.
    26  */
    27 #define SCORE603E_VME_JUMPER_ADDR      0x00e20000
    28 #define SCORE603E_FLASH_BASE_ADDR      0x01000000
    29 #define SCORE603E_ISA_PCI_IO_BASE      0x80000000
    30 #define SCORE603E_TIMER_PORT_C         0x80000278
    31 #define SCORE603E_TIMER_INT_ACK        0x8000027a
    32 #define SCORE603E_TIMER_PORT_B         0x8000027b
    33 #define SCORE603E_TIMER_PORT_A         0x8000027c
    34 #define SCORE603E_85C30_CTRL_1         ((volatile rtems_unsigned8 *)0x800002f8)
    35 #define SCORE603E_85C30_INT_ACK        ((volatile rtems_unsigned8 *)0x800002fa)
    36 #define SCORE603E_85C30_CTRL_0         ((volatile rtems_unsigned8 *)0x800002fb)
    37 #define SCORE603E_85C30_DATA_1         ((volatile rtems_unsigned8 *)0x800002fc)
    38 #define SCORE603E_85C30_DATA_0         ((volatile rtems_unsigned8 *)0x800002ff)
    39 #define SCORE603E_85C30_CTRL_3         ((volatile rtems_unsigned8 *)0x800003f8)
    40 #define SCORE603E_85C30_CTRL_2         ((volatile rtems_unsigned8 *)0x800003fb)
    41 #define SCORE603E_85C30_DATA_3         ((volatile rtems_unsigned8 *)0x800003fc)
    42 #define SCORE603E_85C30_DATA_2         ((volatile rtems_unsigned8 *)0x800003ff)
    43 #define SCORE603E_PCI_IO_CFG_ADDR      0x80000cf8
    44 #define SCORE603E_PCI_IO_CFG_DATA      0x80000cfc
    45 
    46 #define SCORE603E_UNIVERSE_BASE        0x80030000
    47 #define SCORE603E_IO_VME_UNIVERSE_BASE 0x80007000
    48 #define SCORE603E_PCI_MEM_BASE         0xc0000000
    49 #define SCORE603E_NVRAM_BASE           0xc00f0000
    50 #define SCORE603E_RTC_ADDRESS          ((volatile unsigned char *)0xc00f1ff8)
    51 #define SCORE603E_JP1_JP2_PROM_BASE    0xfff00000
    52 #define SCORE603E_NOT_JP1_2_FLASH_BASE 0xff800000
    53 
    54 #define SCORE603E_VME_A16_OFFSET       0x04000000
    55 #define SCORE603E_VME_A16_BASE         (SCORE603E_PCI_MEM_BASE+SCORE603E_VME_A16_OFFSET)
    56 
    57 #define SCORE603E_BOARD_CTRL_REG       ((volatile rtems_unsigned32*)0x80000800)
    58 #define SCORE603E_BRD_FLASH_DISABLE_MASK     0x02000000
    59 
    60  /*
    61  *  Z85C30 Definations for the 232 interface.
    62  */
    63 #define SCORE603E_85C30_0_CLOCK     10000000         /* 10,000,000 */
    64 #define SCORE603E_85C30_0_CLOCK_X       16 
    65 
    66 /*
    67  *  Z85C30 Definations for the 422 interface.
    68  */
    69 #define SCORE603E_85C30_1_CLOCK     10000000         /* 10,000,000 */
    70 #define SCORE603E_85C30_1_CLOCK_X       16 
    71 
    72 
    73 #define SCORE603E_UNIVERSE_CHIP_ID     0x000010E3
    74 
    75 /*
    76  *  Score603e Interupt Definations.
    77  */
    78 
    79 /*
    80  * First Score Unique IRQ
    81  */
    82 #define Score_IRQ_First ( PPC_IRQ_LAST +  1 )
    83 
    84 /*
    85  * 82378ZB IRQ definations.
    86  */
    87 #define SCORE603E_IRQ00_82378ZB   ( Score_IRQ_First +  0 ) 
    88 #define SCORE603E_IRQ01_82378ZB   ( Score_IRQ_First +  1 ) 
    89 #define SCORE603E_IRQ02_82378ZB   ( Score_IRQ_First +  2 )
    90 #define SCORE603E_IRQ03_82378ZB   ( Score_IRQ_First +  3 )
    91 #define SCORE603E_IRQ04_82378ZB   ( Score_IRQ_First +  4 )
    92 #define SCORE603E_IRQ05_82378ZB   ( Score_IRQ_First +  5 )
    93 #define SCORE603E_IRQ06_82378ZB   ( Score_IRQ_First +  6 )
    94 #define SCORE603E_IRQ07_82378ZB   ( Score_IRQ_First +  7 )
    95 #define SCORE603E_IRQ08_82378ZB   ( Score_IRQ_First +  8 )
    96 #define SCORE603E_IRQ09_82378ZB   ( Score_IRQ_First +  9 )
    97 #define SCORE603E_IRQ10_82378ZB   ( Score_IRQ_First + 10 )
    98 #define SCORE603E_IRQ11_82378ZB   ( Score_IRQ_First + 11 )
    99 #define SCORE603E_IRQ12_82378ZB   ( Score_IRQ_First + 12 )
    100 #define SCORE603E_IRQ13_82378ZB   ( Score_IRQ_First + 13 )
    101 #define SCORE603E_IRQ14_82378ZB   ( Score_IRQ_First + 14 )
    102 #define SCORE603E_IRQ15_82378ZB   ( Score_IRQ_First + 15 )
    103 
    104 #define MAX_BOARD_IRQS             SCORE603E_IRQ15_82378ZB
    105 
    106 #define SCORE603E_85C30_1_IRQ          SCORE603E_IRQ03_82378ZB   
    107 #define SCORE603E_85C30_0_IRQ          SCORE603E_IRQ04_82378ZB
    108 #define SCORE603E_UNIVERSE_IRQ         SCORE603E_IRQ12_82378ZB
    109 
    110 
    111 #define Write_82378ZB( _offset, _data ) { \
    112   volatile rtems_unsigned8 *addr;         \
    113   addr = (volatile rtems_unsigned8 *)(SCORE603E_ISA_PCI_IO_BASE + _offset);\
    114   *addr = _data;                         }
    115 
    116 #define Read_82378ZB( _offset, _data ) { \
    117   volatile rtems_unsigned8 *addr;         \
    118   addr = (volatile rtems_unsigned8 *)(SCORE603E_ISA_PCI_IO_BASE + _offset);\
    119   _data = *addr;                         }
    120 
    121 
    122 /*
    123  *  BSP_TIMER_AVG_OVERHEAD and BSP_TIMER_LEAST_VALID for the shared timer
    124  *  driver.
    125  */
    126 
    127 #define BSP_TIMER_AVG_OVERHEAD   4  /* It typically takes xx clicks        */
    128                                     /*     to start/stop the timer.        */
    129 #define BSP_TIMER_LEAST_VALID    1  /* Don't trust a value lower than this */
    130 
    131 /*
    132  *  Convert decrement value to tenths of microsecnds (used by
    133  *  shared timer driver).
    134  *
    135  *    + CPU has a 66.67 Mhz bus,
    136  *    + There are 4 bus cycles per click
    137  *    + We return value in 1/10 microsecond units.
    138  *   Modified following equation to integer equation to remove
    139  *   floating point math.
    140  *   (int) ((float)(_value) / ((66.67 * 0.1) / 4.0))
    141  */
    142 
    143 #define BSP_Convert_decrementer( _value ) \
    144   (int) (((_value) * 4000) / 6667)
    145 
    146 #ifdef __cplusplus
    147 }
    148 #endif
    149 
    150 #endif
    151 
    152 
    153 
    154 
  • c/src/lib/libbsp/powerpc/score603e/start/start.S

    RCS file: /usr1/CVS/rtems/c/src/lib/libbsp/powerpc/score603e/start/start.S,v
    retrieving revision 1.4
    diff -u -r1.4 start.S
     
    1717 *  $Id: start.S,v 1.4 2001/11/21 18:35:11 joel Exp $
    1818 */
    1919
    20 #include <bspopts.h> /* for SCORE603E_GENERATION */
    2120#include "ppc-asm.h"
    2221
    2322        .file   "start.s"
     
    6867        ori     r4,r4,0x0000            /* 0x2030  */
    6968        mtmsr   r4
    7069       
    71 #if (SCORE603E_GENERATION == 1)
    72         lis     r4,0
    73         mtspr   530,r4                  /* Set IBAT1U */
    74         mtspr   531,r4                  /* Set IBAT1L */
    75         mtspr   534,r4                  /* Set IBAT3U */
    76         mtspr   535,r4                  /* Set IBAT3L */
    77         mtspr   538,r4                  /* Set DBAT1U */
    78         mtspr   539,r4                  /* Set DBAT1L */
    79         lis     r4,0
    80         ori     r4,r4,0x1fff
    81         mtspr   528,r4                  /* Set IBAT0U */
    82         mtspr   536,r4                  /* Set DBAT0U */
    83         lis     r4,0
    84         ori     r4,r4,0x0002   
    85         mtspr   529,r4                  /* Set IBAT0L */
    86         mtspr   537,r4                  /* Set DBAT0L */
    87         lis     r4,-4096                /*  0xf000    */
    88         ori     r4,r4,8191              /*  0x1fff    */
    89         mtspr   532,r4                  /* Set IBAT2U */
    90         mtspr   540,r4                  /* Set DBAT2U */
    91         lis     r4,-4096                /*  0xf000    */
    92         ori     r4,r4,1
    93         mtspr   533,r4                  /* Set IBAT2L */
    94         mtspr   541,r4                  /* Set DBAT2L */
    95         lis     r4,-32768               /*  0x8000    */
    96         ori     r4,r4,8191              /*  0x1fff    */
    97         mtspr   542,r4                  /* Set DBAT3U */
    98         lis     r4,-32768               /*  0x8000    */
    99         ori     r4,r4,0x003a
    100         mtspr   543,r4                  /* Set DBAT3L */
    101 
    102 #elif (SCORE603E_GENERATION == 2)
    103 /* XXX FILL THIS IN WHEN I GET HELLO TO COME UP. */
    104        
    105 #else
    106 #error "Unknown Generation of  Score603e"
    107 #endif
     70        /* The first generation board needed initialization here but the */
     71        /* second does not. */
    10872
    10973        bl      .Laddr                  /* get current address */
    11074.Laddr:
  • /

    RCS file: 82378zb.c
    diff -N 82378zb.c
    old new  
    1 /*  82378zb.c
    2  *
    3  *  COPYRIGHT (c) 1989-1997.
    4  *  On-Line Applications Research Corporation (OAR).
    5  *
    6  *  The license and distribution terms for this file may in
    7  *  the file LICENSE in this distribution or at
    8  *  http://www.OARcorp.com/rtems/license.html.
    9  *
    10  *  $Id:
    11  */
    12 
    13 #include <bsp.h>
    14 #if (SCORE603E_GENERATION == 1)
    15 #include <string.h>
    16 #include <fcntl.h>
    17 #include <assert.h>
    18 
    19 #include <rtems/libio.h>
    20 #include <rtems/libcsupport.h>
    21 
    22 
    23 /*
    24  * initialize 82378zb
    25  */
    26 void initialize_PCI_bridge ()
    27 {
    28 
    29   /*
    30    * INT CNTRL-1 ICW1
    31    *            LTIM and ICW4
    32    */
    33   Write_82378ZB( 0x20, 0x19);
    34  
    35   /*
    36    * INT CNTRL-1 ICW 2
    37    *     Sets 5 msbs of the base address in the interrupt vector table
    38    *     for the vector  routines to  0100 0 ??
    39    */
    40   Write_82378ZB( 0x21, 0x40 );
    41  
    42   /*
    43    * INT CNTRL-1 ICW 3
    44    *     Cascade CNTRL-2 INT output to IRQ[2] input of CNTRL-1
    45    */
    46   Write_82378ZB( 0x21, 0x04 );
    47  
    48   /*
    49    * INT CNTRL-1 ICW 4
    50    *     Set Microprocessor mode for 80x86 system.
    51    */
    52   Write_82378ZB( 0x21, 0x01 );
    53  
    54   /*
    55    * INT CNTRL-1 OCW 2 
    56    *     Set Non-specific EOI command
    57    */
    58   Write_82378ZB( 0x20, 0x20 );
    59  
    60   /*
    61    * INT CNTRL-1 OCW 3 
    62    *     Interrupt controller in normal mask mode.
    63    *     Disable Poll mode command
    64    *     Read IRQ register.
    65    */
    66   Write_82378ZB( 0x20, 0x2a );
    67  
    68   /*
    69    * INT CNTRL-1 OCW 1
    70    *     Write Interrupt Request mask for IRQ[7:0].  An interrupt request for
    71    *     a masked IRQ will not set the interrupt request register (IRR) bit for
    72    *     that channel.
    73    *
    74    *     XXXX - Was 0xfd Only allowing Timer interrupt through changed to
    75    *            0xe1.
    76    */
    77   Write_82378ZB( 0x21, 0xe1 );
    78  
    79   /*
    80    * INT CNTRL-2 ICW 1
    81    *            LTIM and ICW4
    82    */
    83   Write_82378ZB( 0xa0, 0x19 );
    84  
    85   /*
    86    * INT CNTRL-2 ICW 2
    87    *     Sets 5 msbs of the base address in the interrupt vector table
    88    *     for the vector  routines to  0100 1 ??
    89    */
    90   Write_82378ZB( 0xa1, 0x48 );
    91  
    92   /*
    93    * INT CNTRL-1 ICW 3
    94    *     Slave Identification Code (Must be intialized to 2).
    95    */
    96   Write_82378ZB( 0xa1, 0x02 );
    97  
    98   /*
    99    * INT CNTRL-1 ICW 4
    100    *     Set Microprocessor mode for 80x86 system.
    101    */
    102   Write_82378ZB( 0xa1, 0x01 );
    103  
    104   /*
    105    * INT CNTRL-1 OCW 2 
    106    *     Set Non-specific EOI command
    107    */
    108   Write_82378ZB( 0xa0, 0x20 );
    109  
    110   /*
    111    * INT CNTRL-1 OCW 3 
    112    *     Interrupt controller in normal mask mode.
    113    *     Disable Poll mode command
    114    *     Read IRQ register.
    115    */
    116   Write_82378ZB( 0xa0, 0x2a );
    117  
    118   /*
    119    * INT CNTRL-1 OCW 1
    120    *     Write Interrupt Request mask for IRQ[7:0].  An interrupt request for
    121    *     a masked IRQ will not set the interrupt request register (IRR) bit for
    122    *     that channel.
    123    *
    124    *     XXXX - All interrupts masked.
    125    */
    126   Write_82378ZB( 0xa1, 0xff );
    127 }
    128 
    129 
    130 rtems_unsigned16 read_and_clear_irq ()
    131 {
    132   rtems_unsigned16 irq;
    133 
    134   /*
    135    * XXX - Fix this for all interrupts later
    136    */
    137 
    138   Write_82378ZB( 0x20, 0x0c);
    139   Read_82378ZB( 0x20, irq );
    140   irq &= 0x7; 
    141   Write_82378ZB( 0x20, 0x20 );
    142  
    143   return irq;
    144 }
    145 
    146 void init_irq_data_register()
    147 {
    148   assert (0);
    149 }
    150 rtems_unsigned16 get_irq_mask()
    151 {
    152   assert (0);
    153   return 0;
    154 }
    155 void set_irq_mask(
    156   rtems_unsigned16 value
    157 )
    158 {
    159   assert (0);
    160 }
    161 #endif /* end of generation 1 */
  • c/src/lib/libbsp/powerpc/score603e/startup/FPGA.c

    RCS file: /usr1/CVS/rtems/c/src/lib/libbsp/powerpc/score603e/startup/FPGA.c,v
    retrieving revision 1.4
    diff -u -r1.4 FPGA.c
     
    1 /*  FPGA.c
     1/*  FPGA.c -- Bridge for second and subsequent generations
    22 *
    3  *  COPYRIGHT (c) 1989-1997.
     3 *  COPYRIGHT (c) 1989-2001.
    44 *  On-Line Applications Research Corporation (OAR).
    55 *
    66 *  The license and distribution terms for this file may in
     
    1111 */
    1212
    1313#include <bsp.h>
    14 #if (SCORE603E_GENERATION == 2)
    1514#include <string.h>
    1615#include <fcntl.h>
    1716#include <assert.h>
     
    164163
    165164  return irq;
    166165}
    167 
    168 #endif /* end of generation 2 */
    169 
  • c/src/lib/libbsp/powerpc/score603e/startup/Makefile.am

    RCS file: /usr1/CVS/rtems/c/src/lib/libbsp/powerpc/score603e/startup/Makefile.am,v
    retrieving revision 1.3
    diff -u -r1.3 Makefile.am
     
    99PGM = $(ARCH)/startup.rel
    1010
    1111#
    12 # First and second generation use different Bridge chips :(
    13 #       Generation 1 --> 82378zb
     12# First and second generation used different Bridge chips :(
     13#       Generation 1 --> 82378zb (now in the CVS Attic)
    1414#       Generation 2 --> FPGA
    15 STARTUP_C_FILES = 82378zb.c FPGA.c
     15STARTUP_C_FILES = FPGA.c
    1616
    1717C_FILES = bspclean.c bsplibc.c bsppost.c bspstart.c bootcard.c main.c sbrk.c \
    1818    setvec.c Hwr_init.c spurious.c genpvec.c $(STARTUP_C_FILES) \
     
    4141
    4242.PRECIOUS: $(PGM)
    4343
    44 EXTRA_DIST = 82378zb.c FPGA.c Hwr_init.c bspclean.c bspstart.c genpvec.c \
     44EXTRA_DIST = FPGA.c Hwr_init.c bspclean.c bspstart.c genpvec.c \
    4545    linkcmds setvec.c spurious.c vmeintr.c
    4646
    4747include $(top_srcdir)/../../../../../../automake/local.am
  • c/src/lib/libbsp/powerpc/score603e/tod/Makefile.am

    RCS file: /usr1/CVS/rtems/c/src/lib/libbsp/powerpc/score603e/tod/Makefile.am,v
    retrieving revision 1.4
    diff -u -r1.4 Makefile.am
     
    1010include $(top_srcdir)/../../../../../../automake/compile.am
    1111include $(top_srcdir)/../../../../../../automake/lib.am
    1212
    13 # generation 1
    14 if SCORE603E_GENERATION_1
    15 TOD_C_FILES = tod_g1.c
    16 else
    17 # generation 2
     13# TOD for Generation 2 or later
    1814TOD_C_FILES = tod.c
    19 endif
    2015
    2116C_FILES = $(TOD_C_FILES)
    2217C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
     
    3631
    3732.PRECIOUS: $(PGM)
    3833
    39 EXTRA_DIST = tod.c tod_g1.c
     34EXTRA_DIST = tod.c
    4035
    4136include $(top_srcdir)/../../../../../../automake/local.am
  • /

    RCS file: tod_g1.c
    diff -N tod_g1.c
    old new  
    1 /*
    2  * Real Time Clock (SGS-Thomson M48T08/M48T18) for RTEMS
    3  *
    4  *  This part is only found on the first generation board.
    5  *
    6  *  Based on MVME162 TOD Driver by:
    7  *    COPYRIGHT (C) 1997
    8  *    by Katsutoshi Shibuya - BU Denken Co.,Ltd. - Sapporo - JAPAN
    9  *    ALL RIGHTS RESERVED
    10  *
    11  *  The license and distribution terms for this file may be
    12  *  found in the file LICENSE in this distribution or at
    13  *  http://www.OARcorp.com/rtems/license.html.
    14  *
    15  *  $Id: tod_g1.c,v 1.1 1999/02/19 00:22:33 joel Exp $
    16  */
    17 
    18 #include <rtems.h>
    19 #include <tod.h>
    20 #include <bsp.h>
    21 
    22 /*
    23  *  These routines are M48T08 and M48T18 dependent and should be in
    24  *  a separate support library.
    25  */
    26 
    27 static int M48T08_GetField(
    28   volatile unsigned char *mk48t08,
    29   int                     n,
    30   unsigned char           mask
    31 )
    32 {
    33   unsigned char x;
    34 
    35   x = mk48t08[n] & mask;
    36   return ((x >> 4) * 10) + (x & 0x0f);
    37 }
    38 
    39 static void M48T08_SetField(
    40   volatile unsigned char *mk48t08,
    41   int                     n,
    42   unsigned char           d
    43 )
    44 {
    45   mk48t08[n] = ((d / 10) << 4) + (d % 10);
    46 }
    47 
    48 static void M48T08_GetTOD(
    49   volatile unsigned char *mk48t08,
    50   rtems_time_of_day      *rtc_tod
    51 )
    52 {
    53   int year;
    54 
    55   mk48t08[0] |= 0x40;     /* Stop read register */
    56 
    57   year = M48T08_GetField( mk48t08, 7, 0xff );
    58   if ( year >= 88 )
    59     year += 1900;
    60   else
    61     year += 2000;
    62 
    63   rtc_tod->year   = year;
    64   rtc_tod->month  = M48T08_GetField( mk48t08, 6, 0x1f );
    65   rtc_tod->day    = M48T08_GetField( mk48t08, 5, 0x3f );
    66   rtc_tod->hour   = M48T08_GetField( mk48t08, 3, 0x3f );
    67   rtc_tod->minute = M48T08_GetField( mk48t08, 2, 0x7f );
    68   rtc_tod->second = M48T08_GetField( mk48t08, 1, 0x7f );
    69   rtc_tod->ticks  = 0;
    70   mk48t08[0] &= 0x3f;     /* Release read register */
    71 }
    72 
    73 static void M48T08_SetTOD(
    74   volatile unsigned char *mk48t08,
    75   rtems_time_of_day      *rtc_tod
    76 )
    77 {
    78   int year;
    79 
    80   year = rtc_tod->year;
    81 
    82   if ( year >= 2088 )        /* plan ahead :) */
    83     rtems_fatal_error_occurred( 0xBAD0BAD0 );
    84 
    85   if ( year >= 2000 )
    86     year -= 2000;
    87   else
    88     year -= 1900;
    89 
    90   mk48t08[0] |= 0x80;     /* Stop write register */
    91   M48T08_SetField( mk48t08, 7, year );
    92   M48T08_SetField( mk48t08, 6, rtc_tod->month );
    93   M48T08_SetField( mk48t08, 5, rtc_tod->day );
    94   M48T08_SetField( mk48t08, 4, 1 );      /* I don't know which day of week is */
    95   M48T08_SetField( mk48t08, 3, rtc_tod->hour );
    96   M48T08_SetField( mk48t08, 2, rtc_tod->minute );
    97   M48T08_SetField( mk48t08, 1, rtc_tod->second );
    98   mk48t08[0] &= 0x3f;     /* Write these parameters */
    99 }
    100 
    101 /*
    102  *  This code is dependent on the Vista 603e's use of the M48T18 RTC/NVRAM
    103  *  and should remain in this file.
    104  */
    105 
    106 void setRealTimeToRTEMS()
    107 {
    108   rtems_time_of_day rtc_tod;
    109 
    110   M48T08_GetTOD( SCORE603E_RTC_ADDRESS, &rtc_tod );
    111   rtems_clock_set( &rtc_tod );
    112 }
    113 
    114 void setRealTimeFromRTEMS()
    115 {
    116   rtems_time_of_day rtems_tod;
    117 
    118   rtems_clock_get( RTEMS_CLOCK_GET_TOD, &rtems_tod );
    119   M48T08_SetTOD( SCORE603E_RTC_ADDRESS, &rtems_tod );
    120 }
    121 
    122 int checkRealTime()
    123 {
    124   rtems_time_of_day rtems_tod;
    125   rtems_time_of_day rtc_tod;
    126 
    127   M48T08_GetTOD( SCORE603E_RTC_ADDRESS, &rtc_tod );
    128   rtems_clock_get( RTEMS_CLOCK_GET_TOD, &rtems_tod );
    129 
    130   if( rtems_tod.year == rtc_tod.year &&
    131       rtems_tod.month == rtc_tod.month &&
    132       rtems_tod.day == rtc_tod.day ) {
    133      return ((rtems_tod.hour   - rtc_tod.hour) * 3600) +
    134             ((rtems_tod.minute - rtc_tod.minute) * 60) +
    135              (rtems_tod.second - rtc_tod.second);
    136   }
    137   return 9999;
    138 }