1 | Index: score603e/include/bsp.h |
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2 | =================================================================== |
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3 | RCS file: /usr1/CVS/rtems/c/src/lib/libbsp/powerpc/score603e/include/bsp.h,v |
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4 | retrieving revision 1.5.4.1 |
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5 | diff -c -r1.5.4.1 bsp.h |
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6 | *** score603e/include/bsp.h 4 Sep 2003 18:45:16 -0000 1.5.4.1 |
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7 | --- score603e/include/bsp.h 11 Apr 2005 17:41:38 -0000 |
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8 | *************** |
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9 | *** 69,75 **** |
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10 | |
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11 | #define Initialize_Board_ctrl_register() \ |
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12 | *SCORE603E_BOARD_CTRL_REG = (*SCORE603E_BOARD_CTRL_REG | \ |
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13 | ! SCORE603E_BRD_FLASH_DISABLE_MASK) \ |
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14 | |
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15 | /* |
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16 | * Define the time limits for RTEMS Test Suite test durations. |
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17 | --- 69,78 ---- |
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18 | |
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19 | #define Initialize_Board_ctrl_register() \ |
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20 | *SCORE603E_BOARD_CTRL_REG = (*SCORE603E_BOARD_CTRL_REG | \ |
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21 | ! SCORE603E_BRD_FLASH_DISABLE_MASK) |
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22 | ! |
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23 | ! #define Processor_Synchronize() \ |
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24 | ! asm(" eieio ") |
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25 | |
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26 | /* |
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27 | * Define the time limits for RTEMS Test Suite test durations. |
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28 | *************** |
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29 | *** 249,254 **** |
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30 | --- 252,260 ---- |
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31 | rtems_unsigned32 area /* Unused */ |
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32 | ); |
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33 | |
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34 | + #define BSP_FLASH_ENABLE_WRITES( _area) SCORE603e_FLASH_Enable_writes( _area ) |
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35 | + #define BSP_FLASH_DISABLE_WRITES(_area) SCORE603e_FLASH_Disable( _area ) |
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36 | + |
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37 | #define Convert_Endian_32( _data ) \ |
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38 | ( ((_data&0x000000ff)<<24) | ((_data&0x0000ff00)<<8) | \ |
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39 | ((_data&0x00ff0000)>>8) | ((_data&0xff000000)>>24) ) |
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40 | Index: score603e/include/gen2.h |
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41 | =================================================================== |
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42 | RCS file: /usr1/CVS/rtems/c/src/lib/libbsp/powerpc/score603e/include/gen2.h,v |
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43 | retrieving revision 1.2.4.1 |
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44 | diff -c -r1.2.4.1 gen2.h |
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45 | *** score603e/include/gen2.h 4 Sep 2003 18:45:16 -0000 1.2.4.1 |
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46 | --- score603e/include/gen2.h 11 Apr 2005 17:41:38 -0000 |
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47 | *************** |
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48 | *** 25,31 **** |
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49 | * ISA/PCI I/O space. |
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50 | */ |
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51 | #define SCORE603E_VME_JUMPER_ADDR 0x00e20000 |
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52 | ! #define SCORE603E_FLASH_BASE_ADDR 0x04000000 |
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53 | #define SCORE603E_ISA_PCI_IO_BASE 0x80000000 |
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54 | #define SCORE603E_TIMER_PORT_C 0xfd000000 |
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55 | #define SCORE603E_TIMER_INT_ACK 0xfd000000 |
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56 | --- 25,31 ---- |
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57 | * ISA/PCI I/O space. |
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58 | */ |
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59 | #define SCORE603E_VME_JUMPER_ADDR 0x00e20000 |
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60 | ! #define BSP_FLASH_BASE 0x04000000 |
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61 | #define SCORE603E_ISA_PCI_IO_BASE 0x80000000 |
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62 | #define SCORE603E_TIMER_PORT_C 0xfd000000 |
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63 | #define SCORE603E_TIMER_INT_ACK 0xfd000000 |
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64 | *************** |
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65 | *** 47,108 **** |
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66 | /* |
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67 | * PSC8 - PMC Card |
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68 | */ |
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69 | ! #define SCORE603E_PCI_CONFIGURATION_BASE 0x80800000 |
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70 | ! #define SCORE603E_PMC_BASE SCORE603E_PCI_CONFIGURATION_BASE |
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71 | ! #define SCORE603E_PCI_PMC_DEVICE_BASE 0x80808000 |
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72 | |
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73 | ! #define SCORE603E_PCI_REGISTER_BASE 0xfc000000 |
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74 | |
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75 | - #define SCORE603E_PCI_DEVICE_ADDRESS( _offset) \ |
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76 | - ((volatile rtems_unsigned32 *)( SCORE603E_PCI_PMC_DEVICE_BASE + _offset )) |
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77 | - |
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78 | |
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79 | ! #define SCORE603E_PMC_SERIAL_ADDRESS( _offset ) \ |
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80 | ! ((volatile rtems_unsigned8 *)(SCORE603E_PCI_REGISTER_BASE + _offset)) |
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81 | |
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82 | /* |
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83 | * PMC serial channels - (4-7: 232 and 8-11: 422) |
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84 | */ |
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85 | ! #define SCORE603E_85C30_CTRL_4 SCORE603E_PMC_SERIAL_ADDRESS(0x200020) |
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86 | ! #define SCORE603E_85C30_DATA_4 SCORE603E_PMC_SERIAL_ADDRESS(0x200024) |
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87 | ! #define SCORE603E_85C30_CTRL_5 SCORE603E_PMC_SERIAL_ADDRESS(0x200028) |
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88 | ! #define SCORE603E_85C30_DATA_5 SCORE603E_PMC_SERIAL_ADDRESS(0x20002c) |
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89 | ! #define SCORE603E_85C30_CTRL_6 SCORE603E_PMC_SERIAL_ADDRESS(0x200030) |
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90 | ! #define SCORE603E_85C30_DATA_6 SCORE603E_PMC_SERIAL_ADDRESS(0x200034) |
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91 | ! #define SCORE603E_85C30_CTRL_7 SCORE603E_PMC_SERIAL_ADDRESS(0x200038) |
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92 | ! #define SCORE603E_85C30_DATA_7 SCORE603E_PMC_SERIAL_ADDRESS(0x20003c) |
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93 | ! #define SCORE603E_85C30_CTRL_8 SCORE603E_PMC_SERIAL_ADDRESS(0x200000) |
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94 | ! #define SCORE603E_85C30_DATA_8 SCORE603E_PMC_SERIAL_ADDRESS(0x200004) |
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95 | ! #define SCORE603E_85C30_CTRL_9 SCORE603E_PMC_SERIAL_ADDRESS(0x200008) |
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96 | ! #define SCORE603E_85C30_DATA_9 SCORE603E_PMC_SERIAL_ADDRESS(0x20000c) |
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97 | ! #define SCORE603E_85C30_CTRL_10 SCORE603E_PMC_SERIAL_ADDRESS(0x200010) |
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98 | ! #define SCORE603E_85C30_DATA_10 SCORE603E_PMC_SERIAL_ADDRESS(0x200014) |
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99 | ! #define SCORE603E_85C30_CTRL_11 SCORE603E_PMC_SERIAL_ADDRESS(0x200018) |
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100 | ! #define SCORE603E_85C30_DATA_11 SCORE603E_PMC_SERIAL_ADDRESS(0x20001c) |
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101 | |
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102 | #define SCORE603E_PCI_IO_CFG_ADDR 0x80000cf8 |
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103 | #define SCORE603E_PCI_IO_CFG_DATA 0x80000cfc |
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104 | |
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105 | #define SCORE603E_UNIVERSE_BASE 0x80030000 |
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106 | #define SCORE603E_IO_VME_UNIVERSE_BASE 0x80007000 |
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107 | ! #define SCORE603E_PCI_MEM_BASE 0xc0000000 |
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108 | ! #define SCORE603E_NVRAM_BASE 0xfd100000 |
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109 | ! #define SCORE603E_RTC_ADDRESS ((volatile unsigned char *)0xfd180000) |
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110 | #define SCORE603E_JP1_JP2_PROM_BASE 0xfff00000 |
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111 | #define SCORE603E_NOT_JP1_2_FLASH_BASE 0xff800000 |
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112 | |
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113 | - |
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114 | #if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE) |
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115 | #define SCORE603E_VME_A16_OFFSET 0x04000000 |
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116 | #elif (SCORE603E_USE_DINK) |
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117 | #define SCORE603E_VME_A16_OFFSET 0x11000000 |
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118 | #define SCORE603E_VME_A24_OFFSET 0x10000000 |
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119 | ! #define SCORE603E_VME_A24_BASE (SCORE603E_PCI_MEM_BASE+SCORE603E_VME_A24_OFFSET) |
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120 | #else |
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121 | #error "SCORE603E gen2.h -- what ROM monitor are you using" |
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122 | #endif |
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123 | |
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124 | ! #define SCORE603E_VME_A16_BASE (SCORE603E_PCI_MEM_BASE+SCORE603E_VME_A16_OFFSET) |
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125 | |
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126 | /* |
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127 | * Definations for the ICM 1770 RTC chip |
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128 | --- 47,107 ---- |
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129 | /* |
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130 | * PSC8 - PMC Card |
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131 | */ |
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132 | ! #define BSP_PCI_CONFIGURATION_BASE 0x80800000 |
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133 | ! #define BSP_PMC_BASE BSP_PCI_CONFIGURATION_BASE |
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134 | ! #define BSP_PCI_PMC_DEVICE_BASE 0x80808000 |
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135 | |
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136 | ! #define BSP_PCI_REGISTER_BASE 0xfc000000 |
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137 | ! |
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138 | ! #define BSP_PCI_DEVICE_ADDRESS( _offset) \ |
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139 | ! ((volatile rtems_unsigned32 *)( BSP_PCI_PMC_DEVICE_BASE + _offset )) |
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140 | |
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141 | |
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142 | ! #define BSP_PMC_SERIAL_ADDRESS( _offset ) \ |
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143 | ! ((volatile rtems_unsigned8 *)(BSP_PCI_REGISTER_BASE + _offset)) |
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144 | |
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145 | /* |
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146 | * PMC serial channels - (4-7: 232 and 8-11: 422) |
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147 | */ |
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148 | ! #define SCORE603E_85C30_CTRL_4 BSP_PMC_SERIAL_ADDRESS(0x200020) |
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149 | ! #define SCORE603E_85C30_DATA_4 BSP_PMC_SERIAL_ADDRESS(0x200024) |
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150 | ! #define SCORE603E_85C30_CTRL_5 BSP_PMC_SERIAL_ADDRESS(0x200028) |
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151 | ! #define SCORE603E_85C30_DATA_5 BSP_PMC_SERIAL_ADDRESS(0x20002c) |
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152 | ! #define SCORE603E_85C30_CTRL_6 BSP_PMC_SERIAL_ADDRESS(0x200030) |
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153 | ! #define SCORE603E_85C30_DATA_6 BSP_PMC_SERIAL_ADDRESS(0x200034) |
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154 | ! #define SCORE603E_85C30_CTRL_7 BSP_PMC_SERIAL_ADDRESS(0x200038) |
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155 | ! #define SCORE603E_85C30_DATA_7 BSP_PMC_SERIAL_ADDRESS(0x20003c) |
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156 | ! #define SCORE603E_85C30_CTRL_8 BSP_PMC_SERIAL_ADDRESS(0x200000) |
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157 | ! #define SCORE603E_85C30_DATA_8 BSP_PMC_SERIAL_ADDRESS(0x200004) |
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158 | ! #define SCORE603E_85C30_CTRL_9 BSP_PMC_SERIAL_ADDRESS(0x200008) |
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159 | ! #define SCORE603E_85C30_DATA_9 BSP_PMC_SERIAL_ADDRESS(0x20000c) |
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160 | ! #define SCORE603E_85C30_CTRL_10 BSP_PMC_SERIAL_ADDRESS(0x200010) |
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161 | ! #define SCORE603E_85C30_DATA_10 BSP_PMC_SERIAL_ADDRESS(0x200014) |
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162 | ! #define SCORE603E_85C30_CTRL_11 BSP_PMC_SERIAL_ADDRESS(0x200018) |
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163 | ! #define SCORE603E_85C30_DATA_11 BSP_PMC_SERIAL_ADDRESS(0x20001c) |
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164 | |
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165 | #define SCORE603E_PCI_IO_CFG_ADDR 0x80000cf8 |
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166 | #define SCORE603E_PCI_IO_CFG_DATA 0x80000cfc |
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167 | |
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168 | #define SCORE603E_UNIVERSE_BASE 0x80030000 |
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169 | #define SCORE603E_IO_VME_UNIVERSE_BASE 0x80007000 |
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170 | ! #define BSP_PCI_MEM_BASE 0xc0000000 |
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171 | ! #define BSP_NVRAM_BASE 0xfd100000 |
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172 | ! #define BSP_RTC_ADDRESS ((volatile unsigned char *)0xfd180000) |
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173 | #define SCORE603E_JP1_JP2_PROM_BASE 0xfff00000 |
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174 | #define SCORE603E_NOT_JP1_2_FLASH_BASE 0xff800000 |
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175 | |
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176 | #if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE) |
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177 | #define SCORE603E_VME_A16_OFFSET 0x04000000 |
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178 | #elif (SCORE603E_USE_DINK) |
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179 | #define SCORE603E_VME_A16_OFFSET 0x11000000 |
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180 | #define SCORE603E_VME_A24_OFFSET 0x10000000 |
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181 | ! #define BSP_VME_A24_BASE (BSP_PCI_MEM_BASE+SCORE603E_VME_A24_OFFSET) |
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182 | #else |
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183 | #error "SCORE603E gen2.h -- what ROM monitor are you using" |
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184 | #endif |
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185 | |
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186 | ! #define BSP_VME_A16_BASE (BSP_PCI_MEM_BASE+SCORE603E_VME_A16_OFFSET) |
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187 | |
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188 | /* |
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189 | * Definations for the ICM 1770 RTC chip |
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190 | *************** |
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191 | *** 115,121 **** |
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192 | #define ICM1770_CRYSTAL_FREQ_2M 0x02 |
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193 | #define ICM1770_CRYSTAL_FREQ_4M 0x03 |
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194 | |
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195 | ! #define SCORE_RTC_FREQUENCY ICM1770_CRYSTAL_FREQ_32K |
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196 | |
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197 | /* |
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198 | * Z85C30 Definations for the 423 interface. |
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199 | --- 114,120 ---- |
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200 | #define ICM1770_CRYSTAL_FREQ_2M 0x02 |
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201 | #define ICM1770_CRYSTAL_FREQ_4M 0x03 |
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202 | |
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203 | ! #define BSP_RTC_FREQUENCY ICM1770_CRYSTAL_FREQ_32K |
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204 | |
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205 | /* |
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206 | * Z85C30 Definations for the 423 interface. |
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207 | *************** |
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208 | *** 158,170 **** |
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209 | /* |
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210 | * The PMC status word is at the PMC base address |
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211 | */ |
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212 | ! #define SCORE603E_PMC_STATUS_ADDRESS (SCORE603E_PMC_SERIAL_ADDRESS (0)) |
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213 | #define Is_PMC_85C30_4_IRQ( _status ) (_status & 0x80) /* SCC 422-1 */ |
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214 | #define Is_PMC_85C30_2_IRQ( _status ) (_status & 0x40) /* SCC 232-1 */ |
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215 | #define Is_PMC_85C30_5_IRQ( _status ) (_status & 0x20) /* SCC 422-2 */ |
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216 | #define Is_PMC_85C30_3_IRQ( _status ) (_status & 0x08) /* SCC 232-2 */ |
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217 | |
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218 | ! #define SCORE603E_PMC_CONTROL_ADDRESS SCORE603E_PMC_SERIAL_ADDRESS(0x100000) |
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219 | #define SCORE603E_PMC_SCC_232_LOOPBACK (_word) (_word|0x20) |
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220 | |
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221 | #define PMC_SET_232_LOOPBACK(_word) (_word | 0x02) |
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222 | --- 157,169 ---- |
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223 | /* |
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224 | * The PMC status word is at the PMC base address |
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225 | */ |
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226 | ! #define BSP_PMC_STATUS_ADDRESS (BSP_PMC_SERIAL_ADDRESS (0)) |
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227 | #define Is_PMC_85C30_4_IRQ( _status ) (_status & 0x80) /* SCC 422-1 */ |
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228 | #define Is_PMC_85C30_2_IRQ( _status ) (_status & 0x40) /* SCC 232-1 */ |
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229 | #define Is_PMC_85C30_5_IRQ( _status ) (_status & 0x20) /* SCC 422-2 */ |
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230 | #define Is_PMC_85C30_3_IRQ( _status ) (_status & 0x08) /* SCC 232-2 */ |
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231 | |
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232 | ! #define SCORE603E_PMC_CONTROL_ADDRESS BSP_PMC_SERIAL_ADDRESS(0x100000) |
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233 | #define SCORE603E_PMC_SCC_232_LOOPBACK (_word) (_word|0x20) |
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234 | |
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235 | #define PMC_SET_232_LOOPBACK(_word) (_word | 0x02) |
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236 | Index: score603e/startup/FPGA.c |
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237 | =================================================================== |
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238 | RCS file: /usr1/CVS/rtems/c/src/lib/libbsp/powerpc/score603e/startup/FPGA.c,v |
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239 | retrieving revision 1.5.4.1 |
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240 | diff -c -r1.5.4.1 FPGA.c |
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241 | *** score603e/startup/FPGA.c 4 Sep 2003 18:45:16 -0000 1.5.4.1 |
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242 | --- score603e/startup/FPGA.c 11 Apr 2005 17:41:38 -0000 |
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243 | *************** |
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244 | *** 115,121 **** |
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245 | { |
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246 | rtems_unsigned16 status_word = irq; |
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247 | |
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248 | ! status_word = (*SCORE603E_PMC_STATUS_ADDRESS); |
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249 | |
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250 | return status_word; |
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251 | } |
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252 | --- 115,121 ---- |
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253 | { |
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254 | rtems_unsigned16 status_word = irq; |
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255 | |
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256 | ! status_word = (*BSP_PMC_STATUS_ADDRESS); |
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257 | |
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258 | return status_word; |
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259 | } |
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260 | Index: score603e/startup/Hwr_init.c |
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261 | =================================================================== |
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262 | RCS file: /usr1/CVS/rtems/c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c,v |
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263 | retrieving revision 1.2 |
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264 | diff -c -r1.2 Hwr_init.c |
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265 | *** score603e/startup/Hwr_init.c 14 Jan 2000 14:44:11 -0000 1.2 |
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266 | --- score603e/startup/Hwr_init.c 11 Apr 2005 17:41:38 -0000 |
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267 | *************** |
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268 | *** 76,82 **** |
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269 | { |
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270 | volatile Harris_RTC *the_RTC; |
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271 | |
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272 | ! the_RTC = (volatile Harris_RTC *)SCORE603E_RTC_ADDRESS; |
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273 | |
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274 | the_RTC->command_register = 0x0; |
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275 | } |
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276 | --- 76,82 ---- |
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277 | { |
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278 | volatile Harris_RTC *the_RTC; |
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279 | |
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280 | ! the_RTC = (volatile Harris_RTC *)BSP_RTC_ADDRESS; |
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281 | |
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282 | the_RTC->command_register = 0x0; |
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283 | } |
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284 | Index: score603e/startup/bspstart.c |
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285 | =================================================================== |
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286 | RCS file: /usr1/CVS/rtems/c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c,v |
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287 | retrieving revision 1.6.4.1 |
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288 | diff -c -r1.6.4.1 bspstart.c |
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289 | *** score603e/startup/bspstart.c 4 Sep 2003 18:45:16 -0000 1.6.4.1 |
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290 | --- score603e/startup/bspstart.c 11 Apr 2005 17:41:38 -0000 |
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291 | *************** |
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292 | *** 116,135 **** |
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293 | /* |
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294 | * set PMC base address. |
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295 | */ |
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296 | ! PMC_addr = SCORE603E_PCI_DEVICE_ADDRESS( 0x14 ); |
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297 | ! *PMC_addr = (SCORE603E_PCI_REGISTER_BASE >> 24) & 0x3f; |
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298 | |
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299 | /* |
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300 | * Clear status, enable SERR and memory space only. |
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301 | */ |
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302 | ! PMC_addr = SCORE603E_PCI_DEVICE_ADDRESS( 0x4 ); |
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303 | *PMC_addr = 0x0201ff37; |
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304 | |
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305 | /* |
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306 | * Bit 0 and 1 HI cause Medium Loopback to occur. |
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307 | */ |
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308 | PMC_addr = (volatile rtems_unsigned32 *) |
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309 | ! SCORE603E_PMC_SERIAL_ADDRESS( 0x100000 ); |
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310 | data = *PMC_addr; |
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311 | /* *PMC_addr = data | 0x3; */ |
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312 | *PMC_addr = data & 0xfc; |
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313 | --- 116,135 ---- |
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314 | /* |
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315 | * set PMC base address. |
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316 | */ |
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317 | ! PMC_addr = BSP_PCI_DEVICE_ADDRESS( 0x14 ); |
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318 | ! *PMC_addr = (BSP_PCI_REGISTER_BASE >> 24) & 0x3f; |
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319 | |
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320 | /* |
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321 | * Clear status, enable SERR and memory space only. |
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322 | */ |
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323 | ! PMC_addr = BSP_PCI_DEVICE_ADDRESS( 0x4 ); |
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324 | *PMC_addr = 0x0201ff37; |
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325 | |
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326 | /* |
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327 | * Bit 0 and 1 HI cause Medium Loopback to occur. |
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328 | */ |
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329 | PMC_addr = (volatile rtems_unsigned32 *) |
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330 | ! BSP_PMC_SERIAL_ADDRESS( 0x100000 ); |
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331 | data = *PMC_addr; |
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332 | /* *PMC_addr = data | 0x3; */ |
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333 | *PMC_addr = data & 0xfc; |
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334 | *************** |
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335 | *** 142,158 **** |
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336 | /* |
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337 | * Clear status, enable SERR and memory space only. |
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338 | */ |
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339 | ! PMC_addr = SCORE603E_PCI_DEVICE_ADDRESS( 0x4 ); |
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340 | *PMC_addr = 0x020080cc; |
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341 | |
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342 | /* |
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343 | * set PMC base address. |
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344 | */ |
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345 | ! PMC_addr = SCORE603E_PCI_DEVICE_ADDRESS( 0x14 ); |
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346 | ! *PMC_addr = (SCORE603E_PCI_REGISTER_BASE >> 24) & 0x3f; |
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347 | |
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348 | PMC_addr = (volatile rtems_unsigned32 *) |
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349 | ! SCORE603E_PMC_SERIAL_ADDRESS( 0x100000 ); |
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350 | data = *PMC_addr; |
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351 | *PMC_addr = data & 0xfc; |
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352 | |
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353 | --- 142,158 ---- |
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354 | /* |
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355 | * Clear status, enable SERR and memory space only. |
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356 | */ |
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357 | ! PMC_addr = BSP_PCI_DEVICE_ADDRESS( 0x4 ); |
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358 | *PMC_addr = 0x020080cc; |
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359 | |
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360 | /* |
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361 | * set PMC base address. |
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362 | */ |
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363 | ! PMC_addr = BSP_PCI_DEVICE_ADDRESS( 0x14 ); |
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364 | ! *PMC_addr = (BSP_PCI_REGISTER_BASE >> 24) & 0x3f; |
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365 | |
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366 | PMC_addr = (volatile rtems_unsigned32 *) |
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367 | ! BSP_PMC_SERIAL_ADDRESS( 0x100000 ); |
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368 | data = *PMC_addr; |
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369 | *PMC_addr = data & 0xfc; |
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370 | |
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371 | Index: score603e/tod/tod.c |
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372 | =================================================================== |
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373 | RCS file: /usr1/CVS/rtems/c/src/lib/libbsp/powerpc/score603e/tod/tod.c,v |
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374 | retrieving revision 1.2.8.1 |
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375 | diff -c -r1.2.8.1 tod.c |
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376 | *** score603e/tod/tod.c 4 Sep 2003 18:45:16 -0000 1.2.8.1 |
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377 | --- score603e/tod/tod.c 11 Apr 2005 17:41:38 -0000 |
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378 | *************** |
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379 | *** 43,49 **** |
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380 | { |
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381 | rtems_time_of_day rtc_tod; |
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382 | |
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383 | ! ICM7170_GetTOD( SCORE603E_RTC_ADDRESS, SCORE_RTC_FREQUENCY, &rtc_tod ); |
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384 | rtems_clock_set( &rtc_tod ); |
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385 | } |
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386 | |
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387 | --- 43,49 ---- |
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388 | { |
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389 | rtems_time_of_day rtc_tod; |
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390 | |
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391 | ! ICM7170_GetTOD( BSP_RTC_ADDRESS, BSP_RTC_FREQUENCY, &rtc_tod ); |
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392 | rtems_clock_set( &rtc_tod ); |
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393 | } |
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394 | |
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395 | *************** |
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396 | *** 52,58 **** |
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397 | rtems_time_of_day rtems_tod; |
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398 | |
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399 | rtems_clock_get( RTEMS_CLOCK_GET_TOD, &rtems_tod ); |
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400 | ! ICM7170_SetTOD( SCORE603E_RTC_ADDRESS, SCORE_RTC_FREQUENCY, &rtems_tod ); |
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401 | } |
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402 | |
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403 | int checkRealTime() |
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404 | --- 52,58 ---- |
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405 | rtems_time_of_day rtems_tod; |
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406 | |
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407 | rtems_clock_get( RTEMS_CLOCK_GET_TOD, &rtems_tod ); |
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408 | ! ICM7170_SetTOD( BSP_RTC_ADDRESS, BSP_RTC_FREQUENCY, &rtems_tod ); |
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409 | } |
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410 | |
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411 | int checkRealTime() |
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412 | *************** |
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413 | *** 60,66 **** |
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414 | rtems_time_of_day rtems_tod; |
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415 | rtems_time_of_day rtc_tod; |
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416 | |
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417 | ! ICM7170_GetTOD( SCORE603E_RTC_ADDRESS, SCORE_RTC_FREQUENCY, &rtc_tod ); |
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418 | rtems_clock_get( RTEMS_CLOCK_GET_TOD, &rtems_tod ); |
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419 | |
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420 | if( rtems_tod.year == rtc_tod.year && |
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421 | --- 60,66 ---- |
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422 | rtems_time_of_day rtems_tod; |
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423 | rtems_time_of_day rtc_tod; |
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424 | |
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425 | ! ICM7170_GetTOD( BSP_RTC_ADDRESS, BSP_RTC_FREQUENCY, &rtc_tod ); |
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426 | rtems_clock_get( RTEMS_CLOCK_GET_TOD, &rtems_tod ); |
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427 | |
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428 | if( rtems_tod.year == rtc_tod.year && |
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