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Ticket #606: joel-diffs-pr606-2.diff

File joel-diffs-pr606-2.diff, 14.5 KB (added by gregory.menke, on 12/03/06 at 13:31:12)
joel-diffs-pr606-2.diff

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1	diff -N -P -r -c -b -X /home/posixfsw/rtems/production/diff-exclude-files c/src/lib/libbsp/powerpc/shared/ChangeLog /home/posixfsw/rtems/production/rtems-ss-20030703/c/src/lib/libbsp/powerpc/shared/ChangeLog
2	*** c/src/lib/libbsp/powerpc/shared/ChangeLog Mon Sep 27 13:54:54 2004
3	--- /home/posixfsw/rtems/production/rtems-ss-20030703/c/src/lib/libbsp/powerpc/shared/ChangeLog Fri Apr 9 16:00:37 2004
4	***************
5	* 1,5 **
6	2003-11-01 Greg Menke <gregory.menke@gsfc.nasa.gov>
7	-
8	PR 606/bsps
9	* bootloader/pci.c: Fixed IO remapping so buses >= 1 are remapped.
10	Reduced PCI space to match bat2. Fixed incorrect region size
11	--- 1,4 ----
12	diff -N -P -r -c -b -X /home/posixfsw/rtems/production/diff-exclude-files c/src/lib/libbsp/powerpc/shared/bootloader/pci.c /home/posixfsw/rtems/production/rtems-ss-20030703/c/src/lib/libbsp/powerpc/shared/bootloader/pci.c
13	*** c/src/lib/libbsp/powerpc/shared/bootloader/pci.c Thu Sep 4 14:45:20 2003
14	--- /home/posixfsw/rtems/production/rtems-ss-20030703/c/src/lib/libbsp/powerpc/shared/bootloader/pci.c Fri Apr 9 15:58:55 2004
15	***************
16	* 10,18 **
17	*
18	* The license and distribution terms for this file may be
19	* found in found in the file LICENSE in this distribution or at
20	! * http://www.rtems.com/license/LICENSE.
21	*
22	! * $Id: pci.c,v 1.2.4.3 2003/09/04 18:45:20 joel Exp $
23	*/
24
25
26	--- 10,18 ----
27	*
28	* The license and distribution terms for this file may be
29	* found in found in the file LICENSE in this distribution or at
30	! * http://www.OARcorp.com/rtems/license.html.
31	*
32	! * pci.c,v 1.3 2003/06/13 17:39:44 joel Exp
33	*/
34
35
36	***************
37	* 30,35 **
38	--- 30,37 ----
39	typedef unsigned int u32;
40
41
42	+
43	+
44	/*
45	#define DEBUG
46	#define PCI_DEBUG
47	***************
48	* 234,241 **
49	** hardware, its just the builtin stuff we're tiptoeing around.
50	**
51	** Gregm, 7/16/2003
52	*/
53	! if( r->dev->bus->number <= 1 )
54	{
55	if ((r->type==PCI_BASE_ADDRESS_SPACE_IO)
56	? (r->base && r->base <0x10000)
57	--- 236,247 ----
58	** hardware, its just the builtin stuff we're tiptoeing around.
59	**
60	** Gregm, 7/16/2003
61	+ **
62	+ ** Gregm, changed 11/2003 so IO devices only on bus 0 zero are not
63	+ ** remapped. This covers the builtin pc-like io devices- but
64	+ ** properly maps IO devices on higher busses.
65	*/
66	! if( r->dev->bus->number == 0 )
67	{
68	if ((r->type==PCI_BASE_ADDRESS_SPACE_IO)
69	? (r->base && r->base <0x10000)
70	***************
71	* 508,518 **
72	#define BUS0_IO_START 0x10000
73	#define BUS0_IO_END 0x1ffff
74	#define BUS0_MEM_START 0x1000000
75	! #define BUS0_MEM_END 0xaffffff
76
77	#define BUSREST_IO_START 0x20000
78	#define BUSREST_IO_END 0x7ffff
79	! #define BUSREST_MEM_START 0xb000000
80	#define BUSREST_MEM_END 0x10000000
81
82
83	--- 514,524 ----
84	#define BUS0_IO_START 0x10000
85	#define BUS0_IO_END 0x1ffff
86	#define BUS0_MEM_START 0x1000000
87	! #define BUS0_MEM_END 0x3f00000
88
89	#define BUSREST_IO_START 0x20000
90	#define BUSREST_IO_END 0x7ffff
91	! #define BUSREST_MEM_START 0x4000000
92	#define BUSREST_MEM_END 0x10000000
93
94
95	***************
96	* 570,577 **
97	(PCI_BASE_ADDRESS_SPACE_MEMORY\|
98	PCI_BASE_ADDRESS_MEM_TYPE_64)) {
99	pci_write_config_dword(r->dev,
100	! PCI_BASE_ADDRESS_1+
101	! (r->reg<<2),
102	0);
103	}
104	}
105	--- 576,582 ----
106	(PCI_BASE_ADDRESS_SPACE_MEMORY\|
107	PCI_BASE_ADDRESS_MEM_TYPE_64)) {
108	pci_write_config_dword(r->dev,
109	! PCI_BASE_ADDRESS_1+(r->reg<<2),
110	0);
111	}
112	}
113	***************
114	* 809,820 **
115	if ((l&PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
116	r->type = l&~PCI_BASE_ADDRESS_IO_MASK;
117	r->base = l&PCI_BASE_ADDRESS_IO_MASK;
118	! r->size = ~(ml&PCI_BASE_ADDRESS_IO_MASK)+1;
119	} else {
120	r->type = l&~PCI_BASE_ADDRESS_MEM_MASK;
121	r->base = l&PCI_BASE_ADDRESS_MEM_MASK;
122	! r->size = ~(ml&PCI_BASE_ADDRESS_MEM_MASK)+1;
123	}
124	/* Check for the blacklisted entries */
125	insert_resource(r);
126	}
127	--- 814,844 ----
128	if ((l&PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
129	r->type = l&~PCI_BASE_ADDRESS_IO_MASK;
130	r->base = l&PCI_BASE_ADDRESS_IO_MASK;
131	! /* r->size = ~(ml&PCI_BASE_ADDRESS_IO_MASK)+1; */
132	} else {
133	r->type = l&~PCI_BASE_ADDRESS_MEM_MASK;
134	r->base = l&PCI_BASE_ADDRESS_MEM_MASK;
135	! /* r->size = ~(ml&PCI_BASE_ADDRESS_MEM_MASK)+1; */
136	}
137	+
138	+ /* find the first bit set to one after the base
139	+ address type bits to find length of region */
140	+ {
141	+ unsigned int c= 16 , val= 0;
142	+ while( !(val= ml & c) ) c <<= 1;
143	+ r->size = val;
144	+ }
145	+
146	+ #ifdef PCI_DEBUG
147	+ printk(" readbase bus %d, (%04x:%04x), base %08x, size %08x, type %d\n",
148	+ r->dev->bus->number,
149	+ r->dev->vendor,
150	+ r->dev->device,
151	+ r->base,
152	+ r->size,
153	+ r->type );
154	+ #endif
155	+
156	/* Check for the blacklisted entries */
157	insert_resource(r);
158	}
159	***************
160	* 1177,1182 **
161	--- 1201,1209 ----
162	{
163	pdev= childbus->self;
164
165	+ pcibios_write_config_byte(pdev->bus->number, pdev->devfn, PCI_LATENCY_TIMER, 0x80 );
166	+ pcibios_write_config_byte(pdev->bus->number, pdev->devfn, PCI_SEC_LATENCY_TIMER, 0x80 );
167	+
168	{
169	struct _addr_start addrhold;
170	unsigned8 base8, limit8;
171	***************
172	* 1200,1206 **
173
174
175	/*
176	! **use the current values & the saved ones to figure out
177	** the address spaces for the bridge
178	*/
179
180	--- 1227,1233 ----
181
182
183	/*
184	! ** use the current values & the saved ones to figure out
185	** the address spaces for the bridge
186	*/
187
188	***************
189	* 1253,1258 **
190	--- 1280,1286 ----
191
192
193
194	+
195	if( astart.start_prefetch == addrhold.start_prefetch )
196	{
197	limit16 = 0;
198	***************
199	* 1272,1289 **
200	pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_PREF_MEMORY_BASE, base16 );
201	pcibios_write_config_dword(pdev->bus->number, pdev->devfn, PCI_PREF_LIMIT_UPPER32, 0);
202	pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_PREF_MEMORY_LIMIT, limit16 );
203	-
204	#endif
205
206	#ifdef WRITE_BRIDGE_ENABLE
207	! pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_BRIDGE_CONTROL, (unsigned16)( PCI_BRIDGE_CTL_PARITY \|
208	! PCI_BRIDGE_CTL_SERR ));
209	!
210	! pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_COMMAND, (unsigned16)( PCI_COMMAND_IO \|
211	PCI_COMMAND_MEMORY \|
212	! PCI_COMMAND_MASTER \|
213	! PCI_COMMAND_PARITY \|
214	! PCI_COMMAND_SERR ));
215	#endif
216	}
217	}
218	--- 1300,1319 ----
219	pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_PREF_MEMORY_BASE, base16 );
220	pcibios_write_config_dword(pdev->bus->number, pdev->devfn, PCI_PREF_LIMIT_UPPER32, 0);
221	pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_PREF_MEMORY_LIMIT, limit16 );
222	#endif
223
224	#ifdef WRITE_BRIDGE_ENABLE
225	! pcibios_write_config_word(pdev->bus->number,
226	! pdev->devfn,
227	! PCI_BRIDGE_CONTROL,
228	! (unsigned16)( 0 ));
229	!
230	! pcibios_write_config_word(pdev->bus->number,
231	! pdev->devfn,
232	! PCI_COMMAND,
233	! (unsigned16)( PCI_COMMAND_IO \|
234	PCI_COMMAND_MEMORY \|
235	! PCI_COMMAND_MASTER ));
236	#endif
237	}
238	}
239	***************
240	* 1319,1325 **
241
242	while( (r= enum_device_resources( pdev, i++ )) )
243	{
244	! if( r->type & PCI_BASE_ADDRESS_MEM_PREFETCH )
245	{
246	/* prefetchable space */
247
248	--- 1349,1366 ----
249
250	while( (r= enum_device_resources( pdev, i++ )) )
251	{
252	! /*
253	! ** Force all memory spaces to be non-prefetchable because
254	! ** on the pci bus, byte-wise reads against prefetchable
255	! ** memory are applied as 32 bit reads, which is a pain
256	! ** when you're trying to talk to hardware. This is a
257	! ** little sub-optimal because the algorithm doesn't sort
258	! ** the address regions to pack them in, OTOH, perhaps its
259	! ** not so bad because the inefficient packing will help
260	! ** avoid buffer overflow/underflow problems.
261	! */
262	! #if 0
263	! if( (r->type & PCI_BASE_ADDRESS_MEM_PREFETCH) )
264	{
265	/* prefetchable space */
266
267	***************
268	* 1333,1339 **
269	printk("pci: pf %08X, size %08X, alloc %08X\n", r->base, r->size, alloc );
270	#endif
271	}
272	! else if( r->type & PCI_BASE_ADDRESS_SPACE_IO )
273	{
274	/* io space */
275
276	--- 1374,1381 ----
277	printk("pci: pf %08X, size %08X, alloc %08X\n", r->base, r->size, alloc );
278	#endif
279	}
280	! #endif
281	! if( r->type & PCI_BASE_ADDRESS_SPACE_IO )
282	{
283	/* io space */
284
285	***************
286	* 1436,1441 **
287	--- 1478,1487 ----
288	reconfigure_pci();
289
290	print_pci_resources("Allocated PCI resources:\n");
291	+
292	+ #if 0
293	+ print_pci_info();
294	+ #endif
295	}
296
297
298	diff -N -P -r -c -b -X /home/posixfsw/rtems/production/diff-exclude-files c/src/lib/libbsp/powerpc/shared/pci/pci.c /home/posixfsw/rtems/production/rtems-ss-20030703/c/src/lib/libbsp/powerpc/shared/pci/pci.c
299	*** c/src/lib/libbsp/powerpc/shared/pci/pci.c Thu Sep 4 14:45:20 2003
300	--- /home/posixfsw/rtems/production/rtems-ss-20030703/c/src/lib/libbsp/powerpc/shared/pci/pci.c Mon Sep 29 09:48:34 2003
301	***************
302	* 11,19 **
303	*
304	* The license and distribution terms for this file may be
305	* found in found in the file LICENSE in this distribution or at
306	! * http://www.rtems.com/license/LICENSE.
307	*
308	! * $Id: pci.c,v 1.2.4.3 2003/09/04 18:45:20 joel Exp $
309	*
310	* Till Straumann, <strauman@slac.stanford.edu>, 1/2002
311	* - separated bridge detection code out of this file
312	--- 11,19 ----
313	*
314	* The license and distribution terms for this file may be
315	* found in found in the file LICENSE in this distribution or at
316	! * http://www.OARcorp.com/rtems/license.html.
317	*
318	! * pci.c,v 1.3 2003/06/13 17:39:44 joel Exp
319	*
320	* Till Straumann, <strauman@slac.stanford.edu>, 1/2002
321	* - separated bridge detection code out of this file
322	***************
323	* 21,27 **
324
325	#include <libcpu/io.h>
326	#include <bsp/pci.h>
327	- #include <rtems/bspIo.h>
328
329	/* allow for overriding these definitions */
330	#ifndef PCI_CONFIG_ADDR
331	--- 21,26 ----
332	***************
333	* 362,367 **
334	--- 361,387 ----
335
336	/* printk("pci : device %d:%02x devid %04x, intpin %d, intline %d\n", pbus, pslot, devid, int_pin, int_name ); */
337
338	+ #if 0
339	+ {
340	+ unsigned short cmd,stat;
341	+ unsigned char lat, seclat, csize;
342	+
343	+ pci_read_config_word(pbus,pslot,0,PCI_COMMAND, &cmd );
344	+ pci_read_config_word(pbus,pslot,0,PCI_STATUS, &stat );
345	+ pci_read_config_byte(pbus,pslot,0,PCI_LATENCY_TIMER, &lat );
346	+ pci_read_config_byte(pbus,pslot,0,PCI_SEC_LATENCY_TIMER, &seclat );
347	+ pci_read_config_byte(pbus,pslot,0,PCI_CACHE_LINE_SIZE, &csize );
348	+
349	+
350	+ printk("pci : device %d:%02x cmd %04X, stat %04X, latency %d, sec_latency %d, clsize %d\n", pbus, pslot,
351	+ cmd,
352	+ stat,
353	+ lat,
354	+ seclat,
355	+ csize);
356	+ }
357	+ #endif
358	+
359	if( int_pin > 0 )
360	{
361	ismatch = 0;
362	***************
363	* 389,395 **
364	}
365	if( int_name == -1 )
366	{
367	! printk("pci : Unable to resolve device %d:%d w/ swizzled int pin %d to an interrupt_line.\n", pbus, pslot, int_pin );
368	}
369	else
370	{
371	--- 409,415 ----
372	}
373	if( int_name == -1 )
374	{
375	! printk("pci : Unable to resolve device %d:%d w/ swizzled int pin %i to an interrupt_line.\n", pbus, pslot, int_pin );
376	}
377	else
378	{
379	***************
380	* 459,465 **
381	}
382	if( int_name == -1 )
383	{
384	! printk("pci : Unable to resolve device %d:%d w/ swizzled int pin %d to an interrupt_line.\n", pbus, pslot, int_pin );
385	}
386	else
387	{
388	--- 479,485 ----
389	}
390	if( int_name == -1 )
391	{
392	! printk("pci : Unable to resolve device %d:%d w/ swizzled int pin %i to an interrupt_line.\n", pbus, pslot, int_pin );
393	}
394	else
395	{
396	***************
397	* 500,506 **
398	}
399	else
400	{
401	! printk("pci : No bridge from bus %d towards root found\n", tbus );
402	goto donesearch;
403	}
404
405	--- 520,526 ----
406	}
407	else
408	{
409	! printk("pci : No bridge from bus %i towards root found\n", tbus );
410	goto donesearch;
411	}
412

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