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Ticket #601: joel-diffs-pr601

File joel-diffs-pr601, 36.2 KB (added by gregory.menke, on 12/03/06 at 13:31:12)

joel-diffs-pr601

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2diff -N -P -r -c -b -X /home/posixfsw/rtems/production/diff-exclude-files cpukit/score/cpu/mips/ChangeLog /home/posixfsw/rtems/production/rtems-ss-20030703/cpukit/score/cpu/mips/ChangeLog
3*** cpukit/score/cpu/mips/ChangeLog     Fri Apr  9 10:57:16 2004
4--- /home/posixfsw/rtems/production/rtems-ss-20030703/cpukit/score/cpu/mips/ChangeLog   Wed Apr  7 11:16:17 2004
5***************
6*** 1,23 ****
7! 2004-04-09    Joel Sherrill <joel@OARcorp.com>
8!
9!       PR 605/bsps
10!       * cpu.c: Do not use C++ style comments.
11!
12! 2004-04-03    Art Ferrer <arturo.b.ferrer@nasa.gov>
13!
14!       PR 598/bsps
15!       * cpu_asm.S, rtems/score/cpu.h: Add save of floating point
16!       status/control register on context switches. Missing this register
17!       was causing intermittent floating point errors.
18!
19! 2003-09-04    Joel Sherrill <joel@OARcorp.com>
20!
21!       * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h,
22!       rtems/score/types.h: URL for license changed.
23!
24! 2003-08-11    Ralf Corsepius <corsepiu@faw.uni-ulm.de>
25!
26!       * configure.ac: Use rtems-bugs@rtems.com as bug report email address.
27 
28  2003-03-06    Ralf Corsepius <corsepiu@faw.uni-ulm.de>
29 
30--- 1,8 ----
31! 2004-04-07    Greg Menke <gregory.menke@gsfc.nasa.gov>
32!       PR 601
33!       * cpu_asm.S: Added __mips==32 support for R4000 processors running
34!       32 bit code.  Fixed #define problems that caused fpu code to
35!       always be included even when no fpu is present.
36 
37  2003-03-06    Ralf Corsepius <corsepiu@faw.uni-ulm.de>
38 
39diff -N -P -r -c -b -X /home/posixfsw/rtems/production/diff-exclude-files cpukit/score/cpu/mips/cpu.c /home/posixfsw/rtems/production/rtems-ss-20030703/cpukit/score/cpu/mips/cpu.c
40*** cpukit/score/cpu/mips/cpu.c Fri Apr  9 10:57:16 2004
41--- /home/posixfsw/rtems/production/rtems-ss-20030703/cpukit/score/cpu/mips/cpu.c       Wed Apr  7 11:18:53 2004
42***************
43*** 37,45 ****
44   *
45   *  The license and distribution terms for this file may be
46   *  found in the file LICENSE in this distribution or at
47!  *  http://www.rtems.com/license/LICENSE.
48   *
49!  *  $Id: cpu.c,v 1.18.2.2 2004/04/09 14:52:27 joel Exp $
50   */
51 
52  #include <rtems/system.h>
53--- 37,45 ----
54   *
55   *  The license and distribution terms for this file may be
56   *  found in the file LICENSE in this distribution or at
57!  *  http://www.OARcorp.com/rtems/license.html.
58   *
59!  *  cpu.c,v 1.18 2002/03/08 16:24:48 joel Exp
60   */
61 
62  #include <rtems/system.h>
63***************
64*** 99,109 ****
65 
66    mips_get_sr(sr);
67 
68!   /* printf("current sr=%08X, ",sr); */
69 
70! #if __mips == 3
71! /* EXL bit and shift down hardware ints into bits 1 thru 6 */
72!   sr = ((sr & SR_EXL) >> 1) | ((sr & 0xfc00) >> 9);
73 
74  #elif __mips == 1
75  /* IEC bit and shift down hardware ints into bits 1 thru 6 */
76--- 99,109 ----
77 
78    mips_get_sr(sr);
79 
80!   //printf("current sr=%08X, ",sr);
81 
82! #if (__mips == 3) || (__mips == 32)
83! /* IE bit and shift down hardware ints into bits 1 thru 6 */
84!   sr = (sr & SR_IE) | ((sr & 0xfc00) >> 9);
85 
86  #elif __mips == 1
87  /* IEC bit and shift down hardware ints into bits 1 thru 6 */
88***************
89*** 112,118 ****
90  #else
91  #error "CPU ISR level: unknown MIPS level for SR handling"
92  #endif
93!   /* printf("intlevel=%02X\n",sr); */
94    return sr;
95  }
96 
97--- 112,118 ----
98  #else
99  #error "CPU ISR level: unknown MIPS level for SR handling"
100  #endif
101!   //printf("intlevel=%02X\n",sr);
102    return sr;
103  }
104 
105***************
106*** 134,147 ****
107 
108    mips_get_sr(sr);
109 
110! #if __mips == 3
111    mips_set_sr( (sr & ~SR_IE) );                 /* first disable ie bit (recommended) */
112 
113-   srbits = sr & ~(0xfc00 | SR_EXL | SR_IE);
114 
115!   sr = srbits | ((new_level==0)? (0xfc00 | SR_EXL | SR_IE): \
116                 (((new_level<<9) & 0xfc00) | \
117!                 (new_level & 1)?(SR_EXL | SR_IE):0));
118  /*
119    if ( (new_level & SR_EXL) == (sr & SR_EXL) )
120      return;
121--- 134,148 ----
122 
123    mips_get_sr(sr);
124 
125! #if (__mips == 3) || (__mips == 32)
126    mips_set_sr( (sr & ~SR_IE) );                 /* first disable ie bit (recommended) */
127 
128 
129!       srbits = sr & ~(0xfc00 | SR_IE);
130!
131!   sr = srbits | ((new_level==0)? (0xfc00 | SR_IE): \
132                 (((new_level<<9) & 0xfc00) | \
133!                 (new_level & 1)?SR_IE:0));
134  /*
135    if ( (new_level & SR_EXL) == (sr & SR_EXL) )
136      return;
137***************
138*** 268,274 ****
139 
140  void _CPU_Thread_Idle_body( void )
141  {
142! #if __mips == 3
143     for( ; ; )
144       asm volatile("wait"); /* use wait to enter low power mode */
145  #elif __mips == 1
146--- 269,275 ----
147 
148  void _CPU_Thread_Idle_body( void )
149  {
150! #if (__mips == 3) || (__mips == 32)
151     for( ; ; )
152       asm volatile("wait"); /* use wait to enter low power mode */
153  #elif __mips == 1
154diff -N -P -r -c -b -X /home/posixfsw/rtems/production/diff-exclude-files cpukit/score/cpu/mips/cpu_asm.S /home/posixfsw/rtems/production/rtems-ss-20030703/cpukit/score/cpu/mips/cpu_asm.S
155*** cpukit/score/cpu/mips/cpu_asm.S     Wed Apr  7 11:11:36 2004
156--- /home/posixfsw/rtems/production/rtems-ss-20030703/cpukit/score/cpu/mips/cpu_asm.S   Fri Apr  9 16:08:28 2004
157***************
158*** 32,49 ****
159   *          and deferred FP contexts.
160   *    2002: Joel Sherrill <joel@OARcorp.com> enhanced the exception processing
161   *          by increasing the amount of context saved/restored.
162!  *    2004: 24March, Art Ferrer, NASA/GSFC, added save of FP status/control
163!  *          register to fix intermittent FP error encountered on ST5 mission
164!  *          implementation on Mongoose V processor.
165   * 
166   *  COPYRIGHT (c) 1989-2002.
167   *  On-Line Applications Research Corporation (OAR).
168   *
169   *  The license and distribution terms for this file may be
170   *  found in the file LICENSE in this distribution or at
171!  *  http://www.rtems.com/license/LICENSE.
172   *
173!  *  $Id: cpu_asm.S,v 1.28.2.2 2004/04/03 16:29:06 joel Exp $
174   */
175 
176  #include <asm.h>
177--- 32,50 ----
178   *          and deferred FP contexts.
179   *    2002: Joel Sherrill <joel@OARcorp.com> enhanced the exception processing
180   *          by increasing the amount of context saved/restored.
181!  *    2004: April 7, Greg Menke <gregory.menke@gsfc.nasa.gov> Added __mips==32
182!  *          support for R4000 processors running 32 bit code.  Fixed #define
183!  *          problems that caused fpu code to always be included even when no
184!  *          fpu is present.
185   * 
186   *  COPYRIGHT (c) 1989-2002.
187   *  On-Line Applications Research Corporation (OAR).
188   *
189   *  The license and distribution terms for this file may be
190   *  found in the file LICENSE in this distribution or at
191!  *  http://www.OARcorp.com/rtems/license.html.
192   *
193!  *  cpu_asm.S,v 1.28 2002/08/14 22:59:05 joel Exp
194   */
195 
196  #include <asm.h>
197***************
198*** 53,58 ****
199--- 54,76 ----
200  #define ASSEMBLY_ONLY
201  #include <rtems/score/cpu.h>
202 
203+ #if TRUE
204+ #else
205+ #error TRUE is not true
206+ #endif
207+ #if FALSE
208+ #error FALSE is not false
209+ #else
210+ #endif
211+
212+ /*           
213+ #if ( CPU_HARDWARE_FP == TRUE )
214+ #warning CPU_HARDWARE_FP == TRUE
215+ #else
216+ #warning CPU_HARDWARE_FP != TRUE
217+ #endif
218+ */
219+       
220               
221  /* enable debugging shadow writes to misc ram, this is a vestigal
222  * Mongoose-ism debug tool- but may be handy in the future so we
223***************
224*** 70,81 ****
225 
226  #if __mips == 3
227  /* 64 bit register operations */
228! #define NOP   
229  #define ADD   dadd
230- #define STREG sd
231- #define LDREG ld
232  #define MFCO  dmfc0
233  #define MTCO  dmtc0
234  #define ADDU  addu
235  #define ADDIU addiu
236  #define R_SZ  8
237--- 88,104 ----
238 
239  #if __mips == 3
240  /* 64 bit register operations */
241! #define NOP   nop
242! /*
243  #define ADD   dadd
244  #define MFCO  dmfc0
245  #define MTCO  dmtc0
246+ */
247+ #define ADD   add     
248+ #define MFCO  mfc0
249+ #define MTCO  mtc0
250+ #define STREG sd
251+ #define LDREG ld
252  #define ADDU  addu
253  #define ADDIU addiu
254  #define R_SZ  8
255***************
256*** 85,91 ****
257 
258  /* XXX if we don't always want 64 bit register ops, then another ifdef */
259 
260! #elif __mips == 1
261  /* 32 bit register operations*/
262  #define NOP   nop
263  #define ADD   add
264--- 108,114 ----
265 
266  /* XXX if we don't always want 64 bit register ops, then another ifdef */
267 
268! #elif (__mips == 1 ) || (__mips == 32)
269  /* 32 bit register operations*/
270  #define NOP   nop
271  #define ADD   add
272***************
273*** 162,168 ****
274  #define FP29_OFFSET 29
275  #define FP30_OFFSET 30
276  #define FP31_OFFSET 31
277- #define FPCS_OFFSET 32
278 
279       
280  ASM_EXTERN(__exceptionStackFrame, SZ_INT)
281--- 185,190 ----
282***************
283*** 256,267 ****
284          swc1 $f29,FP29_OFFSET*F_SZ(a1)
285          swc1 $f30,FP30_OFFSET*F_SZ(a1)
286          swc1 $f31,FP31_OFFSET*F_SZ(a1)
287-         cfc1 a0,$31                    /* Read FP status/conrol reg */
288-         cfc1 a0,$31                    /* Two reads clear pipeline */
289-         NOP
290-         NOP
291-         sw a0, FPCS_OFFSET*F_SZ(a1)    /* Store value to FPCS location */
292-         NOP
293          j ra
294          NOP
295          .set at
296--- 278,283 ----
297***************
298*** 356,369 ****
299          lwc1 $f29,FP29_OFFSET*4(a1)
300          lwc1 $f30,FP30_OFFSET*4(a1)
301          lwc1 $f31,FP31_OFFSET*4(a1)
302-         cfc1 a0,$31                  /* Read from FP status/control reg */
303-         cfc1 a0,$31                  /* Two reads clear pipeline */
304-         NOP                          /* NOPs ensure execution */
305-         NOP
306-         lw a0,FPCS_OFFSET*4(a1)      /* Load saved FPCS value */
307-         NOP
308-         ctc1 a0,$31                  /* Restore FPCS register */
309-         NOP
310          j ra
311          NOP
312          .set at
313--- 372,377 ----
314***************
315*** 385,392 ****
316          .set noreorder
317 
318          MFC0  t0,C0_SR
319! #if __mips == 3
320!       li      t1,SR_EXL | SR_IE
321  #elif __mips == 1
322        li      t1,SR_IEC
323  #endif
324--- 393,400 ----
325          .set noreorder
326 
327          MFC0  t0,C0_SR
328! #if (__mips == 3) || (__mips == 32)
329!       li      t1,SR_IE
330  #elif __mips == 1
331        li      t1,SR_IEC
332  #endif
333***************
334*** 485,491 ****
335  ** Although something of a hack on this processor, we treat the SR register
336  ** int enables as the RTEMS interrupt level.  We use the int level
337  ** value as a bitmask, not as any sort of greater than/less than metric.
338! ** Manipulation of a task's interrupt level directly corresponds to manipulation
339  ** of that task's SR bits, as seen in cpu.c
340  **
341  ** Note, interrupts are disabled before context is saved, though the task's
342--- 493,499 ----
343  ** Although something of a hack on this processor, we treat the SR register
344  ** int enables as the RTEMS interrupt level.  We use the int level
345  ** value as a bitmask, not as any sort of greater than/less than metric.
346! ** Manipulation of a task's interrupt level corresponds directly to manipulation
347  ** of that task's SR bits, as seen in cpu.c
348  **
349  ** Note, interrupts are disabled before context is saved, though the task's
350***************
351*** 499,513 ****
352        or      t2,SR_IMASK
353 
354        /* int enable bits */
355! #if __mips == 3
356!       or      t2,SR_EXL + SR_IE
357  #elif __mips == 1
358        /*
359        ** Save current, previous & old int enables.  This is key because
360        ** we can dispatch from within the stack frame used by an
361        ** interrupt service.  The int enables nest, but not beyond
362        ** previous and old because of the dispatch interlock seen
363!       ** in the interrupt processing code
364        */
365        or      t2,SR_IEC + SR_IEP + SR_IEO
366  #endif
367--- 507,524 ----
368        or      t2,SR_IMASK
369 
370        /* int enable bits */
371! #if (__mips == 3) || (__mips == 32)
372!       /*
373!       ** Save IE
374!       */
375!       or      t2, SR_IE
376  #elif __mips == 1
377        /*
378        ** Save current, previous & old int enables.  This is key because
379        ** we can dispatch from within the stack frame used by an
380        ** interrupt service.  The int enables nest, but not beyond
381        ** previous and old because of the dispatch interlock seen
382!       ** in the interrupt processing code.
383        */
384        or      t2,SR_IEC + SR_IEP + SR_IEO
385  #endif
386***************
387*** 515,521 ****
388               
389        MFC0    t1,C0_SR        /* grab the current SR */
390        not     t2             
391!       and     t1,t2           /* mask off the old task's bits */
392        or      t1,t0           /* or in the new task's bits */
393          MTC0  t1,C0_SR        /* and load the new SR */
394        NOP
395--- 526,532 ----
396               
397        MFC0    t1,C0_SR        /* grab the current SR */
398        not     t2
399!       and     t1,t2           /* mask off the old task's per-task bits */
400        or      t1,t0           /* or in the new task's bits */
401          MTC0  t1,C0_SR        /* and load the new SR */
402        NOP
403***************
404*** 707,713 ****
405          STREG    t1,R_BADVADDR*R_SZ(sp)
406       
407  #if ( CPU_HARDWARE_FP == TRUE )
408!         MFC0     t0,C0_SR                 /* FPU is enabled, save state */
409        NOP
410          srl      t0,t0,16
411          andi     t0,t0,(SR_CU1 >> 16)
412--- 718,724 ----
413          STREG    t1,R_BADVADDR*R_SZ(sp)
414       
415  #if ( CPU_HARDWARE_FP == TRUE )
416!         MFC0     t0,C0_SR                 /* we have an FPU, save state if its enabled */
417        NOP
418          srl      t0,t0,16
419          andi     t0,t0,(SR_CU1 >> 16)
420***************
421*** 731,737 ****
422 
423       
424        /*
425!       ** note, if the exception vector returns, rely on it to have
426        ** adjusted EPC so we will return to some correct address.  If
427        ** this is not done, we might get stuck in an infinite loop because
428        ** we'll return to the instruction where the exception occured and
429--- 742,748 ----
430 
431       
432        /*
433!       ** Note, if the exception vector returns, rely on it to have
434        ** adjusted EPC so we will return to some correct address.  If
435        ** this is not done, we might get stuck in an infinite loop because
436        ** we'll return to the instruction where the exception occured and
437***************
438*** 799,805 ****
439       
440               
441  #if ( CPU_HARDWARE_FP == TRUE )
442!         MFC0     t0,C0_SR               /* FPU is enabled, restore state */
443        NOP
444          srl      t0,t0,16
445          andi     t0,t0,(SR_CU1 >> 16)
446--- 810,816 ----
447       
448               
449  #if ( CPU_HARDWARE_FP == TRUE )
450!         MFC0     t0,C0_SR               /* FPU is present, restore state if enabled */
451        NOP
452          srl      t0,t0,16
453          andi     t0,t0,(SR_CU1 >> 16)
454***************
455*** 955,966 ****
456  */
457 
458          MFC0    t0, C0_SR
459! #if __mips == 3
460!       li      t1,SR_EXL | SR_IE
461! #elif __mips == 1
462        li      t1,SR_IEC
463- #endif
464        or      t0, t1
465          MTC0    t0, C0_SR
466        NOP
467 
468--- 966,987 ----
469  */
470 
471          MFC0    t0, C0_SR
472! #if __mips == 1
473!       
474        li      t1,SR_IEC
475        or      t0, t1
476+       
477+ #elif (__mips == 3) || (__mips == 32)
478+       
479+       /*
480+       ** clear XL and set IE so we can get interrupts.
481+       */
482+       li      t1, SR_EXL
483+       not     t1
484+       and     t0,t1
485+       or      t0, SR_IE
486+       
487+ #endif
488          MTC0    t0, C0_SR
489        NOP
490 
491***************
492*** 971,1010 ****
493          jal     _Thread_Dispatch
494          NOP
495 
496!       /* and make sure its clear in case we didn't dispatch.  if we did, its
497!       ** already cleared */
498        la      t0,__exceptionStackFrame
499        STREG   zero,(t0)
500        NOP
501 
502  /*
503  ** turn interrupts back off while we restore context so
504! ** a badly timed interrupt won't accidentally mess things up
505  */
506          MFC0    t0, C0_SR
507! #if __mips == 3
508!       li      t1,SR_EXL | SR_IE
509! #elif __mips == 1
510        /* ints off, current & prev kernel mode on (kernel mode enabled is bit clear..argh!) */
511        li      t1,SR_IEC | SR_KUP | SR_KUC     
512- #endif
513        not     t1
514        and     t0, t1
515 
516! #if __mips == 1
517!       /* disabled 7/29, gregm, this tasks context was saved previously in an interrupt,
518!       ** so we'll just restore the task's previous interrupt enables.
519 
520!       **
521!       ** make sure previous int enable is on  because we're returning from an interrupt
522!       ** which means interrupts have to be enabled
523       
524!       li      t1,SR_IEP
525!       or      t0,t1
526!       */
527! #endif
528!         MTC0    t0, C0_SR
529        NOP
530       
531  #ifdef INSTRUMENT_EXECUTING_THREAD
532        lw      t0,_Thread_Executing
533--- 992,1046 ----
534          jal     _Thread_Dispatch
535          NOP
536 
537!       /*
538!       ** And make sure its clear in case we didn't dispatch.  if we did, its
539!       ** already cleared
540!       */
541        la      t0,__exceptionStackFrame
542        STREG   zero,(t0)
543        NOP
544 
545  /*
546  ** turn interrupts back off while we restore context so
547! ** a badly timed interrupt won't mess things up
548  */
549          MFC0    t0, C0_SR
550!
551! #if __mips == 1
552!
553        /* ints off, current & prev kernel mode on (kernel mode enabled is bit clear..argh!) */
554        li      t1,SR_IEC | SR_KUP | SR_KUC     
555        not     t1
556        and     t0, t1
557+         MTC0    t0, C0_SR
558+       NOP
559               
560! #elif (__mips == 3) || (__mips == 32)
561 
562!       move    t2, t0
563       
564!       /* make sure XL & IE are clear so ints are disabled & we can update EPC for the return */
565!       li      t1,SR_EXL | SR_IE
566!       not     t1
567!       and     t0,t1
568!       MTC0    t0,C0_SR
569!       NOP
570!       
571!       /* store new EPC value, which we can do since XL=0 */
572!         LDREG   t0, R_EPC*R_SZ(sp)
573!       NOP
574!       MTC0    t0, C0_EPC
575!       NOP
576!       
577!       /* apply task's SR with XL set so the eret will return properly */
578!       or      t2, SR_EXL
579!       MTC0    t2, C0_SR
580        NOP
581+ #endif
582+
583+
584+
585+
586       
587  #ifdef INSTRUMENT_EXECUTING_THREAD
588        lw      t0,_Thread_Executing
589***************
590*** 1061,1075 ****
591--- 1097,1118 ----
592          LDREG v1, R_V1*R_SZ(sp)
593          LDREG v0, R_V0*R_SZ(sp)
594 
595+ #if __mips == 1               
596          LDREG     k1, R_EPC*R_SZ(sp)
597+ #endif
598       
599        .set noat
600          LDREG     AT, R_AT*R_SZ(sp)
601          .set at
602 
603        ADDIU     sp,sp,EXCP_STACK_SIZE
604+
605+ #if (__mips == 3) || (__mips == 32)
606+       eret
607+ #elif __mips == 1
608        j         k1
609        rfe
610+ #endif
611          NOP
612 
613         .set    reorder
614diff -N -P -r -c -b -X /home/posixfsw/rtems/production/diff-exclude-files cpukit/score/cpu/mips/idtcpu.h /home/posixfsw/rtems/production/rtems-ss-20030703/cpukit/score/cpu/mips/idtcpu.h
615*** cpukit/score/cpu/mips/idtcpu.h      Mon Nov  4 17:19:49 2002
616--- /home/posixfsw/rtems/production/rtems-ss-20030703/cpukit/score/cpu/mips/idtcpu.h    Wed Nov 26 15:23:08 2003
617***************
618*** 20,26 ****
619  COPYRIGHT IDT CORPORATION 1996
620  LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
621 
622!   $Id: idtcpu.h,v 1.13 2002/11/04 22:19:49 joel Exp $
623  */
624 
625  /*
626--- 20,26 ----
627  COPYRIGHT IDT CORPORATION 1996
628  LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
629 
630!   idtcpu.h,v 1.13 2002/11/04 22:19:49 joel Exp
631  */
632 
633  /*
634***************
635*** 60,65 ****
636--- 60,70 ----
637  #define       UT_VEC  K0BASE                  /* utlbmiss vector */
638  #define DB_VEC  (K0BASE+0x40)           /* debug vector */
639  #define E_VEC (K0BASE+0x80)           /* exception vector */
640+ #elif  __mips == 32
641+ #define       T_VEC   (K0BASE+0x000)          /* tlbmiss vector */
642+ #define X_VEC (K0BASE+0x080)          /* xtlbmiss vector */
643+ #define C_VEC (K0BASE+0x100)          /* cache error vector */
644+ #define E_VEC (K0BASE+0x180)          /* exception vector */
645  #elif    __mips == 3
646  #define       T_VEC   (K0BASE+0x000)          /* tlbmiss vector */
647  #define X_VEC (K0BASE+0x080)          /* xtlbmiss vector */
648***************
649*** 91,96 ****
650--- 96,195 ----
651  #define       MINCACHE        0x200           /* 512       For 3041. */
652  #define       MAXCACHE        0x40000         /* 256*1024   256k */   
653 
654+ #if  __mips == 32
655+ /* R4000 configuration register definitions */
656+ #define CFG_CM                0x80000000      /* Master-Checker mode */
657+ #define CFG_ECMASK    0x70000000      /* System Clock Ratio */
658+ #define CFG_ECBY2     0x00000000      /* divide by 2 */
659+ #define CFG_ECBY3     0x10000000      /* divide by 3 */
660+ #define CFG_ECBY4     0x20000000      /* divide by 4 */
661+ #define CFG_EPMASK    0x0f000000      /* Transmit data pattern */
662+ #define CFG_EPD               0x00000000      /* D */
663+ #define CFG_EPDDX     0x01000000      /* DDX */
664+ #define CFG_EPDDXX    0x02000000      /* DDXX */
665+ #define CFG_EPDXDX    0x03000000      /* DXDX */
666+ #define CFG_EPDDXXX   0x04000000      /* DDXXX */
667+ #define CFG_EPDDXXXX  0x05000000      /* DDXXXX */
668+ #define CFG_EPDXXDXX  0x06000000      /* DXXDXX */
669+ #define CFG_EPDDXXXXX 0x07000000      /* DDXXXXX */
670+ #define CFG_EPDXXXDXXX        0x08000000      /* DXXXDXXX */
671+ #define CFG_SBMASK    0x00c00000      /* Secondary cache block size */
672+ #define CFG_SBSHIFT   22
673+ #define CFG_SB4               0x00000000      /* 4 words */
674+ #define CFG_SB8               0x00400000      /* 8 words */
675+ #define CFG_SB16      0x00800000      /* 16 words */
676+ #define CFG_SB32      0x00c00000      /* 32 words */
677+ #define CFG_SS                0x00200000      /* Split secondary cache */
678+ #define CFG_SW                0x00100000      /* Secondary cache port width */
679+ #define CFG_EWMASK    0x000c0000      /* System port width */
680+ #define CFG_EWSHIFT   18
681+ #define CFG_EW64      0x00000000      /* 64 bit */
682+ #define CFG_EW32      0x00010000      /* 32 bit */
683+ #define CFG_SC                0x00020000      /* Secondary cache absent */
684+ #define CFG_SM                0x00010000      /* Dirty Shared mode disabled */
685+ #define CFG_BE                0x00008000      /* Big Endian */
686+ #define CFG_EM                0x00004000      /* ECC mode enable */
687+ #define CFG_EB                0x00002000      /* Block ordering */
688+ #define CFG_ICMASK    0x00000e00      /* Instruction cache size */
689+ #define CFG_ICSHIFT   9
690+ #define CFG_DCMASK    0x000001c0      /* Data cache size */
691+ #define CFG_DCSHIFT   6
692+ #define CFG_IB                0x00000020      /* Instruction cache block size */
693+ #define CFG_DB                0x00000010      /* Data cache block size */
694+ #define CFG_CU                0x00000008      /* Update on Store Conditional */
695+ #define CFG_K0MASK    0x00000007      /* KSEG0 coherency algorithm */
696+
697+ /*
698+  * R4000 primary cache mode
699+  */
700+ #define CFG_C_UNCACHED                2
701+ #define CFG_C_NONCOHERENT     3
702+ #define CFG_C_COHERENTXCL     4
703+ #define CFG_C_COHERENTXCLW    5
704+ #define CFG_C_COHERENTUPD     6
705+
706+ /*
707+  * R4000 cache operations (should be in assembler...?)
708+  */
709+ #define Index_Invalidate_I               0x0         /* 0       0 */
710+ #define Index_Writeback_Inv_D            0x1         /* 0       1 */
711+ #define Index_Invalidate_SI              0x2         /* 0       2 */
712+ #define Index_Writeback_Inv_SD           0x3         /* 0       3 */
713+ #define Index_Load_Tag_I                 0x4         /* 1       0 */
714+ #define Index_Load_Tag_D                 0x5         /* 1       1 */
715+ #define Index_Load_Tag_SI                0x6         /* 1       2 */
716+ #define Index_Load_Tag_SD                0x7         /* 1       3 */
717+ #define Index_Store_Tag_I                0x8         /* 2       0 */
718+ #define Index_Store_Tag_D                0x9         /* 2       1 */
719+ #define Index_Store_Tag_SI               0xA         /* 2       2 */
720+ #define Index_Store_Tag_SD               0xB         /* 2       3 */
721+ #define Create_Dirty_Exc_D               0xD         /* 3       1 */
722+ #define Create_Dirty_Exc_SD              0xF         /* 3       3 */
723+ #define Hit_Invalidate_I                 0x10        /* 4       0 */
724+ #define Hit_Invalidate_D                 0x11        /* 4       1 */
725+ #define Hit_Invalidate_SI                0x12        /* 4       2 */
726+ #define Hit_Invalidate_SD                0x13        /* 4       3 */
727+ #define Hit_Writeback_Inv_D              0x15        /* 5       1 */
728+ #define Hit_Writeback_Inv_SD             0x17        /* 5       3 */
729+ #define Fill_I                           0x14        /* 5       0 */
730+ #define Hit_Writeback_D                  0x19        /* 6       1 */
731+ #define Hit_Writeback_SD                 0x1B        /* 6       3 */
732+ #define Hit_Writeback_I                  0x18        /* 6       0 */
733+ #define Hit_Set_Virtual_SI               0x1E        /* 7       2 */
734+ #define Hit_Set_Virtual_SD               0x1F        /* 7       3 */
735+
736+ #ifndef WAIT
737+ #define WAIT .word 0x42000020
738+ #endif /* WAIT */
739+
740+ /* Disabled by joel -- horrible overload of common word.
741+ #ifndef wait
742+ #define wait .word 0x42000020
743+ #endif wait
744+ */
745+
746+ #endif
747+
748  #if  __mips == 3
749  /* R4000 configuration register definitions */
750  #define CFG_CM                0x80000000      /* Master-Checker mode */
751***************
752*** 253,258 ****
753--- 352,392 ----
754  #define TLBPGMASK_MASK                0x01ffe000
755  #endif
756 
757+ #if  __mips == 32
758+ #define       N_TLB_ENTRIES   16
759+
760+ #define       TLBHI_VPN2MASK  0xffffe000
761+ #define       TLBHI_PIDMASK   0x000000ff
762+ #define       TLBHI_NPID      256
763+
764+ #define       TLBLO_PFNMASK   0x3fffffc0
765+ #define TLBLO_PFNSHIFT        6
766+ #define       TLBLO_D         0x00000004      /* writeable */
767+ #define       TLBLO_V         0x00000002      /* valid bit */
768+ #define       TLBLO_G         0x00000001      /* global access bit */
769+ #define TLBLO_CMASK   0x00000038      /* cache algorithm mask */
770+ #define TLBLO_CSHIFT  3
771+
772+ #define TLBLO_UNCACHED                (CFG_C_UNCACHED<<TLBLO_CSHIFT)
773+ #define TLBLO_NONCOHERENT     (CFG_C_NONCOHERENT<<TLBLO_CSHIFT)
774+ #define TLBLO_COHERENTXCL     (CFG_C_COHERENTXCL<<TLBLO_CSHIFT)
775+ #define TLBLO_COHERENTXCLW    (CFG_C_COHERENTXCLW<<TLBLO_CSHIFT)
776+ #define TLBLO_COHERENTUPD     (CFG_C_COHERENTUPD<<TLBLO_CSHIFT)
777+
778+ #define       TLBINX_PROBE    0x80000000
779+ #define       TLBINX_INXMASK  0x0000003f
780+
781+ #define       TLBRAND_RANDMASK        0x0000003f
782+
783+ #define       TLBCTXT_BASEMASK        0xff800000
784+ #define       TLBCTXT_BASESHIFT       23
785+
786+ #define       TLBCTXT_VPN2MASK        0x007ffff0
787+ #define       TLBCTXT_VPN2SHIFT       4
788+
789+ #define TLBPGMASK_MASK                0x01ffe000
790+ #endif
791+
792  #if  __mips == 1
793 
794 
795***************
796*** 383,389 ****
797--- 517,574 ----
798  #define SR_IE         0x00000001      /* Interrupts enabled */
799  #endif
800 
801+ #if  __mips == 32
802+ #define       SR_CUMASK       0xf0000000      /* coproc usable bits */
803+ #define       SR_CU3          0x80000000      /* Coprocessor 3 usable */
804+ #define       SR_CU2          0x40000000      /* Coprocessor 2 usable */
805+ #define       SR_CU1          0x20000000      /* Coprocessor 1 usable */
806+ #define       SR_CU0          0x10000000      /* Coprocessor 0 usable */
807 
808+ #define SR_RP         0x08000000      /* Reduced power operation */
809+ #define SR_FR         0x04000000      /* Additional floating point registers */
810+ #define SR_RE         0x02000000      /* Reverse endian in user mode */
811+
812+ #define SR_BEV                0x00400000      /* Use boot exception vectors */
813+ #define SR_TS         0x00200000      /* TLB shutdown */
814+ #define SR_SR         0x00100000      /* Soft reset */
815+ #define SR_CH         0x00040000      /* Cache hit */
816+ #define SR_CE         0x00020000      /* Use cache ECC  */
817+ #define SR_DE         0x00010000      /* Disable cache exceptions */
818+
819+ /*
820+ **    status register interrupt masks and bits
821+ */
822+
823+ #define       SR_IMASK        0x0000ff00      /* Interrupt mask */
824+ #define       SR_IMASK8       0x00000000      /* mask level 8 */
825+ #define       SR_IMASK7       0x00008000      /* mask level 7 */
826+ #define       SR_IMASK6       0x0000c000      /* mask level 6 */
827+ #define       SR_IMASK5       0x0000e000      /* mask level 5 */
828+ #define       SR_IMASK4       0x0000f000      /* mask level 4 */
829+ #define       SR_IMASK3       0x0000f800      /* mask level 3 */
830+ #define       SR_IMASK2       0x0000fc00      /* mask level 2 */
831+ #define       SR_IMASK1       0x0000fe00      /* mask level 1 */
832+ #define       SR_IMASK0       0x0000ff00      /* mask level 0 */
833+
834+ #define       SR_IMASKSHIFT   8
835+
836+ #define       SR_IBIT8        0x00008000      /* bit level 8 */
837+ #define       SR_IBIT7        0x00004000      /* bit level 7 */
838+ #define       SR_IBIT6        0x00002000      /* bit level 6 */
839+ #define       SR_IBIT5        0x00001000      /* bit level 5 */
840+ #define       SR_IBIT4        0x00000800      /* bit level 4 */
841+ #define       SR_IBIT3        0x00000400      /* bit level 3 */
842+ #define       SR_IBIT2        0x00000200      /* bit level 2 */
843+ #define       SR_IBIT1        0x00000100      /* bit level 1 */
844+
845+ #define SR_KSMASK     0x00000018      /* Kernel mode mask */
846+ #define SR_KSUSER     0x00000010      /* User mode */
847+ #define SR_KSSUPER    0x00000008      /* Supervisor mode */
848+ #define SR_KSKERNEL   0x00000000      /* Kernel mode */
849+ #define SR_ERL                0x00000004      /* Error level */
850+ #define SR_EXL                0x00000002      /* Exception level */
851+ #define SR_IE         0x00000001      /* Interrupts enabled */
852+ #endif
853 
854  /*
855   * Cause Register
856***************
857*** 414,419 ****
858--- 599,610 ----
859  #define       C0_TLBLO1       $3              /* tlb entry low 1 */
860  #endif
861 
862+ #if  __mips == 32
863+ #define       C0_TLBLO0       $2              /* tlb entry low 0 */
864+ #define       C0_TLBLO1       $3              /* tlb entry low 1 */
865+ #endif
866+
867+
868  #define       C0_CTXT         $4              /* tlb context */
869 
870  #if  __mips == 3
871***************
872*** 421,426 ****
873--- 612,622 ----
874  #define C0_WIRED      $6              /* number of wired tlb entries */
875  #endif
876 
877+ #if  __mips == 32
878+ #define C0_PAGEMASK   $5              /* tlb page mask */
879+ #define C0_WIRED      $6              /* number of wired tlb entries */
880+ #endif
881+
882  #if  __mips == 1
883  #define C0_TAR          $6
884  #endif
885***************
886*** 430,435 ****
887--- 626,634 ----
888  #if  __mips == 3
889  #define C0_COUNT      $9              /* cycle count */
890  #endif
891+ #if  __mips == 32
892+ #define C0_COUNT      $9              /* cycle count */
893+ #endif
894 
895  #define       C0_TLBHI        $10             /* tlb entry hi */
896 
897***************
898*** 437,442 ****
899--- 636,645 ----
900  #define C0_COMPARE    $11             /* cyccle count comparator  */
901  #endif
902 
903+ #if  __mips == 32
904+ #define C0_COMPARE    $11             /* cyccle count comparator  */
905+ #endif
906+
907  #define       C0_SR           $12             /* status register */
908  #define       C0_CAUSE        $13             /* exception cause */
909  #define       C0_EPC          $14             /* exception pc */
910***************
911*** 459,464 ****
912--- 662,681 ----
913  #define C0_ERRPC      $30             /* cache error pc */
914  #endif
915 
916+ #if  __mips == 32
917+ #define C0_CONFIG     $16             /* configuration register */
918+ #define C0_LLADDR     $17             /* linked load address */
919+ #define C0_WATCHLO    $18             /* watchpoint trap register */
920+ #define C0_WATCHHI    $19             /* watchpoint trap register */
921+ #define C0_XCTXT    $20     /* extended tlb context */
922+ #define C0_ECC                $26             /* secondary cache ECC control */
923+ #define C0_CACHEERR   $27             /* cache error status */
924+ #define C0_TAGLO      $28             /* cache tag lo */
925+ #define C0_TAGHI      $29             /* cache tag hi */
926+ #define C0_ERRPC      $30             /* cache error pc */
927+ #endif
928+
929+
930  #define C1_REVISION     $0
931  #define C1_STATUS       $31
932 
933diff -N -P -r -c -b -X /home/posixfsw/rtems/production/diff-exclude-files cpukit/score/cpu/mips/iregdef.h /home/posixfsw/rtems/production/rtems-ss-20030703/cpukit/score/cpu/mips/iregdef.h
934*** cpukit/score/cpu/mips/iregdef.h     Fri Mar  1 11:21:12 2002
935--- /home/posixfsw/rtems/production/rtems-ss-20030703/cpukit/score/cpu/mips/iregdef.h   Wed Nov 26 15:25:04 2003
936***************
937*** 20,26 ****
938  COPYRIGHT IDT CORPORATION 1996
939  LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
940 
941!   $Id: iregdef.h,v 1.9 2002/03/01 16:21:12 joel Exp $
942  */
943 
944  /*
945--- 20,26 ----
946  COPYRIGHT IDT CORPORATION 1996
947  LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
948 
949!   iregdef.h,v 1.9 2002/03/01 16:21:12 joel Exp
950  */
951 
952  /*
953***************
954*** 229,235 ****
955  #if __mips == 1
956  #define       R_TLBLO         73
957  #endif
958! #if  __mips == 3
959  #define       R_TLBLO0        73
960  #endif
961 
962--- 229,235 ----
963  #if __mips == 1
964  #define       R_TLBLO         73
965  #endif
966! #if  (__mips == 3 ) || ( __mips == 32)
967  #define       R_TLBLO0        73
968  #endif
969 
970***************
971*** 243,249 ****
972  #if __mips == 1
973  #define NREGS         81
974  #endif
975! #if  __mips == 3
976  #define       R_TLBLO1        81
977  #define R_PAGEMASK    82
978  #define R_WIRED               83
979--- 243,249 ----
980  #if __mips == 1
981  #define NREGS         81
982  #endif
983! #if  (__mips == 3 ) || ( __mips == 32)
984  #define       R_TLBLO1        81
985  #define R_PAGEMASK    82
986  #define R_WIRED               83
987***************
988*** 298,304 ****
989  #define       R_SP            R_R29
990  #define       R_FP            R_R30
991  #define       R_RA            R_R31
992!
993  /* disabled for RTEMS */
994  #if 0
995  /* Ketan added the following */
996--- 298,304 ----
997  #define       R_SP            R_R29
998  #define       R_FP            R_R30
999  #define       R_RA            R_R31
1000! #define R_SZ 4
1001  /* disabled for RTEMS */
1002  #if 0
1003  /* Ketan added the following */
1004diff -N -P -r -c -b -X /home/posixfsw/rtems/production/diff-exclude-files cpukit/score/cpu/mips/rtems/score/cpu.h /home/posixfsw/rtems/production/rtems-ss-20030703/cpukit/score/cpu/mips/rtems/score/cpu.h
1005*** cpukit/score/cpu/mips/rtems/score/cpu.h     Sat Apr  3 11:29:06 2004
1006--- /home/posixfsw/rtems/production/rtems-ss-20030703/cpukit/score/cpu/mips/rtems/score/cpu.h   Wed Dec  3 12:07:00 2003
1007***************
1008*** 31,39 ****
1009   *
1010   *  The license and distribution terms for this file may be
1011   *  found in the file LICENSE in this distribution or at
1012!  *  http://www.rtems.com/license/LICENSE.
1013   *
1014!  *  $Id: cpu.h,v 1.27.2.2 2004/04/03 16:29:06 joel Exp $
1015   */
1016 
1017  #ifndef __CPU_h
1018--- 31,39 ----
1019   *
1020   *  The license and distribution terms for this file may be
1021   *  found in the file LICENSE in this distribution or at
1022!  *  http://www.OARcorp.com/rtems/license.html.
1023   *
1024!  *  cpu.h,v 1.27 2002/04/03 14:05:09 joel Exp
1025   */
1026 
1027  #ifndef __CPU_h
1028***************
1029*** 48,53 ****
1030--- 48,63 ----
1031  #include <rtems/score/types.h>
1032  #endif
1033 
1034+ #ifndef TRUE
1035+ #define TRUE 1
1036+ #warning "TRUE was not defined, assuming default of 1"
1037+ #endif
1038+ #ifndef FALSE
1039+ #define FALSE 0
1040+ #warning "FALSE was not defined, assuming default of 0"
1041+ #endif
1042+
1043+
1044  /* conditional compilation parameters */
1045 
1046  /*
1047***************
1048*** 363,369 ****
1049  #ifndef ASSEMBLY_ONLY
1050 
1051  /* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
1052! #if __mips == 1
1053  #define __MIPS_REGISTER_TYPE     unsigned32
1054  #define __MIPS_FPU_REGISTER_TYPE unsigned32
1055  #elif __mips == 3
1056--- 373,379 ----
1057  #ifndef ASSEMBLY_ONLY
1058 
1059  /* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
1060! #if (__mips == 1) || (__mips == 32)
1061  #define __MIPS_REGISTER_TYPE     unsigned32
1062  #define __MIPS_FPU_REGISTER_TYPE unsigned32
1063  #elif __mips == 3
1064***************
1065*** 426,432 ****
1066      __MIPS_FPU_REGISTER_TYPE fp29;
1067      __MIPS_FPU_REGISTER_TYPE fp30;
1068      __MIPS_FPU_REGISTER_TYPE fp31;
1069-     __MIPS_FPU_REGISTER_TYPE fpcs;
1070  #endif
1071  } Context_Control_fp;
1072 
1073--- 436,441 ----
1074***************
1075*** 540,546 ****
1076    __MIPS_REGISTER_TYPE  tlblo;    /* 73 - NOT FILLED IN, doesn't exist on */
1077                                    /*         all MIPS CPUs (at least MGV) */
1078  #endif
1079! #if  __mips == 3
1080    __MIPS_REGISTER_TYPE  tlblo0;   /* 73 - NOT FILLED IN, doesn't exist on */
1081                                    /*         all MIPS CPUs (at least MGV) */
1082  #endif
1083--- 549,555 ----
1084    __MIPS_REGISTER_TYPE  tlblo;    /* 73 - NOT FILLED IN, doesn't exist on */
1085                                    /*         all MIPS CPUs (at least MGV) */
1086  #endif
1087! #if  (__mips == 3) || (__mips == 32)
1088    __MIPS_REGISTER_TYPE  tlblo0;   /* 73 - NOT FILLED IN, doesn't exist on */
1089                                    /*         all MIPS CPUs (at least MGV) */
1090  #endif
1091***************
1092*** 556,562 ****
1093    __MIPS_REGISTER_TYPE  prid;     /* 79 -- NOT FILLED IN (not need to do so) */
1094    __MIPS_REGISTER_TYPE  tar ;     /* 80 -- target address register, filled on exceptions */
1095    /* end of __mips == 1 so NREGS == 81 */
1096! #if  __mips == 3
1097    __MIPS_REGISTER_TYPE  tlblo1;   /* 81 -- NOT FILLED IN */
1098    __MIPS_REGISTER_TYPE  pagemask; /* 82 -- NOT FILLED IN */
1099    __MIPS_REGISTER_TYPE  wired;    /* 83 -- NOT FILLED IN */
1100--- 565,571 ----
1101    __MIPS_REGISTER_TYPE  prid;     /* 79 -- NOT FILLED IN (not need to do so) */
1102    __MIPS_REGISTER_TYPE  tar ;     /* 80 -- target address register, filled on exceptions */
1103    /* end of __mips == 1 so NREGS == 81 */
1104! #if  (__mips == 3) || (__mips == 32)
1105    __MIPS_REGISTER_TYPE  tlblo1;   /* 81 -- NOT FILLED IN */
1106    __MIPS_REGISTER_TYPE  pagemask; /* 82 -- NOT FILLED IN */
1107    __MIPS_REGISTER_TYPE  wired;    /* 83 -- NOT FILLED IN */
1108***************
1109*** 854,861 ****
1110   */
1111 
1112 
1113! #if __mips == 3
1114! #define _INTON        (SR_EXL | SR_IE)
1115  #define _EXTRABITS      0
1116  #endif
1117  #if __mips == 1
1118--- 863,870 ----
1119   */
1120 
1121 
1122! #if (__mips == 3) || (__mips == 32)
1123! #define _INTON                SR_IE
1124  #define _EXTRABITS      0
1125  #endif
1126  #if __mips == 1
1127***************
1128*** 871,879 ****
1129        _stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \
1130        (_the_context)->sp = _stack_tmp; \
1131        (_the_context)->fp = _stack_tmp; \
1132!       (_the_context)->ra = (unsigned64)_entry_point; \
1133!       (_the_context)->c0_sr = ((_intlvl==0)?(0xFF00 | _INTON):( ((_intlvl<<9) & 0xfc00) | \
1134!                                                      0x300 | \
1135                                                       ((_intlvl & 1)?_INTON:0)) ) | \
1136                                SR_CU0 | ((_is_fp)?SR_CU1:0) | _EXTRABITS; \
1137    }
1138--- 880,888 ----
1139        _stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \
1140        (_the_context)->sp = _stack_tmp; \
1141        (_the_context)->fp = _stack_tmp; \
1142!       (_the_context)->ra = (__MIPS_REGISTER_TYPE)_entry_point; \
1143!       (_the_context)->c0_sr = ((_intlvl==0)?(0xff00 | _INTON):( ((_intlvl<<9) & 0xfc00) | \
1144!                                                      0x0300 | \
1145                                                       ((_intlvl & 1)?_INTON:0)) ) | \
1146                                SR_CU0 | ((_is_fp)?SR_CU1:0) | _EXTRABITS; \
1147    }
1148diff -N -P -r -c -b -X /home/posixfsw/rtems/production/diff-exclude-files cpukit/score/cpu/mips/rtems/score/mips.h /home/posixfsw/rtems/production/rtems-ss-20030703/cpukit/score/cpu/mips/rtems/score/mips.h
1149*** cpukit/score/cpu/mips/rtems/score/mips.h    Thu Sep  4 14:47:30 2003
1150--- /home/posixfsw/rtems/production/rtems-ss-20030703/cpukit/score/cpu/mips/rtems/score/mips.h  Wed Dec  3 12:07:40 2003
1151***************
1152*** 5,13 ****
1153   *
1154   *  The license and distribution terms for this file may be
1155   *  found in the file LICENSE in this distribution or at
1156!  *  http://www.rtems.com/license/LICENSE.
1157   *
1158!  *  $Id: mips.h,v 1.14.2.1 2003/09/04 18:47:30 joel Exp $
1159   */
1160  /* @(#)mips64orion.h       08/29/96     1.3 */
1161 
1162--- 5,13 ----
1163   *
1164   *  The license and distribution terms for this file may be
1165   *  found in the file LICENSE in this distribution or at
1166!  *  http://www.OARcorp.com/rtems/license.html.
1167   *
1168!  *  mips.h,v 1.14 2002/03/08 16:24:48 joel Exp
1169   */
1170  /* @(#)mips64orion.h       08/29/96     1.3 */
1171 
1172***************
1173*** 28,34 ****
1174   *  NOTE: XXX what about SR_ERL?
1175   */
1176 
1177! #if __mips == 3
1178  #ifdef ASM
1179  #define SR_INTERRUPT_ENABLE_BITS 0x01
1180  #else
1181--- 28,34 ----
1182   *  NOTE: XXX what about SR_ERL?
1183   */
1184 
1185! #if (__mips == 3) || (__mips == 32)
1186  #ifdef ASM
1187  #define SR_INTERRUPT_ENABLE_BITS 0x01
1188  #else
1189***************
1190*** 57,65 ****
1191  #define MIPS_HAS_FPU 1
1192  #endif
1193 
1194  #if (__mips == 1)
1195  #define CPU_MODEL_NAME  "ISA Level 1 or 2"
1196! #elif (__mips == 3)
1197  #if defined(__mips64)
1198  #define CPU_MODEL_NAME  "ISA Level 4"
1199  #else
1200--- 57,66 ----
1201  #define MIPS_HAS_FPU 1
1202  #endif
1203 
1204+
1205  #if (__mips == 1)
1206  #define CPU_MODEL_NAME  "ISA Level 1 or 2"
1207! #elif (__mips == 3) || (__mips == 32)
1208  #if defined(__mips64)
1209  #define CPU_MODEL_NAME  "ISA Level 4"
1210  #else
1211***************
1212*** 216,221 ****
1213--- 217,224 ----
1214   *  Access FCR31
1215   */
1216 
1217+ #if ( MIPS_HAS_FPU == 1 )
1218+
1219  #define mips_get_fcr31( _x ) \
1220    do { \
1221      asm volatile( "cfc1 %0, $31; nop" : "=r" (_x) : ); \
1222***************
1223*** 228,233 ****
1224--- 231,242 ----
1225      asm volatile( "ctc1 %0, $31; nop" : : "r" (__x) ); \
1226    } while(0)
1227 
1228+ #else
1229+
1230+ #define mips_get_fcr31( _x )
1231+ #define mips_set_fcr31( _x )
1232+
1233+ #endif
1234 
1235  /*
1236   *  Manipulate interrupt mask