Ticket #581: psim_patch.txt

File psim_patch.txt, 56.8 KB (added by Jennifer Averett, on 12/03/06 at 13:31:12)

psim_patch.txt

Line 
1diff -uNr /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/clock/Makefile.am psim/clock/Makefile.am
2--- /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/clock/Makefile.am       2002-12-16 18:25:25.000000000 -0600
3+++ psim/clock/Makefile.am      2004-03-01 13:50:16.000000000 -0600
4@@ -2,10 +2,9 @@
5## $Id: Makefile.am,v 1.6 2002/12/17 00:25:25 ralf Exp $
6##
7
8+VPATH = @srcdir@:@srcdir@/../../shared/clock
9
10-PGM = $(ARCH)/clock.rel
11-
12-C_FILES = clock.c
13+C_FILES = p_clock.c
14C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.$(OBJEXT))
15
16OBJS = $(C_O_FILES)
17@@ -17,15 +16,8 @@
18# (OPTIONAL) Add local stuff here using +=
19#
20
21-$(PGM): $(OBJS)
22-       $(make-rel)
23-
24# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile
25
26-all-local: $(ARCH) $(OBJS) $(PGM)
27-
28-.PRECIOUS: $(PGM)
29-
30-EXTRA_DIST = clock.c
31+all-local: $(ARCH) $(OBJS)
32
33include $(top_srcdir)/../../../../../../automake/local.am
34diff -uNr /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/configure.ac psim/configure.ac
35--- /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/configure.ac    2003-08-11 09:37:37.000000000 -0500
36+++ psim/configure.ac   2004-03-01 13:38:04.000000000 -0600
37@@ -38,6 +38,7 @@
38clock/Makefile
39console/Makefile
40include/Makefile
41+irq/Makefile
42shmsupp/Makefile
43start/Makefile
44startup/Makefile
45@@ -45,6 +46,6 @@
46vectors/Makefile
47wrapup/Makefile])
48
49-RTEMS_PPC_EXCEPTIONS([old])
50+RTEMS_PPC_EXCEPTIONS([new])
51
52AC_OUTPUT
53diff -uNr /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/include/bsp.h psim/include/bsp.h
54--- /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/include/bsp.h   2003-09-04 13:45:12.000000000 -0500
55+++ psim/include/bsp.h  2004-03-01 15:41:39.000000000 -0600
56@@ -54,9 +54,10 @@
57#else
58#include <rtems.h>
59#include <console.h>
60+#include <libcpu/io.h>
61#include <clockdrv.h>
62-#include <console.h>
63#include <iosupp.h>
64+#include <bsp/vectors.h>
65
66/*
67*  Define the time limits for RTEMS Test Suite test durations.
68@@ -73,11 +74,31 @@
69/*
70*  Stuff for Time Test 27
71*/
72+#if defined(RTEMS_TM27)
73+
74+#include <bsp/irq.h>
75
76#define MUST_WAIT_FOR_INTERRUPT 1
77
78-#define Install_tm27_vector( _handler ) \
79-  set_vector( (_handler), PPC_IRQ_DECREMENTER, 1 )
80+/* #define Install_tm27_vector( _handler ) \
81+   set_vector( (_handler), PPC_IRQ_DECREMENTER, 1 ) */
82+
83+void nullFunc() {}
84+static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER,
85+                                              0,
86+                                              (rtems_irq_enable)nullFunc,
87+                                              (rtems_irq_disable)nullFunc,
88+                                              (rtems_irq_is_enabled) nullFunc};
89+
90+void Install_tm27_vector(void (*_handler)())
91+{
92+  clockIrqData.hdl = _handler;
93+  if (!BSP_install_rtems_irq_handler (&clockIrqData)) {
94+        printk("Error installing clock interrupt handler!\n");
95+        rtems_fatal_error_occurred(1);
96+  }
97+}
98+
99
100#define Cause_tm27_intr()  \
101 do { \
102@@ -88,8 +109,6 @@
103
104#define Clear_tm27_intr() \
105 do { \
106-    unsigned32 _clicks = 0xffffffff; \
107-    asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
108 } while (0)
109
110#define Lower_tm27_intr() \
111@@ -100,6 +119,7 @@
112   _msr |=  0x8002; \
113   asm volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
114 } while (0)
115+#endif
116
117/* Constants */
118
119@@ -132,6 +152,19 @@
120
121extern int   end;        /* last address in the program */
122
123+/*
124+ * PCI Bus Frequency
125+ */
126+extern unsigned int BSP_bus_frequency;
127+
128+/*
129+ * Time base divisior (how many tick for 1 second).
130+ */
131+extern unsigned int BSP_time_base_divisor;
132+
133+#define BSP_Convert_decrementer( _value ) \
134+  ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value)))
135+
136/* functions */
137
138void bsp_start( void );
139diff -uNr /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/irq/irq_asm.S psim/irq/irq_asm.S
140--- /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/irq/irq_asm.S   1969-12-31 18:00:00.000000000 -0600
141+++ psim/irq/irq_asm.S  2004-03-01 13:38:04.000000000 -0600
142@@ -0,0 +1,357 @@
143+/*
144+ *  This file contains the assembly code for the PowerPC
145+ *  IRQ veneers for RTEMS.
146+ *
147+ *  The license and distribution terms for this file may be
148+ *  found in found in the file LICENSE in this distribution or at
149+ *  http://www.rtems.com/license/LICENSE.
150+ *
151+ *  Modified to support the MCP750.
152+ *  Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
153+ *
154+ *  Till Straumann <strauman@slac.stanford.edu>, 2003/7:
155+ *    - store isr nesting level in _ISR_Nest_level rather than
156+ *      SPRG0 - RTEMS relies on that variable.
157+ *
158+ * irq_asm.S,v 1.5.4.3 2003/09/04 18:45:20 joel Exp
159+ */
160+       
161+#include <asm.h>
162+#include <rtems/score/cpu.h>
163+#include <bsp/vectors.h>
164+#include <libcpu/raw_exception.h>
165+       
166+
167+#define SYNC \
168+       sync; \
169+       isync
170+       
171+       .text
172+       .p2align 5     
173+               
174+       PUBLIC_VAR(decrementer_exception_vector_prolog_code)
175+       
176+SYM (decrementer_exception_vector_prolog_code):
177+       /*
178+        * let room for exception frame
179+        */
180+       stwu    r1, - (EXCEPTION_FRAME_END)(r1)
181+       stw     r4, GPR4_OFFSET(r1)
182+       li      r4, ASM_DEC_VECTOR
183+       ba      shared_raw_irq_code_entry
184+
185+       PUBLIC_VAR (decrementer_exception_vector_prolog_code_size)
186+       
187+       decrementer_exception_vector_prolog_code_size = . - decrementer_exception_vector_prolog_code
188+
189+       PUBLIC_VAR(external_exception_vector_prolog_code)
190+       
191+SYM (external_exception_vector_prolog_code):
192+       /*
193+        * let room for exception frame
194+        */
195+       stwu    r1, - (EXCEPTION_FRAME_END)(r1)
196+       stw     r4, GPR4_OFFSET(r1)
197+       li      r4, ASM_EXT_VECTOR
198+       ba      shared_raw_irq_code_entry
199+
200+       PUBLIC_VAR (external_exception_vector_prolog_code_size)
201+       
202+       external_exception_vector_prolog_code_size = . - external_exception_vector_prolog_code
203+
204+       PUBLIC_VAR(shared_raw_irq_code_entry)
205+       PUBLIC_VAR(C_dispatch_irq_handler)
206+       
207+       .p2align 5
208+SYM (shared_raw_irq_code_entry):
209+       /*
210+        * Entry conditions :
211+        *      Registers already saved : R1, R4
212+        *      R1  :   points to a location with enough room for the
213+        *              interrupt frame
214+        *      R4  :   vector number
215+        */
216+       /*
217+        * Save SRR0/SRR1 As soon As possible as it is the minimal needed
218+        * to reenable exception processing
219+        */
220+       stw     r0, GPR0_OFFSET(r1)
221+       /* PPC EABI: R2 is reserved (pointer to short data .sdata2) - we won't touch it
222+        * but we still save/restore it, just in case...
223+        */
224+       stw     r2, GPR2_OFFSET(r1)
225+       stw     r3, GPR3_OFFSET(r1)
226+       
227+       mfsrr0  r0
228+       mfsrr1  r3
229+       
230+       stw     r0, SRR0_FRAME_OFFSET(r1)
231+       stw     r3, SRR1_FRAME_OFFSET(r1)
232+
233+       mfmsr   r3
234+       /*
235+        * Enable data and instruction address translation, exception recovery
236+     *
237+     * also, on CPUs with FP, enable FP so that FP context can be
238+     * saved and restored (using FP instructions)
239+        */
240+#if (PPC_HAS_FPU == 0)
241+       ori     r3, r3, MSR_RI | MSR_IR | MSR_DR
242+#else
243+       ori     r3, r3, MSR_RI | MSR_FP  /* MSR_IR | MSR_DR */
244+#endif
245+       mtmsr   r3
246+       SYNC
247+       /*
248+        * Push C scratch registers on the current stack. It may
249+        * actually be the thread stack or the interrupt stack.
250+        * Anyway we have to make it in order to be able to call C/C++
251+        * functions. Depending on the nesting interrupt level, we will
252+        * switch to the right stack later.
253+        */
254+       stw     r5, GPR5_OFFSET(r1)
255+       stw     r6, GPR6_OFFSET(r1)
256+       stw     r7, GPR7_OFFSET(r1)
257+       stw     r8, GPR8_OFFSET(r1)
258+       stw     r9, GPR9_OFFSET(r1)
259+       stw     r10, GPR10_OFFSET(r1)
260+       stw     r11, GPR11_OFFSET(r1)
261+       stw     r12, GPR12_OFFSET(r1)
262+       stw     r13, GPR13_OFFSET(r1)
263+
264+       mfcr    r5
265+       mfctr   r6
266+       mfxer   r7
267+       mflr    r8
268+       
269+       stw     r5,  EXC_CR_OFFSET(r1)
270+       stw     r6,  EXC_CTR_OFFSET(r1)
271+       stw     r7,  EXC_XER_OFFSET(r1)
272+       stw     r8,  EXC_LR_OFFSET(r1)
273+
274+       /*
275+        * Add some non volatile registers to store information
276+        * that will be used when returning from C handler
277+        */
278+       stw     r14, GPR14_OFFSET(r1)
279+       stw     r15, GPR15_OFFSET(r1)
280+       /*
281+        * save current stack pointer location in R14
282+        */
283+       addi    r14, r1, 0
284+       /*
285+        * store part of _Thread_Dispatch_disable_level address in R15
286+        */
287+       addis r15,0, _Thread_Dispatch_disable_level@ha
288+#if BROKEN_ISR_NEST_LEVEL
289+       /*
290+        * Get current nesting level in R3
291+        */
292+       mfspr   r3, SPRG0
293+#else
294+       /*
295+        * Retrieve current nesting level from _ISR_Nest_level
296+        */
297+       lis             r7, _ISR_Nest_level@ha
298+       lwz             r3, _ISR_Nest_level@l(r7)
299+#endif
300+       /*
301+        * Check if stack switch is necessary
302+        */
303+       cmpwi   r3,0
304+       bne     nested
305+       mfspr   r1, SPRG1
306+       
307+nested:       
308+       /*
309+        * Start Incrementing nesting level in R3
310+        */
311+       addi    r3,r3,1
312+       /*
313+        * Start Incrementing _Thread_Dispatch_disable_level R4 = _Thread_Dispatch_disable_level
314+        */
315+       lwz     r6,_Thread_Dispatch_disable_level@l(r15)
316+#if BROKEN_ISR_NEST_LEVEL
317+       /*
318+        * Store new nesting level in SPRG0
319+        */
320+       mtspr   SPRG0, r3
321+#else
322+       /* store new nesting level in _ISR_Nest_level */
323+       stw             r3, _ISR_Nest_level@l(r7)
324+#endif
325+       
326+       addi    r6, r6, 1
327+       mfmsr   r5
328+       /*
329+        * store new _Thread_Dispatch_disable_level value
330+        */
331+       stw     r6, _Thread_Dispatch_disable_level@l(r15)
332+       /*
333+        * We are now running on the interrupt stack. External and decrementer
334+        * exceptions are still disabled. I see no purpose trying to optimize
335+        * further assembler code.
336+        */
337+       /*
338+        * Call C exception handler for decrementer Interrupt frame is passed just
339+        * in case...
340+        */
341+       addi    r3, r14, 0x8
342+       bl      C_dispatch_irq_handler /* C_dispatch_irq_handler(cpu_interrupt_frame* r3, vector r4) */
343+       /*
344+        * start decrementing nesting level. Note : do not test result against 0
345+        * value as an easy exit condition because if interrupt nesting level > 1
346+        * then _Thread_Dispatch_disable_level > 1
347+        */
348+#if BROKEN_ISR_NEST_LEVEL
349+       mfspr   r4, SPRG0
350+#else
351+       lis             r7, _ISR_Nest_level@ha
352+       lwz             r4, _ISR_Nest_level@l(r7)
353+#endif
354+       /*
355+        * start decrementing _Thread_Dispatch_disable_level
356+        */
357+       lwz     r3,_Thread_Dispatch_disable_level@l(r15)
358+       addi    r4, r4, -1      /* Continue decrementing nesting level */
359+       addi    r3, r3, -1      /* Continue decrementing _Thread_Dispatch_disable_level */
360+#if BROKEN_ISR_NEST_LEVEL
361+       mtspr   SPRG0, r4       /* End decrementing nesting level */
362+#else
363+       stw             r4, _ISR_Nest_level@l(r7) /* End decrementing nesting level */
364+#endif
365+       stw     r3,_Thread_Dispatch_disable_level@l(r15) /* End decrementing _Thread_Dispatch_disable_level */
366+       cmpwi   r3, 0
367+       /*
368+        * switch back to original stack (done here just optimize registers
369+        * contention. Could have been done before...)
370+        */
371+       addi    r1, r14, 0
372+       bne     easy_exit /* if (_Thread_Dispatch_disable_level != 0) goto easy_exit */
373+       /*
374+        * Here we are running again on the thread system stack.
375+        * We have interrupt nesting level = _Thread_Dispatch_disable_level = 0.
376+        * Interrupt are still disabled. Time to check if scheduler request to
377+        * do something with the current thread...
378+        */
379+       addis   r4, 0, _Context_Switch_necessary@ha
380+       lwz     r5, _Context_Switch_necessary@l(r4)
381+       cmpwi   r5, 0
382+       bne     switch
383+       
384+       addis   r6, 0, _ISR_Signals_to_thread_executing@ha
385+       lwz     r7, _ISR_Signals_to_thread_executing@l(r6)
386+       cmpwi   r7, 0
387+       li      r8, 0
388+       beq     easy_exit
389+       stw     r8, _ISR_Signals_to_thread_executing@l(r6)
390+       /*
391+        * going to call _ThreadProcessSignalsFromIrq
392+        * Push a complete exception like frame...
393+        */
394+       stmw    r16, GPR16_OFFSET(r1)
395+       addi    r3, r1, 0x8
396+       /*
397+        * compute SP at exception entry
398+        */
399+       addi    r4, r1, EXCEPTION_FRAME_END
400+       /*
401+        * store it at the right place
402+        */
403+       stw     r4, GPR1_OFFSET(r1)
404+       /*
405+        * Call High Level signal handling code
406+        */
407+       bl      _ThreadProcessSignalsFromIrq
408+       /*
409+        * start restoring exception like frame
410+        */
411+       lwz     r31,  EXC_CTR_OFFSET(r1)
412+       lwz     r30,  EXC_XER_OFFSET(r1)
413+       lwz     r29,  EXC_CR_OFFSET(r1)
414+       lwz     r28,  EXC_LR_OFFSET(r1)
415+       
416+       mtctr   r31
417+       mtxer   r30
418+       mtcr    r29
419+       mtlr    r28
420+       
421+       lmw     r4, GPR4_OFFSET(r1)
422+       lwz     r2, GPR2_OFFSET(r1)
423+       lwz     r0, GPR0_OFFSET(r1)
424+
425+       /*
426+        * Disable data and instruction translation. Make path non recoverable...
427+        */
428+       mfmsr   r3
429+       xori    r3, r3, MSR_RI /* | MSR_IR | MSR_DR */
430+       mtmsr   r3
431+       SYNC
432+       /*
433+        * Restore rfi related settings
434+        */
435+               
436+       lwz     r3, SRR1_FRAME_OFFSET(r1)
437+       mtsrr1  r3
438+       lwz     r3, SRR0_FRAME_OFFSET(r1)
439+       mtsrr0  r3
440+       
441+       lwz     r3, GPR3_OFFSET(r1)
442+       addi    r1,r1, EXCEPTION_FRAME_END
443+       SYNC
444+       rfi
445+       
446+switch:
447+       bl      SYM (_Thread_Dispatch)
448+       
449+easy_exit:     
450+       /*
451+        * start restoring interrupt frame
452+        */
453+       lwz     r3,  EXC_CTR_OFFSET(r1)
454+       lwz     r4,  EXC_XER_OFFSET(r1)
455+       lwz     r5,  EXC_CR_OFFSET(r1)
456+       lwz     r6,  EXC_LR_OFFSET(r1)
457+       
458+       mtctr   r3
459+       mtxer   r4
460+       mtcr    r5
461+       mtlr    r6
462+
463+       lwz     r15, GPR15_OFFSET(r1)
464+       lwz     r14, GPR14_OFFSET(r1)
465+       lwz     r13, GPR13_OFFSET(r1)
466+       lwz     r12, GPR12_OFFSET(r1)
467+       lwz     r11, GPR11_OFFSET(r1)
468+       lwz     r10, GPR10_OFFSET(r1)
469+       lwz     r9, GPR9_OFFSET(r1)
470+       lwz     r8, GPR8_OFFSET(r1)
471+       lwz     r7, GPR7_OFFSET(r1)
472+       lwz     r6, GPR6_OFFSET(r1)
473+       lwz     r5, GPR5_OFFSET(r1)
474+
475+       /*
476+        * Disable nested exception processing, data and instruction
477+        * translation.
478+        */
479+       mfmsr   r3
480+       xori    r3, r3, MSR_RI /* | MSR_IR | MSR_DR */
481+       mtmsr   r3
482+       SYNC
483+       /*
484+        * Restore rfi related settings
485+        */
486+               
487+       lwz     r4, SRR1_FRAME_OFFSET(r1)
488+       lwz     r3, SRR0_FRAME_OFFSET(r1)
489+       lwz     r2, GPR2_OFFSET(r1)
490+       lwz     r0, GPR0_OFFSET(r1)
491+
492+       mtsrr1  r4
493+       mtsrr0  r3
494+       lwz     r4, GPR4_OFFSET(r1)
495+       lwz     r3, GPR3_OFFSET(r1)
496+       addi    r1,r1, EXCEPTION_FRAME_END
497+       SYNC
498+       rfi
499+
500diff -uNr /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/irq/irq.c psim/irq/irq.c
501--- /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/irq/irq.c       1969-12-31 18:00:00.000000000 -0600
502+++ psim/irq/irq.c      2004-03-01 13:38:04.000000000 -0600
503@@ -0,0 +1,361 @@
504+/*
505+ *
506+ *  This file contains the implementation of the function described in irq.h
507+ *
508+ *  Copyright (C) 1998, 1999 valette@crf.canon.fr
509+ *
510+ *  The license and distribution terms for this file may be
511+ *  found in found in the file LICENSE in this distribution or at
512+ *  http://www.rtems.com/license/LICENSE.
513+ *
514+ *  irq.c,v 1.4.2.8 2003/09/04 18:45:20 joel Exp
515+ */
516+ 
517+#include <rtems/system.h>
518+#include <bsp.h>
519+#include <bsp/irq.h>
520+#if 0
521+#include <bsp/VME.h>
522+#include <bsp/openpic.h>
523+#endif
524+#include <stdlib.h>
525+
526+#include <rtems/score/thread.h>
527+#include <rtems/score/apiext.h>
528+#include <libcpu/raw_exception.h>
529+#include <libcpu/io.h>
530+#include <bsp/vectors.h>
531+
532+#include <rtems/bspIo.h> /* for printk */
533+#define RAVEN_INTR_ACK_REG 0xfeff0030
534+
535+/*
536+ * pointer to the mask representing the additionnal irq vectors
537+ * that must be disabled when a particular entry is activated.
538+ * They will be dynamically computed from teh prioruty table given
539+ * in BSP_rtems_irq_mngt_set();
540+ * CAUTION : this table is accessed directly by interrupt routine
541+ *          prologue.
542+ */
543+rtems_i8259_masks      irq_mask_or_tbl[BSP_IRQ_NUMBER];
544+/*
545+ * default handler connected on each irq after bsp initialization
546+ */
547+static rtems_irq_connect_data  default_rtems_entry;
548+
549+/*
550+ * location used to store initial tables used for interrupt
551+ * management.
552+ */
553+static rtems_irq_global_settings*      internal_config;
554+static rtems_irq_connect_data*         rtems_hdl_tbl;
555+
556+/*
557+ * Check if IRQ is an ISA IRQ
558+ */
559+static inline int is_isa_irq(const rtems_irq_symbolic_name irqLine)
560+{
561+  return (((int) irqLine <= BSP_ISA_IRQ_MAX_OFFSET) &
562+         ((int) irqLine >= BSP_ISA_IRQ_LOWEST_OFFSET)
563+        );
564+}
565+
566+/*
567+ * Check if IRQ is an OPENPIC IRQ
568+ */
569+static inline int is_pci_irq(const rtems_irq_symbolic_name irqLine)
570+{
571+  return (((int) irqLine <= BSP_PCI_IRQ_MAX_OFFSET) &
572+         ((int) irqLine >= BSP_PCI_IRQ_LOWEST_OFFSET)
573+        );
574+}
575+
576+/*
577+ * Check if IRQ is a Porcessor IRQ
578+ */
579+static inline int is_processor_irq(const rtems_irq_symbolic_name irqLine)
580+{
581+  return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) &
582+         ((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
583+        );
584+}
585+
586+
587+/*
588+ * ------------------------ RTEMS Irq helper functions ----------------
589+ */
590+
591+/*
592+ * Caution : this function assumes the variable "internal_config"
593+ * is already set and that the tables it contains are still valid
594+ * and accessible.
595+ */
596+static void compute_i8259_masks_from_prio ()
597+{
598+  int i;
599+  int j;
600+  /*
601+   * Always mask at least current interrupt to prevent re-entrance
602+   */
603+  for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) {
604+    * ((unsigned short*) &irq_mask_or_tbl[i]) = (1 << i);
605+    for (j = BSP_ISA_IRQ_LOWEST_OFFSET; j < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; j++) {
606+      /*
607+       * Mask interrupts at i8259 level that have a lower priority
608+       */
609+      if (internal_config->irqPrioTbl [i] > internal_config->irqPrioTbl [j]) {
610+       * ((unsigned short*) &irq_mask_or_tbl[i]) |= (1 << j);
611+      }
612+    }
613+  }
614+}
615+
616+/*
617+ * This function check that the value given for the irq line
618+ * is valid.
619+ */
620+
621+static int isValidInterrupt(int irq)
622+{
623+  if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET))
624+    return 0;
625+  return 1;
626+}
627+
628+
629+/*
630+ * ------------------------ RTEMS Shared Irq Handler Mngt Routines ----------------
631+ */
632+int BSP_install_rtems_shared_irq_handler  (const rtems_irq_connect_data* irq)
633+{
634+  printk("BSP_insall_rtems_shared_irq_handler Not supported in psim\n");
635+  return 0;
636+}
637+
638+
639+/*
640+ * ------------------------ RTEMS Single Irq Handler Mngt Routines ----------------
641+ */
642+
643+int BSP_install_rtems_irq_handler  (const rtems_irq_connect_data* irq)
644+{
645+    unsigned int level;
646+ 
647+    if (!isValidInterrupt(irq->name)) {
648+      printk("Invalid interrupt vector %d\n",irq->name);
649+      return 0;
650+    }
651+    /*
652+     * Check if default handler is actually connected. If not issue an error.
653+     * You must first get the current handler via i386_get_current_idt_entry
654+     * and then disconnect it using i386_delete_idt_entry.
655+     * RATIONALE : to always have the same transition by forcing the user
656+     * to get the previous handler before accepting to disconnect.
657+     */
658+    _CPU_ISR_Disable(level);
659+    if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) {
660+      _CPU_ISR_Enable(level);
661+      printk("IRQ vector %d already connected\n",irq->name);
662+      return 0;
663+    }
664+
665+    /*
666+     * store the data provided by user
667+     */
668+    rtems_hdl_tbl[irq->name] = *irq;
669+    rtems_hdl_tbl[irq->name].next_handler = (void *)-1;
670+   
671+    if (is_isa_irq(irq->name)) {
672+      printk("What's a isa_irq on psim?");
673+    }
674+
675+    if (is_processor_irq(irq->name)) {
676+      /*
677+       * Enable exception at processor level
678+       */
679+    }
680+    /*
681+     * Enable interrupt on device
682+     */
683+    irq->on(irq);
684+   
685+    _CPU_ISR_Enable(level);
686+
687+    return 1;
688+}
689+
690+
691+int BSP_get_current_rtems_irq_handler  (rtems_irq_connect_data* irq)
692+{
693+     unsigned int level;
694+
695+     if (!isValidInterrupt(irq->name)) {
696+      return 0;
697+     }
698+     _CPU_ISR_Disable(level);
699+     *irq = rtems_hdl_tbl[irq->name];
700+     _CPU_ISR_Enable(level);
701+     return 1;
702+}
703+
704+int BSP_remove_rtems_irq_handler  (const rtems_irq_connect_data* irq)
705+{
706+   rtems_irq_connect_data *pchain= NULL, *vchain = NULL;
707+    unsigned int level;
708+ 
709+    if (!isValidInterrupt(irq->name)) {
710+      return 0;
711+    }
712+    /*
713+     * Check if default handler is actually connected. If not issue an error.
714+     * You must first get the current handler via i386_get_current_idt_entry
715+     * and then disconnect it using i386_delete_idt_entry.
716+     * RATIONALE : to always have the same transition by forcing the user
717+     * to get the previous handler before accepting to disconnect.
718+     */
719+    _CPU_ISR_Disable(level);
720+    if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) {
721+      _CPU_ISR_Enable(level);
722+      return 0;
723+    }
724+
725+    if( (int)rtems_hdl_tbl[irq->name].next_handler != -1 )
726+    {
727+       int found = 0;
728+
729+       for( (pchain= NULL, vchain = &rtems_hdl_tbl[irq->name]);
730+            (vchain->hdl != default_rtems_entry.hdl);
731+            (pchain= vchain, vchain = (rtems_irq_connect_data*)vchain->next_handler) )
732+       {
733+          if( vchain->hdl == irq->hdl )
734+          {
735+             found= -1; break;
736+          }
737+       }
738+
739+       if( !found )
740+       {
741+          _CPU_ISR_Enable(level);
742+          return 0;
743+       }
744+    }
745+    else
746+    {
747+       if (rtems_hdl_tbl[irq->name].hdl != irq->hdl)
748+       {
749+          _CPU_ISR_Enable(level);
750+         return 0;
751+       }
752+    }
753+
754+    if (is_isa_irq(irq->name)) {
755+      printk("isa irq on psim?");
756+    }
757+    if (is_processor_irq(irq->name)) {
758+      /*
759+       * disable exception at processor level
760+       */
761+    }   
762+
763+    /*
764+     * Disable interrupt on device
765+     */
766+    irq->off(irq);
767+
768+    /*
769+     * restore the default irq value
770+     */
771+    if( !vchain )
772+    {
773+       /* single handler vector... */
774+       rtems_hdl_tbl[irq->name] = default_rtems_entry;
775+    }
776+    else
777+    {
778+       if( pchain )
779+       {
780+          /* non-first handler being removed */
781+          pchain->next_handler = vchain->next_handler;
782+       }
783+       else
784+       {
785+          /* first handler isn't malloc'ed, so just overwrite it.  Since
786+          the contents of vchain are being struct copied, vchain itself
787+          goes away */
788+          rtems_hdl_tbl[irq->name]= *vchain;
789+       }
790+       free(vchain);
791+    }
792+
793+    _CPU_ISR_Enable(level);
794+
795+    return 1;
796+}
797+
798+/*
799+ * ------------------------ RTEMS Global Irq Handler Mngt Routines ----------------
800+ */
801+
802+int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
803+{
804+   /*
805+    * Store various code accelerators
806+    */
807+    internal_config            = config;
808+    default_rtems_entry        = config->defaultEntry;
809+    rtems_hdl_tbl              = config->irqHdlTbl;
810+   
811+    return 1;
812+}
813+
814+int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config)
815+{
816+    *config = internal_config;
817+    return 0;
818+}   
819+
820+int _BSP_vme_bridge_irq = -1;
821+
822+unsigned BSP_spuriousIntr = 0;
823+
824+/*
825+ * High level IRQ handler called from shared_raw_irq_code_entry
826+ */
827+void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
828+{
829+  register unsigned msr;
830+  register unsigned new_msr;
831+
832+  if (excNum == ASM_DEC_VECTOR) {
833+    _CPU_MSR_GET(msr);
834+    new_msr = msr | MSR_EE;
835+    _CPU_MSR_SET(new_msr);
836+   
837+    rtems_hdl_tbl[BSP_DECREMENTER].hdl();
838+
839+    _CPU_MSR_SET(msr);
840+    return;
841+   
842+  }
843+}
844+   
845+   
846+ 
847+void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx)
848+{
849+  /*
850+   * Process pending signals that have not already been
851+   * processed by _Thread_Displatch. This happens quite
852+   * unfrequently : the ISR must have posted an action
853+   * to the current running thread.
854+   */
855+  if ( _Thread_Do_post_task_switch_extension ||
856+       _Thread_Executing->do_post_task_switch_extension ) {
857+    _Thread_Executing->do_post_task_switch_extension = FALSE;
858+    _API_extensions_Run_postswitch();
859+  }
860+  /*
861+   * I plan to process other thread related events here.
862+   * This will include DEBUG session requested from keyboard...
863+   */
864+}
865diff -uNr /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/irq/irq.h psim/irq/irq.h
866--- /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/irq/irq.h       1969-12-31 18:00:00.000000000 -0600
867+++ psim/irq/irq.h      2004-03-01 13:38:04.000000000 -0600
868@@ -0,0 +1,333 @@
869+/* irq.h
870+ *
871+ *  This include file describe the data structure and the functions implemented
872+ *  by rtems to write interrupt handlers.
873+ *
874+ *  CopyRight (C) 1999 valette@crf.canon.fr
875+ *
876+ *  This code is heavilly inspired by the public specification of STREAM V2
877+ *  that can be found at :
878+ *
879+ *      <http://www.chorus.com/Documentation/index.html> by following
880+ *  the STREAM API Specification Document link.
881+ *
882+ *  The license and distribution terms for this file may be
883+ *  found in found in the file LICENSE in this distribution or at
884+ *  http://www.rtems.com/license/LICENSE.
885+ *
886+ *  irq.h,v 1.2.4.2 2003/09/04 18:45:20 joel Exp
887+ */
888+
889+#ifndef LIBBSP_POWERPC_MCP750_IRQ_IRQ_H
890+#define LIBBSP_POWERPC_MCP750_IRQ_IRQ_H
891+
892+
893+/*
894+ * 8259 edge/level control definitions at VIA
895+ */
896+#define ISA8259_M_ELCR                 0x4d0
897+#define ISA8259_S_ELCR                 0x4d1
898+
899+#define ELCRS_INT15_LVL         0x80
900+#define ELCRS_INT14_LVL         0x40
901+#define ELCRS_INT13_LVL         0x20
902+#define ELCRS_INT12_LVL         0x10
903+#define ELCRS_INT11_LVL         0x08
904+#define ELCRS_INT10_LVL         0x04
905+#define ELCRS_INT9_LVL          0x02
906+#define ELCRS_INT8_LVL          0x01
907+#define ELCRM_INT7_LVL          0x80
908+#define ELCRM_INT6_LVL          0x40
909+#define ELCRM_INT5_LVL          0x20
910+#define ELCRM_INT4_LVL          0x10
911+#define ELCRM_INT3_LVL          0x8
912+#define ELCRM_INT2_LVL          0x4
913+#define ELCRM_INT1_LVL          0x2
914+#define ELCRM_INT0_LVL          0x1
915+
916+#define BSP_ASM_IRQ_VECTOR_BASE 0x0
917+    /* PIC's command and mask registers */
918+#define PIC_MASTER_COMMAND_IO_PORT             0x20    /* Master PIC command register */
919+#define PIC_SLAVE_COMMAND_IO_PORT              0xa0    /* Slave PIC command register */
920+#define PIC_MASTER_IMR_IO_PORT                 0x21    /* Master PIC Interrupt Mask Register */
921+#define PIC_SLAVE_IMR_IO_PORT                  0xa1    /* Slave PIC Interrupt Mask Register */
922+
923+    /* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
924+#define PIC_EOSI       0x60    /* End of Specific Interrupt (EOSI) */
925+#define        SLAVE_PIC_EOSI  0x62    /* End of Specific Interrupt (EOSI) for cascade */
926+#define PIC_EOI                0x20    /* Generic End of Interrupt (EOI) */
927+
928+#ifndef ASM
929+
930+
931+/*
932+ * Symblolic IRQ names and related definitions.
933+ */
934+
935+typedef enum {
936+  /* Base vector for our ISA IRQ handlers. */
937+  BSP_ISA_IRQ_VECTOR_BASE      =       BSP_ASM_IRQ_VECTOR_BASE,
938+  /*
939+   * ISA IRQ handler related definitions
940+   */
941+  BSP_ISA_IRQ_NUMBER           =       16,
942+  BSP_ISA_IRQ_LOWEST_OFFSET    =       0,
943+  BSP_ISA_IRQ_MAX_OFFSET       =       BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1,
944+  /*
945+   * PCI IRQ handlers related definitions
946+   * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
947+   */
948+  BSP_PCI_IRQ_NUMBER           =       16,
949+  BSP_PCI_IRQ_LOWEST_OFFSET    =       BSP_ISA_IRQ_NUMBER,
950+  BSP_PCI_IRQ_MAX_OFFSET       =       BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1,
951+  /*
952+   * PowerPc exceptions handled as interrupt where a rtems managed interrupt
953+   * handler might be connected
954+   */
955+  BSP_PROCESSOR_IRQ_NUMBER     =       1,
956+  BSP_PROCESSOR_IRQ_LOWEST_OFFSET =    BSP_PCI_IRQ_MAX_OFFSET + 1,
957+  BSP_PROCESSOR_IRQ_MAX_OFFSET =       BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1,
958+  /* Misc vectors for OPENPIC irqs (IPI, timers)
959+   */
960+  BSP_MISC_IRQ_NUMBER          =       8,
961+  BSP_MISC_IRQ_LOWEST_OFFSET   =       BSP_PROCESSOR_IRQ_MAX_OFFSET + 1,
962+  BSP_MISC_IRQ_MAX_OFFSET      =       BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1,
963+  /*
964+   * Summary
965+   */
966+  BSP_IRQ_NUMBER               =       BSP_MISC_IRQ_MAX_OFFSET + 1,
967+  BSP_LOWEST_OFFSET            =       BSP_ISA_IRQ_LOWEST_OFFSET,
968+  BSP_MAX_OFFSET               =       BSP_MISC_IRQ_MAX_OFFSET,
969+    /*
970+     * Some ISA IRQ symbolic name definition
971+     */               
972+  BSP_ISA_PERIODIC_TIMER       =       0,
973+
974+  BSP_ISA_KEYBOARD             =       1,
975+
976+  BSP_ISA_UART_COM2_IRQ                =       3,
977+
978+  BSP_ISA_UART_COM1_IRQ                =       4,
979+
980+  BSP_ISA_RT_TIMER1            =       8,
981+ 
982+  BSP_ISA_RT_TIMER3            =       10,
983+    /*
984+     * Some PCI IRQ symbolic name definition
985+     */
986+  BSP_PCI_IRQ0                 =       BSP_PCI_IRQ_LOWEST_OFFSET,
987+  BSP_PCI_ISA_BRIDGE_IRQ       =       BSP_PCI_IRQ0,
988+    /*
989+     * Some Processor execption handled as rtems IRQ symbolic name definition
990+     */
991+  BSP_DECREMENTER              =       BSP_PROCESSOR_IRQ_LOWEST_OFFSET
992+ 
993+}rtems_irq_symbolic_name;
994+
995+   
996+
997+
998+/*
999+ * Type definition for RTEMS managed interrupts
1000+ */
1001+typedef unsigned char  rtems_irq_prio;
1002+typedef unsigned short rtems_i8259_masks;
1003+
1004+extern  volatile rtems_i8259_masks i8259s_cache;
1005+
1006+struct         __rtems_irq_connect_data__;     /* forward declaratiuon */
1007+
1008+typedef void (*rtems_irq_hdl)          (void);
1009+typedef void (*rtems_irq_enable)       (const struct __rtems_irq_connect_data__*);
1010+typedef void (*rtems_irq_disable)      (const struct __rtems_irq_connect_data__*);
1011+typedef int  (*rtems_irq_is_enabled)   (const struct __rtems_irq_connect_data__*);
1012+
1013+typedef struct __rtems_irq_connect_data__ {
1014+      /*
1015+       * IRQ line
1016+       */
1017+      rtems_irq_symbolic_name  name;
1018+      /*
1019+       * handler. See comment on handler properties below in function prototype.
1020+       */
1021+      rtems_irq_hdl                    hdl;
1022+      /*
1023+       * function for enabling interrupts at device level (ONLY!).
1024+       * The BSP code will automatically enable it at i8259s level and openpic level.
1025+       * RATIONALE : anyway such code has to exist in current driver code.
1026+       * It is usually called immediately AFTER connecting the interrupt handler.
1027+       * RTEMS may well need such a function when restoring normal interrupt
1028+       * processing after a debug session.
1029+       *
1030+       */
1031+      rtems_irq_enable         on;     
1032+      /*
1033+       * function for disabling interrupts at device level (ONLY!).
1034+       * The code will disable it at i8259s level. RATIONALE : anyway
1035+       * such code has to exist for clean shutdown. It is usually called
1036+       * BEFORE disconnecting the interrupt. RTEMS may well need such
1037+       * a function when disabling normal interrupt processing for
1038+       * a debug session. May well be a NOP function.
1039+       */
1040+      rtems_irq_disable                off;
1041+      /*
1042+       * function enabling to know what interrupt may currently occur
1043+       * if someone manipulates the i8259s interrupt mask without care...
1044+       */
1045+      rtems_irq_is_enabled     isOn;
1046+      /*
1047+       *  Set to -1 for vectors forced to have only 1 handler
1048+       */
1049+      void *next_handler;
1050+
1051+}rtems_irq_connect_data;
1052+
1053+typedef struct {
1054+  /*
1055+   * size of all the table fields (*Tbl) described below.
1056+   */
1057+  unsigned int                 irqNb;
1058+  /*
1059+   * Default handler used when disconnecting interrupts.
1060+   */
1061+  rtems_irq_connect_data       defaultEntry;
1062+  /*
1063+   * Table containing initials/current value.
1064+   */
1065+  rtems_irq_connect_data*      irqHdlTbl;
1066+  /*
1067+   * actual value of BSP_ISA_IRQ_VECTOR_BASE...
1068+   */
1069+  rtems_irq_symbolic_name      irqBase;
1070+  /*
1071+   * software priorities associated with interrupts.
1072+   * if irqPrio  [i]  >  intrPrio  [j]  it  means  that 
1073+   * interrupt handler hdl connected for interrupt name i
1074+   * will  not be interrupted by the handler connected for interrupt j
1075+   * The interrupt source  will be physically masked at i8259 level.
1076+   */
1077+    rtems_irq_prio*            irqPrioTbl;
1078+}rtems_irq_global_settings;
1079+
1080+
1081+
1082+
1083+/*-------------------------------------------------------------------------+
1084+| Function Prototypes.
1085++--------------------------------------------------------------------------*/
1086+/*
1087+ * ------------------------ Intel 8259 (or emulation) Mngt Routines -------
1088+ */
1089+
1090+/*
1091+ * function to disable a particular irq at 8259 level. After calling
1092+ * this function, even if the device asserts the interrupt line it will
1093+ * not be propagated further to the processor
1094+ */
1095+int BSP_irq_disable_at_i8259s        (const rtems_irq_symbolic_name irqLine);
1096+/*
1097+ * function to enable a particular irq at 8259 level. After calling
1098+ * this function, if the device asserts the interrupt line it will
1099+ * be propagated further to the processor
1100+ */
1101+int BSP_irq_enable_at_i8259s           (const rtems_irq_symbolic_name irqLine);
1102+/*
1103+ * function to acknoledge a particular irq at 8259 level. After calling
1104+ * this function, if a device asserts an enabled interrupt line it will
1105+ * be propagated further to the processor. Mainly usefull for people
1106+ * writting raw handlers as this is automagically done for rtems managed
1107+ * handlers.
1108+ */
1109+int BSP_irq_ack_at_i8259s              (const rtems_irq_symbolic_name irqLine);
1110+/*
1111+ * function to check if a particular irq is enabled at 8259 level. After calling
1112+ */
1113+int BSP_irq_enabled_at_i8259s          (const rtems_irq_symbolic_name irqLine);
1114+/*
1115+ * ------------------------ RTEMS Single Irq Handler Mngt Routines ----------------
1116+ */
1117+/*
1118+ * function to connect a particular irq handler. This hanlder will NOT be called
1119+ * directly as the result of the corresponding interrupt. Instead, a RTEMS
1120+ * irq prologue will be called that will :
1121+ *
1122+ *     1) save the C scratch registers,
1123+ *     2) switch to a interrupt stack if the interrupt is not nested,
1124+ *     3) store the current i8259s' interrupt masks
1125+ *     4) modify them to disable the current interrupt at 8259 level (and may
1126+ *     be others depending on software priorities)
1127+ *     5) aknowledge the i8259s',
1128+ *     6) demask the processor,
1129+ *     7) call the application handler
1130+ *
1131+ * As a result the hdl function provided
1132+ *
1133+ *     a) can perfectly be written is C,
1134+ *     b) may also well directly call the part of the RTEMS API that can be used
1135+ *     from interrupt level,
1136+ *     c) It only responsible for handling the jobs that need to be done at
1137+ *     the device level including (aknowledging/re-enabling the interrupt at device,
1138+ *     level, getting the data,...)
1139+ *
1140+ *     When returning from the function, the following will be performed by
1141+ *     the RTEMS irq epilogue :
1142+ *
1143+ *     1) masks the interrupts again,
1144+ *     2) restore the original i8259s' interrupt masks
1145+ *     3) switch back on the orinal stack if needed,
1146+ *     4) perform rescheduling when necessary,
1147+ *     5) restore the C scratch registers...
1148+ *     6) restore initial execution flow
1149+ *
1150+ */
1151+int BSP_install_rtems_irq_handler      (const rtems_irq_connect_data*);
1152+int BSP_install_rtems_shared_irq_handler  (const rtems_irq_connect_data*);
1153+
1154+#define BSP_SHARED_HANDLER_SUPPORT      1
1155+
1156+/*
1157+ * function to get the current RTEMS irq handler for ptr->name. It enables to
1158+ * define hanlder chain...
1159+ */
1160+int BSP_get_current_rtems_irq_handler  (rtems_irq_connect_data* ptr);
1161+/*
1162+ * function to get disconnect the RTEMS irq handler for ptr->name.
1163+ * This function checks that the value given is the current one for safety reason.
1164+ * The user can use the previous function to get it.
1165+ */
1166+int BSP_remove_rtems_irq_handler       (const rtems_irq_connect_data*);
1167+
1168+/*
1169+ * ------------------------ RTEMS Global Irq Handler Mngt Routines ----------------
1170+ */
1171+/*
1172+ * (Re) Initialize the RTEMS interrupt management.
1173+ *
1174+ * The result of calling this function will be the same as if each individual
1175+ * handler (config->irqHdlTbl[i].hdl)  different from "config->defaultEntry.hdl"
1176+ * has been individualy connected via
1177+ *     BSP_install_rtems_irq_handler(&config->irqHdlTbl[i])
1178+ * And each handler currently equal to config->defaultEntry.hdl
1179+ * has been previously disconnected via
1180+ *      BSP_remove_rtems_irq_handler (&config->irqHdlTbl[i])
1181+ *
1182+ * This is to say that all information given will be used and not just
1183+ * only the space.
1184+ *
1185+ * CAUTION : the various table address contained in config will be used
1186+ *          directly by the interrupt mangement code in order to save
1187+ *          data size so they must stay valid after the call => they should
1188+ *          not be modified or declared on a stack.
1189+ */
1190+
1191+int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config);
1192+/*
1193+ * (Re) get info on current RTEMS interrupt management.
1194+ */
1195+int BSP_rtems_irq_mngt_get(rtems_irq_global_settings**);
1196+ 
1197+extern void BSP_rtems_irq_mng_init(unsigned cpuId);
1198+extern void BSP_i8259s_init(void);
1199+#endif
1200+
1201+#endif
1202diff -uNr /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/irq/irq_init.c psim/irq/irq_init.c
1203--- /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/irq/irq_init.c  1969-12-31 18:00:00.000000000 -0600
1204+++ psim/irq/irq_init.c 2004-03-01 13:38:04.000000000 -0600
1205@@ -0,0 +1,169 @@
1206+/* irq_init.c
1207+ *
1208+ *  This file contains the implementation of rtems initialization
1209+ *  related to interrupt handling.
1210+ *
1211+ *  CopyRight (C) 1999 valette@crf.canon.fr
1212+ *
1213+ * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com>
1214+ * to make it valid for MVME2300 Motorola boards.
1215+ *
1216+ * Till Straumann <strauman@slac.stanford.edu>, 12/20/2001:
1217+ * Use the new interface to openpic_init
1218+ *
1219+ *  The license and distribution terms for this file may be
1220+ *  found in the file LICENSE in this distribution or at
1221+ *  http://www.rtems.com/license/LICENSE.
1222+ *
1223+ *  irq_init.c,v 1.6.2.5 2003/09/04 18:45:20 joel Exp
1224+ */
1225+
1226+#include <libcpu/io.h>
1227+#include <libcpu/spr.h>
1228+#include <bsp/irq.h>
1229+#include <bsp.h>
1230+#include <libcpu/raw_exception.h>
1231+#include <rtems/bspIo.h>
1232+#if 0
1233+#include <bsp/pci.h>
1234+#include <bsp/residual.h>
1235+#include <bsp/openpic.h>
1236+#include <bsp/motorola.h>
1237+#endif
1238+
1239+
1240+/*
1241+#define SHOW_ISA_PCI_BRIDGE_SETTINGS
1242+*/
1243+
1244+typedef struct {
1245+  unsigned char bus;   /* few chance the PCI/ISA bridge is not on first bus but ... */
1246+  unsigned char device;
1247+  unsigned char function;
1248+} pci_isa_bridge_device;
1249+
1250+pci_isa_bridge_device* via_82c586 = 0;
1251+static pci_isa_bridge_device bridge;
1252+
1253+extern unsigned int external_exception_vector_prolog_code_size[];
1254+extern void external_exception_vector_prolog_code();
1255+extern unsigned int decrementer_exception_vector_prolog_code_size[];
1256+extern void decrementer_exception_vector_prolog_code();
1257+
1258+/*
1259+ * default on/off function
1260+ */
1261+static void nop_func(){}
1262+/*
1263+ * default isOn function
1264+ */
1265+static int not_connected() {return 0;}
1266+/*
1267+ * default possible isOn function
1268+ */
1269+static int connected() {return 1;}
1270+
1271+static rtems_irq_connect_data          rtemsIrq[BSP_IRQ_NUMBER];
1272+static rtems_irq_global_settings       initial_config;
1273+static rtems_irq_connect_data          defaultIrq = {
1274+  /* vectorIdex,        hdl            , on            , off           , isOn */
1275+  0,                    nop_func       , nop_func      , nop_func      , not_connected
1276+};
1277+static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={
1278+  /*
1279+   * actual rpiorities for interrupt :
1280+   *   0   means that only current interrupt is masked
1281+   *   255 means all other interrupts are masked
1282+   */
1283+  /*
1284+   * ISA interrupts.
1285+   * The second entry has a priority of 255 because
1286+   * it is the slave pic entry and is should always remain
1287+   * unmasked.
1288+   */
1289+  0,0,
1290+  255,
1291+  0, 0, 0, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
1292+  /*
1293+   * PCI Interrupts
1294+   */
1295+  8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, /* for raven prio 0 means unactive... */
1296+  /*
1297+   * Processor exceptions handled as interrupts
1298+   */
1299+  0
1300+};
1301+
1302+void VIA_isa_bridge_interrupts_setup(void)
1303+{
1304+  printk("VIA_isa_bridge_interrupts_setup - Shouldn't get here!\n");
1305+  return;
1306+}
1307+
1308+  /*
1309+   * This code assumes the exceptions management setup has already
1310+   * been done. We just need to replace the exceptions that will
1311+   * be handled like interrupt. On mcp750/mpc750 and many PPC processors
1312+   * this means the decrementer exception and the external exception.
1313+   */
1314+void BSP_rtems_irq_mng_init(unsigned cpuId)
1315+{
1316+  rtems_raw_except_connect_data vectorDesc;
1317+  int i;
1318+ 
1319+  /*
1320+   * First initialize the Interrupt management hardware
1321+   */
1322+
1323+  /*
1324+   * Initialize Rtems management interrupt table
1325+   */
1326+    /*
1327+     * re-init the rtemsIrq table
1328+     */
1329+    for (i = 0; i < BSP_IRQ_NUMBER; i++) {
1330+      rtemsIrq[i]      = defaultIrq;
1331+      rtemsIrq[i].name = i;
1332+    }
1333+    /*
1334+     * Init initial Interrupt management config
1335+     */
1336+    initial_config.irqNb       = BSP_IRQ_NUMBER;
1337+    initial_config.defaultEntry = defaultIrq;
1338+    initial_config.irqHdlTbl   = rtemsIrq;
1339+    initial_config.irqBase     = BSP_ASM_IRQ_VECTOR_BASE;
1340+    initial_config.irqPrioTbl  = irqPrioTable;
1341+
1342+    if (!BSP_rtems_irq_mngt_set(&initial_config)) {
1343+      /*
1344+       * put something here that will show the failure...
1345+       */
1346+      BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n");
1347+    }
1348+ 
1349+  /*
1350+   * We must connect the raw irq handler for the two
1351+   * expected interrupt sources : decrementer and external interrupts.
1352+   */
1353+    vectorDesc.exceptIndex     =       ASM_DEC_VECTOR;
1354+    vectorDesc.hdl.vector      =       ASM_DEC_VECTOR;
1355+    vectorDesc.hdl.raw_hdl     =       decrementer_exception_vector_prolog_code;
1356+    vectorDesc.hdl.raw_hdl_size        =       (unsigned) decrementer_exception_vector_prolog_code_size;
1357+    vectorDesc.on              =       nop_func;
1358+    vectorDesc.off             =       nop_func;
1359+    vectorDesc.isOn            =       connected;
1360+    if (!mpc60x_set_exception (&vectorDesc)) {
1361+      BSP_panic("Unable to initialize RTEMS decrementer raw exception\n");
1362+    }
1363+    vectorDesc.exceptIndex     =       ASM_EXT_VECTOR;
1364+    vectorDesc.hdl.vector      =       ASM_EXT_VECTOR;
1365+    vectorDesc.hdl.raw_hdl     =       external_exception_vector_prolog_code;
1366+    vectorDesc.hdl.raw_hdl_size        =       (unsigned) external_exception_vector_prolog_code_size;
1367+    if (!mpc60x_set_exception (&vectorDesc)) {
1368+      BSP_panic("Unable to initialize RTEMS external raw exception\n");
1369+    }
1370+#ifdef TRACE_IRQ_INIT 
1371+    printk("RTEMS IRQ management is now operationnal\n");
1372+#endif
1373+}
1374+
1375diff -uNr /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/irq/Makefile.am psim/irq/Makefile.am
1376--- /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/irq/Makefile.am 1969-12-31 18:00:00.000000000 -0600
1377+++ psim/irq/Makefile.am        2004-03-01 13:38:04.000000000 -0600
1378@@ -0,0 +1,41 @@
1379+##
1380+## Makefile.am,v 1.5 2002/12/17 13:37:41 ralf Exp
1381+##
1382+
1383+
1384+include_bspdir = $(includedir)/bsp
1385+
1386+C_FILES = irq.c irq_init.c
1387+OBJS = $(C_FILES:%.c=$(ARCH)/%.$(OBJEXT))
1388+
1389+include_bsp_HEADERS = irq.h
1390+
1391+S_FILES = irq_asm.S
1392+OBJS += $(S_FILES:%.S=$(ARCH)/%.$(OBJEXT))
1393+
1394+include $(top_srcdir)/../../../../../../automake/compile.am
1395+include $(top_srcdir)/../../../../../../automake/lib.am
1396+
1397+$(PROJECT_INCLUDE)/bsp:
1398+       $(mkinstalldirs) $@
1399+
1400+$(PROJECT_INCLUDE)/bsp/%.h: %.h
1401+       $(INSTALL_DATA) $< $@
1402+
1403+PREINSTALL_FILES = $(PROJECT_INCLUDE)/bsp \
1404+    $(include_bsp_HEADERS:%=$(PROJECT_INCLUDE)/bsp/%)
1405+
1406+#
1407+# (OPTIONAL) Add local stuff here using +=
1408+#
1409+
1410+$(PGM): $(OBJS)
1411+       $(make-rel)
1412+
1413+# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile
1414+
1415+all-local: $(PREINSTALL_FILES) $(ARCH) $(OBJS) $(PGM)
1416+
1417+EXTRA_DIST = irq.c irq.h irq_asm.S irq_init.c
1418+
1419+include $(top_srcdir)/../../../../../../automake/local.am
1420diff -uNr /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/Makefile.am psim/Makefile.am
1421--- /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/Makefile.am     2002-03-27 18:41:49.000000000 -0600
1422+++ psim/Makefile.am    2004-03-01 13:38:04.000000000 -0600
1423@@ -6,7 +6,7 @@
1424
1425# wrapup is the one that actually builds and installs the library
1426#  from the individual .rel files built in other directories
1427-SUBDIRS = include start clock console startup shmsupp timer vectors \
1428+SUBDIRS = include start irq clock console startup shmsupp timer vectors\
1429   @exceptions@ wrapup \
1430   tools
1431
1432diff -uNr /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/start/start.S psim/start/start.S
1433--- /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/start/start.S   2000-08-02 11:30:57.000000000 -0500
1434+++ psim/start/start.S  2004-03-01 13:38:04.000000000 -0600
1435@@ -17,6 +17,9 @@
1436*  $Id: start.S,v 1.3 2000/08/02 16:30:57 joel Exp $
1437*/
1438
1439+#include <asm.h>
1440+#include <rtems/score/cpu.h>
1441+#include <libcpu/io.h>
1442#include "ppc-asm.h"
1443
1444        .file   "startsim.s"
1445@@ -53,9 +56,14 @@
1446.Lptr:
1447        .long .LCTOC1-.Laddr
1448
1449+       .globl  __rtems_entry_point
1450+       .type   __rtems_entry_point,@function
1451+__rtems_entry_point:
1452+#if 1
1453        .globl  _start
1454        .type   _start,@function
1455_start:
1456+#endif
1457        bl      .Laddr                  /* get current address */
1458.Laddr:
1459        mflr    r4                      /* real address of .Laddr */
1460@@ -100,6 +108,7 @@
1461       la       r5,environ@l(r5)        /* environp */
1462        li      r4, 0                   /* argv */
1463        li      r3, 0                   /* argc */
1464+
1465        /* Let her rip */
1466        bl      FUNC_NAME(boot_card)
1467
1468diff -uNr /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/startup/bspstart.c psim/startup/bspstart.c
1469--- /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/startup/bspstart.c      2003-09-04 13:45:12.000000000 -0500
1470+++ psim/startup/bspstart.c     2004-03-01 13:38:04.000000000 -0600
1471@@ -16,11 +16,32 @@
1472
1473#include <string.h>
1474#include <fcntl.h>
1475-
1476#include <bsp.h>
1477#include <rtems/libio.h>
1478#include <rtems/libcsupport.h>
1479#include <rtems/bspIo.h>
1480+#include <libcpu/cpuIdent.h>
1481+#include <libcpu/spr.h>
1482+
1483+SPR_RW(SPRG0)
1484+SPR_RW(SPRG1)
1485+
1486+
1487+extern unsigned long __rtems_end[];
1488+
1489+void  initialize_exceptions(void);
1490+
1491+
1492+/*  On psim, each click of the decrementer register corresponds
1493+ *  to 1 instruction.  By setting this to 100, we are indicating
1494+ *  that we are assuming it can execute 100 instructions per
1495+ *  microsecond.  This corresponds to sustaining 1 instruction
1496+ *  per cycle at 100 Mhz.  Whether this is a good guess or not
1497+ *  is anyone's guess.
1498+ */
1499+
1500+extern int PSIM_INSTRUCTIONS_PER_MICROSECOND;
1501+
1502
1503/*
1504*  The original table from the application and our copy of it with
1505@@ -42,6 +63,15 @@
1506#endif
1507
1508/*
1509+ * PCI Bus Frequency
1510+ */
1511+ unsigned int BSP_bus_frequency;
1512+ /*
1513+  *  * Time base divisior (how many tick for 1 second).
1514+  *   */
1515+ unsigned int BSP_time_base_divisor;
1516+
1517+/*
1518*  Use the shared implementations of the following routines
1519*/
1520
1521@@ -49,6 +79,25 @@
1522void bsp_libc_init( void *, unsigned32, int );
1523
1524/*
1525+ * system init stack and soft ir stack size
1526+ */
1527+#define INIT_STACK_SIZE 0x1000
1528+#define INTR_STACK_SIZE CONFIGURE_INTERRUPT_STACK_MEMORY
1529+
1530+
1531+void BSP_panic(char *s)
1532+{
1533+    printk("%s PANIC %s\n",_RTEMS_version, s);
1534+      __asm__ __volatile ("sc");
1535+}
1536+
1537+void _BSP_Fatal_error(unsigned int v)
1538+{
1539+    printk("%s PANIC ERROR %x\n",_RTEMS_version, v);
1540+      __asm__ __volatile ("sc");
1541+}
1542+
1543+/*
1544*  bsp_pretasking_hook
1545*
1546*  BSP pretasking hook.  Called just before drivers are initialized.
1547@@ -76,6 +125,7 @@
1548
1549}
1550
1551+
1552/*
1553*  bsp_start
1554*
1555@@ -84,17 +134,14 @@
1556
1557void bsp_start( void )
1558{
1559-  unsigned char *work_space_start;
1560-
1561-#if 0
1562-  /*
1563-   * Set MSR to show vectors at 0 XXX
1564+  unsigned char     *work_space_start;
1565+  register unsigned char* intrStack;
1566+   
1567+  /*
1568+   * Note we can not get CPU identification dynamically, so force current_ppc_cpu.
1569  */
1570-  _CPU_MSR_Value( msr_value );
1571-  msr_value &= ~PPC_MSR_EP;
1572-  _CPU_MSR_SET( msr_value );
1573-#endif
1574-
1575+  current_ppc_cpu = PPC_PSIM;
1576+     
1577 /*
1578  * Set up our hooks
1579  * Make sure libc_init is done before drivers initialized so that
1580@@ -118,11 +165,14 @@
1581
1582 Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY;
1583
1584+  BSP_bus_frequency        = (unsigned int)&PSIM_INSTRUCTIONS_PER_MICROSECOND;
1585+  BSP_time_base_divisor    = 1;
1586+     
1587 /*
1588-   *  The monitor likes the exception table to be at 0x0.
1589+   *  The simulator likes the exception table to be at 0xfff00000.
1590  */
1591
1592-  Cpu_table.exceptions_in_RAM = TRUE;
1593+  Cpu_table.exceptions_in_RAM = FALSE;
1594
1595 BSP_Configuration.work_space_size += 1024;
1596
1597@@ -136,4 +186,33 @@
1598
1599 BSP_Configuration.work_space_start = work_space_start;
1600
1601+  /*
1602+   * Initialize the interrupt related settings
1603+   * SPRG1 = software managed IRQ stack
1604+   *
1605+   * This could be done latter (e.g in IRQ_INIT) but it helps to understand
1606+   * some settings below...
1607+   */
1608+  intrStack = ((unsigned char*) __rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE;
1609+
1610+  /* make sure it's properly aligned */
1611+  (unsigned32)intrStack &= ~(CPU_STACK_ALIGNMENT-1);
1612+
1613+  /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */
1614+  *((unsigned32 *)intrStack) = 0;
1615+
1616+  _write_SPRG1((unsigned int)intrStack);
1617+
1618+  /* signal them that we have fixed PR288 - eventually, this should go away */
1619+  _write_SPRG0(PPC_BSP_HAS_FIXED_PR288);
1620+
1621+  /*
1622+   * Initialize default raw exception hanlders. See vectors/vectors_init.c
1623+   */
1624+  initialize_exceptions();
1625+
1626+  /*
1627+   * Initalize RTEMS IRQ system
1628+   */
1629+  BSP_rtems_irq_mng_init(0);
1630}
1631diff -uNr /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/startup/linkcmds psim/startup/linkcmds
1632--- /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/startup/linkcmds        2003-12-16 17:17:19.000000000 -0600
1633+++ psim/startup/linkcmds       2004-03-01 13:38:04.000000000 -0600
1634@@ -16,7 +16,7 @@
1635ENTRY(_start)
1636/* Do we need any of these for elf?
1637  __DYNAMIC = 0;    */
1638-PROVIDE (PSIM_INSTRUCTIONS_PER_MICROSECOND = 100);
1639+PROVIDE (PSIM_INSTRUCTIONS_PER_MICROSECOND = 10000);   /* 100); */
1640PROVIDE (CPU_PPC_CLICKS_PER_MS = 16667);
1641MEMORY
1642 {
1643@@ -26,10 +26,10 @@
1644
1645SECTIONS
1646{
1647-  .vectors 0xFFF00100 :
1648+  .entry_point_section :
1649 {
1650-    *(.vectors)
1651-  } >EPROM
1652+       *(.entry_point_section)
1653+  } > EPROM
1654
1655 /* Read-only sections, merged into text segment: */
1656 /* . = 0x40000 + SIZEOF_HEADERS; */
1657@@ -170,6 +170,7 @@
1658  *(COMMON)
1659 } >RAM
1660 . =  ALIGN(8) + 0x8000;
1661+  __rtems_end = . ;
1662 PROVIDE(__stack = .);
1663 PROVIDE(_end = .);
1664 PROVIDE(end = .);
1665diff -uNr /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/startup/Makefile.am psim/startup/Makefile.am
1666--- /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/startup/Makefile.am     2002-12-16 18:25:35.000000000 -0600
1667+++ psim/startup/Makefile.am    2004-03-01 13:38:04.000000000 -0600
1668@@ -8,7 +8,7 @@
1669PGM = $(ARCH)/startup.rel
1670
1671C_FILES = bspclean.c bsplibc.c bsppost.c bspstart.c bootcard.c main.c sbrk.c \
1672-    setvec.c gnatinstallhandler.c
1673+    gnatinstallhandler.c
1674C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.$(OBJEXT))
1675
1676OBJS = $(C_O_FILES)
1677@@ -38,6 +38,6 @@
1678
1679.PRECIOUS: $(PGM)
1680
1681-EXTRA_DIST = bspclean.c bspstart.c device-tree linkcmds setvec.c
1682+EXTRA_DIST = bspclean.c bspstart.c device-tree linkcmds
1683
1684include $(top_srcdir)/../../../../../../automake/local.am
1685diff -uNr /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/vectors/Makefile.am psim/vectors/Makefile.am
1686--- /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/vectors/Makefile.am     2002-12-16 18:25:35.000000000 -0600
1687+++ psim/vectors/Makefile.am    2004-03-01 14:52:31.000000000 -0600
1688@@ -2,13 +2,17 @@
1689## $Id: Makefile.am,v 1.6 2002/12/17 00:25:35 ralf Exp $
1690##
1691
1692+VPATH = @srcdir@:@srcdir@/../console:@srcdir@/../../shared/vectors
1693
1694-PGM = $(ARCH)/vectors.rel
1695+C_FILES = vectors_init.c
1696+C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.$(OBJEXT))
1697
1698-S_FILES = align_h.S vectors.S
1699+H_FILES = ../../shared/vectors/vectors.h
1700+
1701+S_FILES = vectors.S
1702S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.$(OBJEXT))
1703
1704-OBJS = $(S_O_FILES)
1705+OBJS = $(S_O_FILES) $(C_O_FILES)
1706
1707include $(top_srcdir)/../../../../../../automake/compile.am
1708include $(top_srcdir)/../../../../../../automake/lib.am
1709@@ -20,12 +24,20 @@
1710$(PGM): $(OBJS)
1711        $(make-rel)
1712
1713-# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile
1714+include_bspdir = $(includedir)/bsp
1715+include_bsp_HEADERS = ../../shared/vectors/vectors.h
1716+
1717+$(PROJECT_INCLUDE)/bsp:
1718+       $(mkinstalldirs) $@
1719
1720-all-local: $(ARCH) $(OBJS) $(PGM)
1721+$(PROJECT_INCLUDE)/bsp/vectors.h: ../../shared/vectors/vectors.h
1722+       $(INSTALL_DATA) $< $@
1723
1724-.PRECIOUS: $(PGM)
1725+TMPINSTALL_FILES += $(PROJECT_INCLUDE)
1726+TMPINSTALL_FILES += $(PROJECT_INCLUDE)/bsp
1727+TMPINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h
1728
1729-EXTRA_DIST = README align_h.S vectors.S
1730+all-local: $(ARCH) $(TMPINSTALL_FILES) $(OBJS)
1731
1732+include $(top_srcdir)/../../../../../../automake/force-preinstall.am
1733include $(top_srcdir)/../../../../../../automake/local.am
1734diff -uNr /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/vectors/vectors.S psim/vectors/vectors.S
1735--- /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/vectors/vectors.S       2003-09-04 13:45:13.000000000 -0500
1736+++ psim/vectors/vectors.S      2004-03-01 14:17:39.000000000 -0600
1737@@ -1,18 +1,13 @@
1738-/*  vectors.s  1.1 - 95/12/04
1739- *
1740- *  This file contains the assembly code for the PowerPC
1741- *  interrupt vectors for RTEMS.
1742+/*
1743+ * (c) 1999, Eric Valette valette@crf.canon.fr
1744*
1745- *  COPYRIGHT (c) 1989-1999.
1746- *  On-Line Applications Research Corporation (OAR).
1747*
1748- *  The license and distribution terms for this file may be
1749- *  found in found in the file LICENSE in this distribution or at
1750- *  http://www.rtems.com/license/LICENSE.
1751+ *  This file contains the assembly code for the PowerPC
1752+ *  exception veneers for RTEMS.
1753*
1754*  $Id: vectors.S,v 1.3.4.1 2003/09/04 18:45:13 joel Exp $
1755*/
1756-
1757+       
1758/*
1759*  The issue with this file is getting it loaded at the right place.
1760*  The first vector MUST be at address 0x????0100.
1761@@ -31,93 +26,151 @@
1762*  will usually be 0x0000 or 0x0100.
1763*/
1764
1765-#include <bsp.h>
1766-#include "asm.h"
1767-
1768-#ifndef PPC_VECTOR_FILE_BASE
1769-#error "PPC_VECTOR_FILE_BASE is not defined."
1770-#endif
1771-
1772-       /* Where this file will be loaded */
1773-       .set    file_base, PPC_VECTOR_FILE_BASE
1774-
1775-       /* Offset to store reg 0 */
1776-
1777-       .set    IP_LINK, 0
1778-#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
1779-       .set    IP_0, (IP_LINK + 56)
1780-#else
1781-       .set    IP_0, (IP_LINK + 8)
1782-#endif
1783-       .set    IP_2, (IP_0 + 4)
1784-
1785-       .set    IP_3, (IP_2 + 4)
1786-       .set    IP_4, (IP_3 + 4)
1787-       .set    IP_5, (IP_4 + 4)
1788-       .set    IP_6, (IP_5 + 4)
1789-       
1790-       .set    IP_7, (IP_6 + 4)
1791-       .set    IP_8, (IP_7 + 4)
1792-       .set    IP_9, (IP_8 + 4)
1793-       .set    IP_10, (IP_9 + 4)
1794-       
1795-       .set    IP_11, (IP_10 + 4)
1796-       .set    IP_12, (IP_11 + 4)
1797-       .set    IP_13, (IP_12 + 4)
1798-       .set    IP_28, (IP_13 + 4)
1799-       
1800-       .set    IP_29, (IP_28 + 4)
1801-       .set    IP_30, (IP_29 + 4)
1802-       .set    IP_31, (IP_30 + 4)
1803-       .set    IP_CR, (IP_31 + 4)
1804-       
1805-       .set    IP_CTR, (IP_CR + 4)
1806-       .set    IP_XER, (IP_CTR + 4)
1807-       .set    IP_LR, (IP_XER + 4)
1808-       .set    IP_PC, (IP_LR + 4)
1809-       
1810-       .set    IP_MSR, (IP_PC + 4)
1811-       
1812-       .set    IP_END, (IP_MSR + 16)
1813-
1814-       /* Vector offsets                        */
1815-       .set    begin_vector,0xFFF00000
1816-       .set    crit_vector,0xFFF00100
1817-       .set    mach_vector,0xFFF00200
1818-       .set    prot_vector,0xFFF00300
1819-       .set    ext_vector,0xFFF00500
1820-       .set    align_vector,0xFFF00600
1821-       .set    prog_vector,0xFFF00700
1822-       .set    dec_vector,0xFFF00900
1823-       .set    sys_vector,0xFFF00C00
1824-       .set    pit_vector,0xFFF01000
1825-       .set    fit_vector,0xFFF01010
1826-       .set    wadt_vector,0xFFF01020
1827-       .set    debug_vector,0xFFF02000
1828-
1829-/* Go to the right section */
1830-#if PPC_ASM == PPC_ASM_ELF
1831-       .section .vectors,"awx",@progbits
1832-#elif PPC_ASM == PPC_ASM_XCOFF
1833-       .csect  .text[PR]
1834-#endif
1835-
1836-       PUBLIC_VAR (__vectors)
1837-SYM (__vectors):
1838-       
1839-/* Decrementer interrupt */
1840-       .org    dec_vector - file_base
1841-#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
1842-#if (PPC_HAS_FPU)
1843-       stwu    r1, -(20*4 + 18*8 + IP_END)(r1)
1844-#else
1845-       stwu    r1, -(20*4 + IP_END)(r1)
1846-#endif
1847-#else
1848-       stwu    r1, -(IP_END)(r1)
1849-#endif
1850-       stw     r0, IP_0(r1)
1851+#include <asm.h>
1852+#include <rtems/score/cpu.h>
1853+#include <bsp/vectors.h>
1854+       
1855
1856-       li      r0, PPC_IRQ_DECREMENTER
1857-       b       PROC (_ISR_Handler)
1858+#define SYNC \
1859+       sync; \
1860+       isync
1861+       
1862+       PUBLIC_VAR (__rtems_start)
1863+       .section .entry_point_section,"awx",@progbits
1864+/*
1865+ * Entry point information used by bootloader code
1866+ */
1867+SYM (__rtems_start):           
1868+       .long   __rtems_entry_point
1869
1870+       /*
1871+        * end of special Entry point section
1872+        */     
1873+       .text
1874+       .p2align 5     
1875+               
1876+PUBLIC_VAR(default_exception_vector_code_prolog)
1877+SYM (default_exception_vector_code_prolog):
1878+       /*
1879+        * let room for exception frame
1880+        */
1881+       stwu    r1, - (EXCEPTION_FRAME_END)(r1)
1882+       stw     r3, GPR3_OFFSET(r1)
1883+       /* R2 should never change (EABI: pointer to .sdata2) - we
1884+     * save it nevertheless..
1885+        */
1886+       stw     r2, GPR2_OFFSET(r1)
1887+       mflr    r3
1888+       stw     r3, EXC_LR_OFFSET(r1)
1889+       bl      0f
1890+0:     /*
1891+        * r3 = exception vector entry point
1892+        * (256 * vector number) + few instructions
1893+        */
1894+       mflr    r3
1895+       /*
1896+        * r3 = r3 >> 8 = vector
1897+        */
1898+       srwi    r3,r3,8
1899+       ba      push_normalized_frame
1900+       
1901+       PUBLIC_VAR (default_exception_vector_code_prolog_size)
1902+       
1903+       default_exception_vector_code_prolog_size= . - default_exception_vector_code_prolog
1904+       
1905+       .p2align 5
1906+PUBLIC_VAR (push_normalized_frame)     
1907+SYM (push_normalized_frame):
1908+       stw     r3, EXCEPTION_NUMBER_OFFSET(r1)
1909+       stw     r0, GPR0_OFFSET(r1)
1910+       mfsrr0  r3
1911+       stw     r3, SRR0_FRAME_OFFSET(r1)
1912+       mfsrr1  r3
1913+       stw     r3, SRR1_FRAME_OFFSET(r1)
1914+       /*
1915+        * Save general purpose registers
1916+        * Already saved in prolog : R1, R2, R3, LR.
1917+        * Saved a few line above  : R0
1918+        *
1919+        * Manual says that "stmw" instruction may be slower than
1920+        * series of individual "stw" but who cares about performance
1921+        * for the DEFAULT exception handler?
1922+        */
1923+       stmw    r4, GPR4_OFFSET(r1)     /* save R4->R31 */
1924+
1925+       mfcr    r31
1926+       stw     r31,  EXC_CR_OFFSET(r1)
1927+       mfctr   r30
1928+       stw     r30,  EXC_CTR_OFFSET(r1)
1929+       mfxer   r28
1930+       stw     r28,  EXC_XER_OFFSET(r1)
1931+       mfmsr   r28
1932+       stw     r28,  EXC_MSR_OFFSET(r1)
1933+       mfdar   r28
1934+       stw     r28,  EXC_DAR_OFFSET(r1)
1935+       /*
1936+        * compute SP at exception entry
1937+        */
1938+       addi    r3, r1, EXCEPTION_FRAME_END
1939+       /*
1940+        * store it at the right place
1941+        */
1942+       stw     r3, GPR1_OFFSET(r1)
1943+       /*
1944+        * Enable data and instruction address translation, exception nesting
1945+        */
1946+       mfmsr   r3
1947+       ori     r3,r3, MSR_RI /* | MSR_IR | MSR_DR */
1948+       mtmsr   r3
1949+       SYNC
1950+       
1951+       /*
1952+        * Call C exception handler
1953+        */
1954+       /*
1955+        * store the execption frame address in r3 (first param)
1956+        */
1957+       addi    r3, r1, 0x8
1958+       /*
1959+        * globalExceptHdl(r3)
1960+        */
1961+       addis   r4, 0, globalExceptHdl@ha
1962+       lwz     r5, globalExceptHdl@l(r4)
1963+       mtlr    r5
1964+       blrl
1965+       /*
1966+        * Restore registers status
1967+        */
1968+       lwz     r31,  EXC_CR_OFFSET(r1)
1969+       mtcr    r31
1970+       lwz     r30,  EXC_CTR_OFFSET(r1)
1971+       mtctr   r30
1972+       lwz     r29,  EXC_LR_OFFSET(r1)
1973+       mtlr    r29
1974+       lwz     r28,  EXC_XER_OFFSET(r1)
1975+       mtxer   r28
1976+
1977+       lmw     r4, GPR4_OFFSET(r1)
1978+       lwz     r2, GPR2_OFFSET(r1)
1979+       lwz     r0, GPR0_OFFSET(r1)
1980+
1981+       /*
1982+        * Disable data and instruction translation. Make path non recoverable...
1983+        */
1984+       mfmsr   r3
1985+       xori    r3, r3, MSR_RI | MSR_IR | MSR_DR
1986+       mtmsr   r3
1987+       SYNC
1988+       /*
1989+        * Restore rfi related settings
1990+        */
1991+               
1992+       lwz     r3, SRR1_FRAME_OFFSET(r1)
1993+       mtsrr1  r3
1994+       lwz     r3, SRR0_FRAME_OFFSET(r1)
1995+       mtsrr0  r3
1996+       
1997+       lwz     r3, GPR3_OFFSET(r1)
1998+       addi    r1,r1, EXCEPTION_FRAME_END
1999+       SYNC
2000+       rfi
2001diff -uNr /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/wrapup/Makefile.am psim/wrapup/Makefile.am
2002--- /shorad/tools/rtems-46-jennifer/rtems/c/src/lib/libbsp/powerpc/psim/wrapup/Makefile.am      2002-12-11 03:06:41.000000000 -0600
2003+++ psim/wrapup/Makefile.am     2004-03-01 14:22:41.000000000 -0600
2004@@ -2,25 +2,19 @@
2005## $Id: Makefile.am,v 1.11 2002/12/11 09:06:41 ralf Exp $
2006##
2007
2008-include $(top_srcdir)/../../../../../../automake/compile.am
2009-include $(top_srcdir)/../../../../../../automake/lib.am
2010-
2011-if HAS_MP
2012-GENERIC_MP_REL_PIECES = shmdr
2013-endif
2014-GENERIC_PIECES = $(GENERIC_MP_REL_PIECES)
2015-
2016-if HAS_MP
2017-BSP_MP_O_PIECES = shmsupp
2018-endif
2019-BSP_PIECES = startup clock console timer vectors $(BSP_MP_O_PIECES)
2020+BSP_PIECES = startup clock console irq vectors
2021
2022# bummer; have to use $foreach since % pattern subst rules only replace 1x
2023-OBJS = $(foreach piece, $(BSP_PIECES), $(wildcard ../$(piece)/$(ARCH)/*.$(OBJEXT))) \
2024+OBJS = $(foreach piece, $(BSP_PIECES), ../$(piece)/$(ARCH)/*.$(OBJEXT)) \
2025+    $(wildcard ../../../../libcpu/$(RTEMS_CPU)/shared/*/$(ARCH)/*.$(OBJEXT)) \
2026+    $(wildcard ../../../../libcpu/$(RTEMS_CPU)/mpc6xx/*/$(ARCH)/*.$(OBJEXT)) \
2027   ../@exceptions@/$(ARCH)/rtems-cpu.rel \
2028-    $(foreach piece, $(GENERIC_PIECES), ../../../$(piece)/$(ARCH)/$(piece).rel)
2029+    $(wildcard ../../../../libcpu/$(RTEMS_CPU)/$(RTEMS_CPU_MODEL)/*/$(ARCH)/*.$(OBJEXT))
2030LIB = $(ARCH)/libbsp.a
2031
2032+include $(top_srcdir)/../../../../../../automake/compile.am
2033+include $(top_srcdir)/../../../../../../automake/lib.am
2034+
2035#
2036# (OPTIONAL) Add local stuff here using +=
2037#