RCS file: /usr1/CVS/rtems/cpukit/score/cpu/sparc/cpu_asm.S,v
retrieving revision 1.8.2.1
diff -u -r1.8.2.1 cpu_asm.S
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684 | 684 | call SYM(_Thread_Dispatch), 0 |
685 | 685 | nop |
686 | 686 | |
| 687 | /* |
| 688 | * We invoked _Thread_Dispatch in a state similar to the interrupted |
| 689 | * task. In order to safely be able to tinker with the register |
| 690 | * windows and get the task back to its pre-interrupt state, |
| 691 | * we need to disable interrupts disabled so we can safely tinker |
| 692 | * with the register windowing. In particular, the CWP in the PSR |
| 693 | * is fragile during this period. (See PR578.) |
| 694 | */ |
| 695 | mov 2,%g1 ! syscall (disable interrupts) |
| 696 | ta 0 ! syscall (disable interrupts) |
| 697 | |
687 | 698 | /* |
688 | 699 | * The CWP in place at this point may be different from |
689 | 700 | * that which was in effect at the beginning of the ISR if we |