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Ticket #477: rtems-ss-20030703.patch

File rtems-ss-20030703.patch, 37.6 KB (added by Joel Sherrill, on 12/03/06 at 13:31:12)

rtems-ss-20030703.patch

  • c/src/lib/libbsp/sparc/leon/Makefile.am

    diff -Naur rtems-ss-20030703/c/src/lib/libbsp/sparc/leon/Makefile.am rtems-ss-20030703-jg1/c/src/lib/libbsp/sparc/leon/Makefile.am
    old new  
    11##
    22## Makefile.am,v 1.2 2002/03/28 00:42:50 joel Exp
    33##
    44
    55ACLOCAL_AMFLAGS = -I ../../../../../../aclocal
    66
    77# wrapup is the one that actually builds and installs the library
    88#  from the individual .rel files built in other directories
    9 SUBDIRS = . include start startup gnatsupp console clock timer wrapup tools
     9SUBDIRS = . include start startup gnatsupp console clock timer leon_open_eth \
     10    wrapup tools
    1011
    1112include $(top_srcdir)/../../bsp.am
    1213
  • c/src/lib/libbsp/sparc/leon/configure.ac

    diff -Naur rtems-ss-20030703/c/src/lib/libbsp/sparc/leon/configure.ac rtems-ss-20030703-jg1/c/src/lib/libbsp/sparc/leon/configure.ac
    old new  
    11## Process this file with autoconf to produce a configure script.
    22##
    3 ## configure.ac,v 1.10 2003/03/11 10:43:29 ralf Exp
     3## configure.ac,v 1.9 2003/03/11 10:43:29 ralf Exp
    44
    55AC_PREREQ(2.57)
    66AC_INIT([rtems-c-src-lib-libbsp-sparc-leon],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com])
     
    1414RTEMS_PROG_CC_FOR_TARGET([-ansi -fasm])
    1515RTEMS_CANONICALIZE_TOOLS
    1616
     17RTEMS_CHECK_NETWORKING
     18
     19AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
     20
    1721RTEMS_CONFIG_BUILD_SUBDIRS(tools)
    1822
    1923## bsp-specific options
     
    3640AC_CONFIG_FILES([Makefile
    3741clock/Makefile
    3842console/Makefile
     43leon_open_eth/Makefile
    3944gnatsupp/Makefile
    4045include/Makefile
    4146start/Makefile
  • c/src/lib/libbsp/sparc/leon/console/console.c

    diff -Naur rtems-ss-20030703/c/src/lib/libbsp/sparc/leon/console/console.c rtems-ss-20030703-jg1/c/src/lib/libbsp/sparc/leon/console/console.c
    old new  
    334334   *  Initialize Hardware
    335335   */
    336336 
    337   LEON_REG.UART_Control_1 = LEON_REG_UART_CTRL_RE | LEON_REG_UART_CTRL_TE;
    338   LEON_REG.UART_Control_2 = LEON_REG_UART_CTRL_RE | LEON_REG_UART_CTRL_TE |
     337  LEON_REG.UART_Control_1 |= LEON_REG_UART_CTRL_RE | LEON_REG_UART_CTRL_TE;
     338  LEON_REG.UART_Control_2 |= LEON_REG_UART_CTRL_RE | LEON_REG_UART_CTRL_TE |
    339339        LEON_REG_UART_CTRL_RI;  /* rx irq default enable for remote debugger */
    340340  LEON_REG.UART_Status_1 = 0;
    341341  LEON_REG.UART_Status_2 = 0;
  • c/src/lib/libbsp/sparc/leon/include/bsp.h

    diff -Naur rtems-ss-20030703/c/src/lib/libbsp/sparc/leon/include/bsp.h rtems-ss-20030703-jg1/c/src/lib/libbsp/sparc/leon/include/bsp.h
    old new  
    4545#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2
    4646#define CONFIGURE_INTERRUPT_STACK_MEMORY  (16 * 1024)
    4747
     48/*
     49 * Network driver configuration
     50 */
     51
     52struct rtems_bsdnet_ifconfig;
     53extern int rtems_leon_open_eth_driver_attach (struct rtems_bsdnet_ifconfig *config);
     54#define RTEMS_BSP_NETWORK_DRIVER_NAME   "open_eth1"
     55#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_leon_open_eth_driver_attach
     56
    4857
    4958/*
    5059 *  Define the time limits for RTEMS Test Suite test durations.
  • c/src/lib/libbsp/sparc/leon/leon_open_eth/.cvsignore

    diff -Naur rtems-ss-20030703/c/src/lib/libbsp/sparc/leon/leon_open_eth/.cvsignore rtems-ss-20030703-jg1/c/src/lib/libbsp/sparc/leon/leon_open_eth/.cvsignore
    old new  
     1Makefile
     2Makefile.in
  • c/src/lib/libbsp/sparc/leon/leon_open_eth/Makefile.am

    diff -Naur rtems-ss-20030703/c/src/lib/libbsp/sparc/leon/leon_open_eth/Makefile.am rtems-ss-20030703-jg1/c/src/lib/libbsp/sparc/leon/leon_open_eth/Makefile.am
    old new  
     1##
     2## Makefile.am,v 1.5 2002/12/14 08:17:45 ralf Exp
     3##
     4
     5
     6PGM = $(ARCH)/leon_open_eth.rel
     7
     8C_FILES = leon_open_eth.c
     9C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.$(OBJEXT))
     10
     11OBJS = $(C_O_FILES)
     12
     13include $(top_srcdir)/../../../../../../automake/compile.am
     14include $(top_srcdir)/../../../../../../automake/lib.am
     15
     16#
     17# (OPTIONAL) Add local stuff here using +=
     18#
     19
     20AM_CPPFLAGS += -D__INSIDE_RTEMS_BSD_TCPIP_STACK__
     21
     22$(PGM): $(OBJS)
     23        $(make-rel)
     24
     25# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile
     26
     27if HAS_NETWORKING
     28all-local: $(ARCH) $(OBJS) $(PGM)
     29endif
     30
     31.PRECIOUS: $(PGM)
     32
     33EXTRA_DIST = leon_open_eth.c
     34
     35include $(top_srcdir)/../../../../../../automake/local.am
  • c/src/lib/libbsp/sparc/leon/leon_open_eth/leon_open_eth.c

    diff -Naur rtems-ss-20030703/c/src/lib/libbsp/sparc/leon/leon_open_eth/leon_open_eth.c rtems-ss-20030703-jg1/c/src/lib/libbsp/sparc/leon/leon_open_eth/leon_open_eth.c
    old new  
     1/*
     2 *  LEON2 Opencores Ethernet MAC Configuration Information
     3 *
     4 */
     5
     6
     7#include <bsp.h>
     8#include <libchip/open_eth.h>
     9#if (OPEN_ETH_DEBUG & OPEN_ETH_DEBUG_PRINT_REGISTERS)
     10#include <stdio.h>
     11#endif
     12
     13/*
     14 * Default sizes of transmit and receive descriptor areas
     15 */
     16#define RDA_COUNT     16
     17#define TDA_COUNT     16
     18
     19/*
     20 * Default location of device registers
     21 */
     22#define OPEN_ETH_BASE_ADDRESS 0xb0000000
     23
     24/*
     25 * Default interrupt vector
     26 */
     27#define OPEN_ETH_VECTOR 0x1C
     28
     29open_eth_configuration_t leon_open_eth_configuration = {
     30  OPEN_ETH_BASE_ADDRESS,        /* base address */
     31  OPEN_ETH_VECTOR,              /* vector number */
     32  TDA_COUNT,                 /* number of transmit descriptors */
     33  RDA_COUNT                  /* number of receive descriptors */
     34};
     35
     36int rtems_leon_open_eth_driver_attach(struct rtems_bsdnet_ifconfig *config)
     37{
     38
     39  *(volatile int *) OPEN_ETH_BASE_ADDRESS = 0;
     40  *(volatile int *) OPEN_ETH_BASE_ADDRESS = 0x800;
     41  *(volatile int *) OPEN_ETH_BASE_ADDRESS = 0;
     42  if (rtems_open_eth_driver_attach( config, &leon_open_eth_configuration )) {
     43    LEON_REG.Interrupt_Clear = (1 << (OPEN_ETH_VECTOR - 0x10));
     44    LEON_REG.Interrupt_Mask  |= (1 << (OPEN_ETH_VECTOR - 0x10));
     45  } else
     46    return 0;
     47 
     48}
  • c/src/lib/libbsp/sparc/leon/startup/setvec.c

    diff -Naur rtems-ss-20030703/c/src/lib/libbsp/sparc/leon/startup/setvec.c rtems-ss-20030703-jg1/c/src/lib/libbsp/sparc/leon/startup/setvec.c
    old new  
    6565void _CPU_Thread_Idle_body( void )
    6666{
    6767  while (1) {
    68     LEON_REG.Power_Down = 0;   /* value is irrelevant */
     68    LEON_REG.Power_Down = LEON_REG.Power_Down;   /* make sure on load follows store to power-down reg */
    6969  }
    7070}
    7171
  • c/src/lib/libbsp/sparc/leon/wrapup/Makefile.am

    diff -Naur rtems-ss-20030703/c/src/lib/libbsp/sparc/leon/wrapup/Makefile.am rtems-ss-20030703-jg1/c/src/lib/libbsp/sparc/leon/wrapup/Makefile.am
    old new  
    11##
    2 ## Makefile.am,v 1.10 2002/12/10 11:32:05 ralf Exp
     2## Makefile.am,v 1.12 2002/12/10 11:32:12 ralf Exp
    33##
    44
    5 BSP_PIECES = startup console clock timer gnatsupp $(NETWORK)
     5# We only build the networking device driver if HAS_NETWORKING was defined
     6if HAS_NETWORKING
     7NETWORKING_DRIVER = leon_open_eth
     8endif
     9
     10BSP_PIECES = startup console clock timer gnatsupp $(NETWORKING_DRIVER)
    611# pieces to pick up out of libcpu/sparc
    712CPU_PIECES = cache reg_win syscall
    813
  • c/src/libchip/network/README.open_eth

    diff -Naur rtems-ss-20030703/c/src/libchip/network/README.open_eth rtems-ss-20030703-jg1/c/src/libchip/network/README.open_eth
    old new  
     1
     2Driver for opencores ethernet MAC - README
     3------------------------------------------
     4
     5The device name for the driver is 'open_eth1', the attach
     6function for the leon bsp is rtems_leon_open_eth_driver_attach().
     7
     8No cache flushing is made when a frame is received. On leon,
     9this means that cache snooping must be configured in the
     10vhdl model and enabled by software.
     11
     12TX interrupts are not used and masked in the interrupt mask
     13register.
     14
     15For now, only 10 Mbit/s half-duplex is supported.
     16100 Mbit/s operations does not work reliably, the transmitter
     17locks up or skips frames. Seems to depend on the TX fifo
     18implementation in the opencores MAC. Send a mail to
     19jiri@gaisler.com if you know how to fix this.
     20
     21Tested only on leon, using the GR-PCI-XC2V board @ 40 MHz.
     22Output from ttcp receiving 1 Mbyte file:
     23
     24>>> ttcp -r -s
     25ttcp-r: buflen=8192, nbuf=2048, align=16384/0, port=5001  tcp
     26ttcp-r: socket
     27ttcp-r: accept from 192.168.0.2
     28ttcp-r: 1145339 bytes in 1.18 real seconds = 947.88 KB/sec +++
     29ttcp-r: 792 I/O calls, msec/call = 1.53, calls/sec = 671.19
     30ttcp-r: 0.0user 1.1sys 0:01real 100% 0i+0d 0maxrss 0+0pf 0+0csw
     31************ MBUF STATISTICS ************
     32mbufs:1024    clusters: 128    free: 112
     33drops:   0       waits:   0  drains:   0
     34      free:1007          data:17          header:0           socket:0
     35       pcb:0           rtable:0           htable:0           atable:0
     36    soname:0           soopts:0           ftable:0           rights:0
     37    ifaddr:0          control:0          oobdata:0
     38
     39************ INTERFACE STATISTICS ************
     40***** open_eth1 *****
     41Address:192.168.0.66    Broadcast Address:192.168.0.255
     42Flags: Up Broadcast Running Simplex
     43Send queue limit:50   length:0    Dropped:0
     44         Rx Packets:796           Rx Interrupts:796               Length:0
     45            Bad CRC:0                Overrun:0                   Miss:0
     46      Tx Interrupts:0               Deferred:0        Missed Hearbeat:0
     47         No Carrier:0       Retransmit Limit:0         Late Collision:0
     48           Underrun:0        Raw output wait:0
     49
     50************ IP Statistics ************
     51             total packets received         795
     52 datagrams delivered to upper level         795
     53    total ip packets generated here         401
     54
     55************ TCP Statistics ************
     56               connections accepted           1
     57            connections established           1
     58      conn. closed (includes drops)           1
     59     segs where we tried to get rtt           2
     60                 times we succeeded           2
     61                  delayed acks sent           4
     62                 total packets sent         401
     63              ack-only packets sent           6
     64    window update-only packets sent         394
     65 control (SYN|FIN|RST) packets sent           1
     66             total packets received         795
     67       packets received in sequence         792
     68         bytes received in sequence     1145339
     69                   rcvd ack packets           2
     70           bytes acked by rcvd acks           2
     71 times hdr predict ok for data pkts         791
     72
     73
  • c/src/libchip/network/open_eth.c

    diff -Naur rtems-ss-20030703/c/src/libchip/network/open_eth.c rtems-ss-20030703-jg1/c/src/libchip/network/open_eth.c
    old new  
     1/*
     2 *  RTEMS driver for Opencores Ethernet Controller
     3 *
     4 *  Weakly based on dec21140 rtems driver and open_eth linux driver
     5 *  Written by Jiri Gaisler, Gaisler Research
     6 *
     7 *  The license and distribution terms for this file may be
     8 *  found in found in the file LICENSE in this distribution or at
     9 *  http://www.OARcorp.com/rtems/license.html.
     10 *
     11 */
     12
     13#include <rtems.h>
     14
     15#define OPEN_ETH_SUPPORTED
     16#include <bsp.h>
     17
     18#include <stdlib.h>
     19#include <stdio.h>
     20#include <stdarg.h>
     21#include <rtems/error.h>
     22#include <rtems/rtems_bsdnet.h>
     23#include <libchip/open_eth.h>
     24
     25#include <sys/param.h>
     26#include <sys/mbuf.h>
     27
     28#include <sys/socket.h>
     29#include <sys/sockio.h>
     30#include <net/if.h>
     31#include <netinet/in.h>
     32#include <netinet/if_ether.h>
     33
     34#ifdef malloc
     35#undef malloc
     36#endif
     37#ifdef free
     38#undef free
     39#endif
     40
     41 /*
     42#define OPEN_ETH_DEBUG
     43 */
     44
     45#ifdef CPU_U32_FIX
     46extern void ipalign(struct mbuf *m);
     47#endif
     48
     49/* message descriptor entry */
     50struct MDTX
     51{
     52    char  *buf;
     53};
     54
     55struct MDRX
     56{
     57    struct mbuf *m;
     58};
     59
     60/*
     61 * Number of OCs supported by this driver
     62 */
     63#define NOCDRIVER       1
     64
     65/*
     66 * Receive buffer size -- Allow for a full ethernet packet including CRC
     67 */
     68#define RBUF_SIZE       1536
     69
     70#define ET_MINLEN 64            /* minimum message length */
     71
     72/*
     73 * RTEMS event used by interrupt handler to signal driver tasks.
     74 * This must not be any of the events used by the network task synchronization.
     75 */
     76#define INTERRUPT_EVENT RTEMS_EVENT_1
     77
     78/*
     79 * RTEMS event used to start transmit daemon.
     80 * This must not be the same as INTERRUPT_EVENT.
     81 */
     82#define START_TRANSMIT_EVENT    RTEMS_EVENT_2
     83
     84 /* event to send when tx buffers become available */
     85#define OPEN_ETH_TX_WAIT_EVENT  RTEMS_EVENT_3
     86
     87 /* suspend when all TX descriptors exhausted */
     88 /*
     89#define OETH_SUSPEND_NOTXBUF
     90 */
     91
     92#define OETH_RATE_10MHZ
     93
     94#if (MCLBYTES < RBUF_SIZE)
     95# error "Driver must have MCLBYTES > RBUF_SIZE"
     96#endif
     97
     98/*
     99 * Per-device data
     100 */
     101struct open_eth_softc
     102{
     103
     104    struct arpcom arpcom;
     105
     106    oeth_regs *regs;
     107
     108    int acceptBroadcast;
     109    rtems_id rxDaemonTid;
     110    rtems_id txDaemonTid;
     111
     112    unsigned int tx_ptr;
     113    unsigned int rx_ptr;
     114    unsigned int txbufs;
     115    unsigned int rxbufs;
     116    struct MDTX *txdesc;
     117    struct MDRX *rxdesc;
     118    rtems_vector_number vector;
     119
     120
     121    /*
     122     * Statistics
     123     */
     124    unsigned long rxInterrupts;
     125    unsigned long rxPackets;
     126    unsigned long rxLengthError;
     127    unsigned long rxNonOctet;
     128    unsigned long rxBadCRC;
     129    unsigned long rxOverrun;
     130    unsigned long rxMiss;
     131    unsigned long rxCollision;
     132
     133    unsigned long txInterrupts;
     134    unsigned long txDeferred;
     135    unsigned long txHeartbeat;
     136    unsigned long txLateCollision;
     137    unsigned long txRetryLimit;
     138    unsigned long txUnderrun;
     139    unsigned long txLostCarrier;
     140    unsigned long txRawWait;
     141};
     142
     143static struct open_eth_softc oc;
     144
     145/* OPEN_ETH interrupt handler */
     146
     147static rtems_isr
     148open_eth_interrupt_handler (rtems_vector_number v)
     149{
     150    unsigned32 status;
     151
     152    /* read and clear interrupt cause */
     153
     154    status = oc.regs->int_src;
     155    oc.regs->int_src = status;
     156
     157    /* Frame received? */
     158
     159    if (status & (OETH_INT_RXF | OETH_INT_RXE))
     160      {
     161          oc.rxInterrupts++;
     162          rtems_event_send (oc.rxDaemonTid, INTERRUPT_EVENT);
     163      }
     164#ifdef OETH_SUSPEND_NOTXBUF
     165    if (status & (OETH_INT_MASK_TXB | OETH_INT_MASK_TXC | OETH_INT_MASK_TXE))
     166      {
     167          oc.txInterrupts++;
     168          rtems_event_send (oc.txDaemonTid, OPEN_ETH_TX_WAIT_EVENT);
     169      }
     170#endif
     171      /*
     172#ifdef __leon__
     173      LEON_Clear_interrupt(v-0x10);
     174#endif
     175      */
     176}
     177
     178static unsigned32 read_mii(unsigned32 addr)
     179{
     180    while (oc.regs->miistatus & OETH_MIISTATUS_BUSY) {}
     181    oc.regs->miiaddress = addr << 8;
     182    oc.regs->miicommand = OETH_MIICOMMAND_RSTAT;
     183    while (oc.regs->miistatus & OETH_MIISTATUS_BUSY) {}
     184    if (!(oc.regs->miistatus & OETH_MIISTATUS_NVALID))
     185        return(oc.regs->miirx_data);
     186    else {
     187        printf("open_eth: failed to read mii\n");
     188        return (0);
     189    }
     190}
     191
     192static void write_mii(unsigned32 addr, unsigned32 data)
     193{
     194    while (oc.regs->miistatus & OETH_MIISTATUS_BUSY) {}
     195    oc.regs->miiaddress = addr << 8;
     196    oc.regs->miitx_data = data;
     197    oc.regs->miicommand = OETH_MIICOMMAND_WCTRLDATA;
     198    while (oc.regs->miistatus & OETH_MIISTATUS_BUSY) {}
     199}
     200/*
     201 * Initialize the ethernet hardware
     202 */
     203static void
     204open_eth_initialize_hardware (struct open_eth_softc *sc)
     205{
     206    struct mbuf *m;
     207    int i;
     208    int mii_cr = 0;
     209
     210    oeth_regs *regs;
     211
     212    regs = sc->regs;
     213
     214    /* Reset the controller.  */
     215
     216    regs->ctrlmoder = 0;
     217    regs->moder = OETH_MODER_RST;       /* Reset ON */
     218    regs->moder = 0;                    /* Reset OFF */
     219
     220    /* reset PHY and wait for complettion */
     221    mii_cr = read_mii(0);
     222    mii_cr = 0x3320;
     223#ifdef OETH_RATE_10MHZ
     224    mii_cr = 0;
     225#endif
     226    write_mii(0, mii_cr | 0x8000);
     227    while (read_mii(0) & 0x8000) {}
     228    write_mii(20, 0x1422);
     229#ifdef OETH_RATE_10MHZ
     230    mii_cr = 0;
     231#endif
     232    write_mii(0, mii_cr);
     233    printf("open_eth: driver attached, PHY config : 0x%04x\n", read_mii(0));
     234
     235#ifdef OPEN_ETH_DEBUG
     236    printf("mii_cr: %04x\n", mii_cr);
     237    for (i=0;i<21;i++)
     238      printf("mii_reg %2d : 0x%04x\n", i, read_mii(i));
     239#endif
     240
     241    /* Setting TXBD base to sc->txbufs  */
     242
     243    regs->tx_bd_num = sc->txbufs;
     244
     245    /* Initialize rx/tx pointers.  */
     246
     247    sc->rx_ptr = 0;
     248    sc->tx_ptr = 0;
     249
     250    /* Set min/max packet length */
     251    regs->packet_len = 0x00400600;
     252
     253    /* Set IPGT register to recomended value */
     254    regs->ipgt = 0x00000015;
     255
     256    /* Set IPGR1 register to recomended value */
     257    regs->ipgr1 = 0x0000000c;
     258
     259    /* Set IPGR2 register to recomended value */
     260    regs->ipgr2 = 0x00000012;
     261
     262    /* Set COLLCONF register to recomended value */
     263    regs->collconf = 0x000f003f;
     264
     265    /* initialize TX descriptors */
     266
     267    sc->txdesc = calloc(sc->txbufs, sizeof(*sc->txdesc));
     268    for (i = 0; i < sc->txbufs; i++)
     269      {
     270          sc->regs->xd[i].len_status = OETH_TX_BD_PAD | OETH_TX_BD_CRC;
     271          sc->txdesc[i].buf = calloc(1, OETH_MAXBUF_LEN);
     272#ifdef OPEN_ETH_DEBUG
     273          printf("TXBUF: %08x\n", (int) sc->txdesc[i].buf);
     274#endif
     275      }
     276    sc->regs->xd[sc->txbufs - 1].len_status |= OETH_TX_BD_WRAP;
     277
     278    /* allocate RX buffers */
     279
     280    sc->rxdesc = calloc(sc->rxbufs, sizeof(*sc->rxdesc));
     281    for (i = 0; i < sc->rxbufs; i++)
     282      {
     283
     284          MGETHDR (m, M_WAIT, MT_DATA);
     285          MCLGET (m, M_WAIT);
     286          m->m_pkthdr.rcvif = &sc->arpcom.ac_if;
     287          sc->rxdesc[i].m = m;
     288          sc->regs->xd[i + sc->txbufs].addr = mtod (m, unsigned32 *);
     289          sc->regs->xd[i + sc->txbufs].len_status =
     290              OETH_RX_BD_EMPTY | OETH_RX_BD_IRQ;
     291#ifdef OPEN_ETH_DEBUG
     292          printf("RXBUF: %08x\n", (int) sc->rxdesc[i].m);
     293#endif
     294      }
     295    sc->regs->xd[sc->rxbufs + sc->txbufs - 1].len_status |= OETH_RX_BD_WRAP;
     296
     297
     298    /* set ethernet address.  */
     299
     300    regs->mac_addr1 = sc->arpcom.ac_enaddr[0] << 8 | sc->arpcom.ac_enaddr[1];
     301    regs->mac_addr0 = sc->arpcom.ac_enaddr[2] << 24 | sc->arpcom.ac_enaddr[3] << 16 |
     302        sc->arpcom.ac_enaddr[4] << 8 | sc->arpcom.ac_enaddr[5];
     303
     304    /* install interrupt vector */
     305    set_vector (open_eth_interrupt_handler, sc->vector, 1);
     306
     307    /* clear all pending interrupts */
     308
     309    regs->int_src = 0xffffffff;
     310
     311    /* MAC mode register: PAD, IFG, CRCEN */
     312
     313    regs->moder = OETH_MODER_PAD | OETH_MODER_CRCEN | ((mii_cr & 0x100) << 2);
     314
     315    /* enable interrupts */
     316
     317    regs->int_mask = OETH_INT_MASK_RXF | OETH_INT_MASK_RXE | OETH_INT_MASK_RXC;
     318
     319#ifdef OETH_SUSPEND_NOTXBUF
     320    regs->int_mask |= OETH_INT_MASK_TXB | OETH_INT_MASK_TXC | OETH_INT_MASK_TXE | OETH_INT_BUSY;*/
     321    sc->regs->xd[(sc->txbufs - 1)/2].len_status |= OETH_TX_BD_IRQ;
     322    sc->regs->xd[sc->txbufs - 1].len_status |= OETH_TX_BD_IRQ;
     323#endif
     324
     325    regs->moder |= OETH_MODER_RXEN | OETH_MODER_TXEN;
     326}
     327
     328static void
     329open_eth_rxDaemon (void *arg)
     330{
     331    struct ether_header *eh;
     332    struct open_eth_softc *dp = (struct open_eth_softc *) &oc;
     333    struct ifnet *ifp = &dp->arpcom.ac_if;
     334    struct mbuf *m;
     335    unsigned int len, len_status, bad;
     336    rtems_event_set events;
     337
     338
     339    for (;;)
     340      {
     341
     342          rtems_bsdnet_event_receive (INTERRUPT_EVENT,
     343                                      RTEMS_WAIT | RTEMS_EVENT_ANY,
     344                                      RTEMS_NO_TIMEOUT, &events);
     345#ifdef OPEN_ETH_DEBUG
     346    printf ("r\n");
     347#endif
     348
     349          while (!
     350                 ((len_status =
     351                   dp->regs->xd[dp->rx_ptr+dp->txbufs].len_status) & OETH_RX_BD_EMPTY))
     352            {
     353                bad = 0;
     354                if (len_status & (OETH_RX_BD_TOOLONG | OETH_RX_BD_SHORT))
     355                  {
     356                      dp->rxLengthError++;
     357                      bad = 1;
     358                  }
     359                if (len_status & OETH_RX_BD_DRIBBLE)
     360                  {
     361                      dp->rxNonOctet++;
     362                      bad = 1;
     363                  }
     364                if (len_status & OETH_RX_BD_CRCERR)
     365                  {
     366                      dp->rxBadCRC++;
     367                      bad = 1;
     368                  }
     369                if (len_status & OETH_RX_BD_OVERRUN)
     370                  {
     371                      dp->rxOverrun++;
     372                      bad = 1;
     373                  }
     374                if (len_status & OETH_RX_BD_MISS)
     375                  {
     376                      dp->rxMiss++;
     377                      bad = 1;
     378                  }
     379                if (len_status & OETH_RX_BD_LATECOL)
     380                  {
     381                      dp->rxCollision++;
     382                      bad = 1;
     383                  }
     384
     385                if (!bad)
     386                  {
     387                      /* pass on the packet in the receive buffer */
     388                      len = len_status >> 16;
     389                      m = (struct mbuf *) (dp->rxdesc[dp->rx_ptr].m);
     390                      m->m_len = m->m_pkthdr.len =
     391                          len - sizeof (struct ether_header);
     392                      eh = mtod (m, struct ether_header *);
     393                      m->m_data += sizeof (struct ether_header);
     394#ifdef CPU_U32_FIX
     395                      ipalign(m);       /* Align packet on 32-bit boundary */
     396#endif
     397
     398                      ether_input (ifp, eh, m);
     399
     400                      /* get a new mbuf */
     401                      MGETHDR (m, M_WAIT, MT_DATA);
     402                      MCLGET (m, M_WAIT);
     403                      m->m_pkthdr.rcvif = ifp;
     404                      dp->rxdesc[dp->rx_ptr].m = m;
     405                      dp->regs->xd[dp->rx_ptr + dp->txbufs].addr =
     406                          (unsigned32 *) mtod (m, void *);
     407                      dp->rxPackets++;
     408                  }
     409
     410                dp->regs->xd[dp->rx_ptr+dp->txbufs].len_status =
     411                  (dp->regs->xd[dp->rx_ptr+dp->txbufs].len_status &
     412                    ~OETH_TX_BD_STATS) | OETH_TX_BD_READY;
     413                dp->rx_ptr = (dp->rx_ptr + 1) % dp->rxbufs;
     414            }
     415      }
     416}
     417
     418static int inside = 0;
     419static void
     420sendpacket (struct ifnet *ifp, struct mbuf *m)
     421{
     422    struct open_eth_softc *dp = ifp->if_softc;
     423    unsigned char *temp;
     424    struct mbuf *n;
     425    unsigned int len, len_status;
     426
     427    if (inside) printf ("error: sendpacket re-entered!!\n");
     428    inside = 1;
     429    /*
     430     * Waiting for Transmitter ready
     431     */
     432    n = m;
     433
     434    while (dp->regs->xd[dp->tx_ptr].len_status & OETH_TX_BD_READY)
     435      {
     436#ifdef OETH_SUSPEND_NOTXBUF
     437          rtems_event_set events;
     438          rtems_bsdnet_event_receive (OPEN_ETH_TX_WAIT_EVENT,
     439                                      RTEMS_WAIT | RTEMS_EVENT_ANY,
     440                                      TOD_MILLISECONDS_TO_TICKS(500), &events);
     441#endif
     442      }
     443
     444    len = 0;
     445    temp = (unsigned char *) dp->txdesc[dp->tx_ptr].buf;
     446    dp->regs->xd[dp->tx_ptr].addr = (unsigned32 *) temp;
     447
     448#ifdef OPEN_ETH_DEBUG
     449    printf("TXD: 0x%08x\n", (int) m->m_data);
     450#endif
     451    for (;;)
     452        {
     453#ifdef OPEN_ETH_DEBUG
     454          int i;
     455          printf("MBUF: 0x%08x : ", (int) m->m_data);
     456          for (i=0;i<m->m_len;i++)
     457            printf("%x%x", (m->m_data[i] >> 4) & 0x0ff, m->m_data[i] & 0x0ff);
     458          printf("\n");
     459#endif
     460          len += m->m_len;
     461          if (len <= RBUF_SIZE)
     462            memcpy ((void *) temp, (char *) m->m_data, m->m_len);
     463          temp += m->m_len;
     464          if ((m = m->m_next) == NULL)
     465              break;
     466        }
     467
     468    m_freem (n);
     469
     470    /* don't send long packets */
     471
     472    if (len <= RBUF_SIZE) {
     473
     474     /* Clear all of the status flags.  */
     475     len_status = dp->regs->xd[dp->tx_ptr].len_status & ~OETH_TX_BD_STATS;
     476
     477     /* If the frame is short, tell CPM to pad it.  */
     478     if (len < ET_MINLEN) {
     479        len_status |= OETH_TX_BD_PAD;
     480        len = ET_MINLEN;
     481     }
     482     else
     483        len_status &= ~OETH_TX_BD_PAD;
     484
     485      /* write buffer descriptor length and status */
     486      len_status |= (len << 16) | (OETH_TX_BD_READY | OETH_TX_BD_CRC);
     487      dp->regs->xd[dp->tx_ptr].len_status = len_status;
     488      dp->tx_ptr = (dp->tx_ptr + 1) % dp->txbufs;
     489
     490    }
     491    inside = 0;
     492}
     493
     494/*
     495 * Driver transmit daemon
     496 */
     497void
     498open_eth_txDaemon (void *arg)
     499{
     500    struct open_eth_softc *sc = (struct open_eth_softc *) arg;
     501    struct ifnet *ifp = &sc->arpcom.ac_if;
     502    struct mbuf *m;
     503    rtems_event_set events;
     504
     505    for (;;)
     506      {
     507          /*
     508           * Wait for packet
     509           */
     510
     511          rtems_bsdnet_event_receive (START_TRANSMIT_EVENT,
     512                                      RTEMS_EVENT_ANY | RTEMS_WAIT,
     513                                      RTEMS_NO_TIMEOUT, &events);
     514#ifdef OPEN_ETH_DEBUG
     515    printf ("t\n");
     516#endif
     517
     518          /*
     519           * Send packets till queue is empty
     520           */
     521          for (;;)
     522            {
     523                /*
     524                 * Get the next mbuf chain to transmit.
     525                 */
     526                IF_DEQUEUE (&ifp->if_snd, m);
     527                if (!m)
     528                    break;
     529                sendpacket (ifp, m);
     530            }
     531          ifp->if_flags &= ~IFF_OACTIVE;
     532      }
     533}
     534
     535
     536static void
     537open_eth_start (struct ifnet *ifp)
     538{
     539    struct open_eth_softc *sc = ifp->if_softc;
     540
     541    rtems_event_send (sc->txDaemonTid, START_TRANSMIT_EVENT);
     542    ifp->if_flags |= IFF_OACTIVE;
     543}
     544
     545/*
     546 * Initialize and start the device
     547 */
     548static void
     549open_eth_init (void *arg)
     550{
     551    struct open_eth_softc *sc = arg;
     552    struct ifnet *ifp = &sc->arpcom.ac_if;
     553
     554    if (sc->txDaemonTid == 0)
     555      {
     556
     557          /*
     558           * Set up OPEN_ETH hardware
     559           */
     560          open_eth_initialize_hardware (sc);
     561
     562          /*
     563           * Start driver tasks
     564           */
     565          sc->rxDaemonTid = rtems_bsdnet_newproc ("DCrx", 4096,
     566                                                  open_eth_rxDaemon, sc);
     567          sc->txDaemonTid = rtems_bsdnet_newproc ("DCtx", 4096,
     568                                                  open_eth_txDaemon, sc);
     569      }
     570
     571    /*
     572     * Tell the world that we're running.
     573     */
     574    ifp->if_flags |= IFF_RUNNING;
     575
     576}
     577
     578/*
     579 * Stop the device
     580 */
     581static void
     582open_eth_stop (struct open_eth_softc *sc)
     583{
     584    struct ifnet *ifp = &sc->arpcom.ac_if;
     585
     586    ifp->if_flags &= ~IFF_RUNNING;
     587
     588    sc->regs->moder = 0;                /* RX/TX OFF */
     589    sc->regs->moder = OETH_MODER_RST;   /* Reset ON */
     590    sc->regs->moder = 0;                /* Reset OFF */
     591}
     592
     593
     594/*
     595 * Show interface statistics
     596 */
     597static void
     598open_eth_stats (struct open_eth_softc *sc)
     599{
     600    printf ("         Rx Packets:%-8lu", sc->rxPackets);
     601    printf ("      Rx Interrupts:%-8lu", sc->rxInterrupts);
     602    printf ("          Length:%-8lu", sc->rxLengthError);
     603    printf ("       Non-octet:%-8lu\n", sc->rxNonOctet);
     604    printf ("            Bad CRC:%-8lu", sc->rxBadCRC);
     605    printf ("         Overrun:%-8lu", sc->rxOverrun);
     606    printf ("            Miss:%-8lu", sc->rxMiss);
     607    printf ("       Collision:%-8lu\n", sc->rxCollision);
     608
     609    printf ("      Tx Interrupts:%-8lu", sc->txInterrupts);
     610    printf ("        Deferred:%-8lu", sc->txDeferred);
     611    printf (" Missed Hearbeat:%-8lu\n", sc->txHeartbeat);
     612    printf ("         No Carrier:%-8lu", sc->txLostCarrier);
     613    printf ("Retransmit Limit:%-8lu", sc->txRetryLimit);
     614    printf ("  Late Collision:%-8lu\n", sc->txLateCollision);
     615    printf ("           Underrun:%-8lu", sc->txUnderrun);
     616    printf (" Raw output wait:%-8lu\n", sc->txRawWait);
     617}
     618
     619/*
     620 * Driver ioctl handler
     621 */
     622static int
     623open_eth_ioctl (struct ifnet *ifp, int command, caddr_t data)
     624{
     625    struct open_eth_softc *sc = ifp->if_softc;
     626    int error = 0;
     627
     628    switch (command)
     629      {
     630      case SIOCGIFADDR:
     631      case SIOCSIFADDR:
     632          ether_ioctl (ifp, command, data);
     633          break;
     634
     635      case SIOCSIFFLAGS:
     636          switch (ifp->if_flags & (IFF_UP | IFF_RUNNING))
     637            {
     638            case IFF_RUNNING:
     639                open_eth_stop (sc);
     640                break;
     641
     642            case IFF_UP:
     643                open_eth_init (sc);
     644                break;
     645
     646            case IFF_UP | IFF_RUNNING:
     647                open_eth_stop (sc);
     648                open_eth_init (sc);
     649                break;
     650
     651            default:
     652                break;
     653            }
     654          break;
     655
     656      case SIO_RTEMS_SHOW_STATS:
     657          open_eth_stats (sc);
     658          break;
     659
     660          /*
     661           * FIXME: All sorts of multicast commands need to be added here!
     662           */
     663      default:
     664          error = EINVAL;
     665          break;
     666      }
     667
     668    return error;
     669}
     670
     671/*
     672 * Attach an OPEN_ETH driver to the system
     673 */
     674int
     675rtems_open_eth_driver_attach (struct rtems_bsdnet_ifconfig *config,
     676                              open_eth_configuration_t * chip)
     677{
     678    struct open_eth_softc *sc;
     679    struct ifnet *ifp;
     680    int mtu;
     681    int unitNumber;
     682    char *unitName;
     683
     684      /* parse driver name */
     685    if ((unitNumber = rtems_bsdnet_parse_driver_name (config, &unitName)) < 0)
     686        return 0;
     687
     688    sc = &oc;
     689    ifp = &sc->arpcom.ac_if;
     690    memset (sc, 0, sizeof (*sc));
     691
     692    if (config->hardware_address)
     693      {
     694          memcpy (sc->arpcom.ac_enaddr, config->hardware_address,
     695                  ETHER_ADDR_LEN);
     696      }
     697    else
     698      {
     699          memset (sc->arpcom.ac_enaddr, 0x08, ETHER_ADDR_LEN);
     700      }
     701
     702    if (config->mtu)
     703        mtu = config->mtu;
     704    else
     705        mtu = ETHERMTU;
     706
     707    sc->acceptBroadcast = !config->ignore_broadcast;
     708    sc->regs = (void *) chip->base_address;
     709    sc->vector = chip->vector;
     710    sc->txbufs = chip->txd_count;
     711    sc->rxbufs = chip->rxd_count;
     712
     713
     714    /*
     715     * Set up network interface values
     716     */
     717    ifp->if_softc = sc;
     718    ifp->if_unit = unitNumber;
     719    ifp->if_name = unitName;
     720    ifp->if_mtu = mtu;
     721    ifp->if_init = open_eth_init;
     722    ifp->if_ioctl = open_eth_ioctl;
     723    ifp->if_start = open_eth_start;
     724    ifp->if_output = ether_output;
     725    ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX;
     726    if (ifp->if_snd.ifq_maxlen == 0)
     727        ifp->if_snd.ifq_maxlen = ifqmaxlen;
     728
     729    /*
     730     * Attach the interface
     731     */
     732    if_attach (ifp);
     733    ether_ifattach (ifp);
     734
     735#ifdef OPEN_ETH_DEBUG
     736    printf ("OPEN_ETH : driver has been attached\n");
     737#endif
     738    return 1;
     739};
  • c/src/libchip/network/open_eth.h

    diff -Naur rtems-ss-20030703/c/src/libchip/network/open_eth.h rtems-ss-20030703-jg1/c/src/libchip/network/open_eth.h
    old new  
     1/* Opencores ethernet MAC driver */
     2/* adapted from linux driver by Jiri Gaisler */
     3
     4#ifndef _OPEN_ETH_
     5#define _OPEN_ETH_
     6
     7
     8/* Configuration Information */
     9
     10typedef struct {
     11  unsigned32              base_address;
     12  unsigned32              vector;
     13  unsigned32              txd_count;
     14  unsigned32              rxd_count;
     15} open_eth_configuration_t;
     16
     17
     18/* Ethernet buffer descriptor */
     19
     20typedef struct _oeth_rxtxdesc {
     21    volatile unsigned32 len_status; /* Length and status */
     22    volatile unsigned32 *addr;      /* Buffer pointer */
     23} oeth_rxtxdesc;
     24
     25/* Ethernet configuration registers */
     26
     27typedef struct _oeth_regs {
     28    volatile unsigned32 moder;       /* Mode Register */
     29    volatile unsigned32 int_src;     /* Interrupt Source Register */
     30    volatile unsigned32 int_mask;    /* Interrupt Mask Register */
     31    volatile unsigned32 ipgt;        /* Back to Bak Inter Packet Gap Register */
     32    volatile unsigned32 ipgr1;       /* Non Back to Back Inter Packet Gap Register 1 */
     33    volatile unsigned32 ipgr2;       /* Non Back to Back Inter Packet Gap Register 2 */
     34    volatile unsigned32 packet_len;  /* Packet Length Register (min. and max.) */
     35    volatile unsigned32 collconf;    /* Collision and Retry Configuration Register */
     36    volatile unsigned32 tx_bd_num;   /* Transmit Buffer Descriptor Number Register */
     37    volatile unsigned32 ctrlmoder;   /* Control Module Mode Register */
     38    volatile unsigned32 miimoder;    /* MII Mode Register */
     39    volatile unsigned32 miicommand;  /* MII Command Register */
     40    volatile unsigned32 miiaddress;  /* MII Address Register */
     41    volatile unsigned32 miitx_data;  /* MII Transmit Data Register */
     42    volatile unsigned32 miirx_data;  /* MII Receive Data Register */
     43    volatile unsigned32 miistatus;   /* MII Status Register */
     44    volatile unsigned32 mac_addr0;   /* MAC Individual Address Register 0 */
     45    volatile unsigned32 mac_addr1;   /* MAC Individual Address Register 1 */
     46    volatile unsigned32 hash_addr0;  /* Hash Register 0 */
     47    volatile unsigned32 hash_addr1;  /* Hash Register 1 */
     48    volatile unsigned32 txctrl;      /* Transmitter control register */
     49    unsigned32 empty[235];           /* Unused space */
     50    oeth_rxtxdesc xd[128];           /* TX & RX descriptors */
     51} oeth_regs;
     52
     53#define OETH_TOTAL_BD           128
     54#define OETH_MAXBUF_LEN         0x610
     55                               
     56/* Tx BD */                     
     57#define OETH_TX_BD_READY        0x8000 /* Tx BD Ready */
     58#define OETH_TX_BD_IRQ          0x4000 /* Tx BD IRQ Enable */
     59#define OETH_TX_BD_WRAP         0x2000 /* Tx BD Wrap (last BD) */
     60#define OETH_TX_BD_PAD          0x1000 /* Tx BD Pad Enable */
     61#define OETH_TX_BD_CRC          0x0800 /* Tx BD CRC Enable */
     62                               
     63#define OETH_TX_BD_UNDERRUN     0x0100 /* Tx BD Underrun Status */
     64#define OETH_TX_BD_RETRY        0x00F0 /* Tx BD Retry Status */
     65#define OETH_TX_BD_RETLIM       0x0008 /* Tx BD Retransmission Limit Status */
     66#define OETH_TX_BD_LATECOL      0x0004 /* Tx BD Late Collision Status */
     67#define OETH_TX_BD_DEFER        0x0002 /* Tx BD Defer Status */
     68#define OETH_TX_BD_CARRIER      0x0001 /* Tx BD Carrier Sense Lost Status */
     69#define OETH_TX_BD_STATS        (OETH_TX_BD_UNDERRUN            | \
     70                                OETH_TX_BD_RETRY                | \
     71                                OETH_TX_BD_RETLIM               | \
     72                                OETH_TX_BD_LATECOL              | \
     73                                OETH_TX_BD_DEFER                | \
     74                                OETH_TX_BD_CARRIER)
     75                               
     76/* Rx BD */                     
     77#define OETH_RX_BD_EMPTY        0x8000 /* Rx BD Empty */
     78#define OETH_RX_BD_IRQ          0x4000 /* Rx BD IRQ Enable */
     79#define OETH_RX_BD_WRAP         0x2000 /* Rx BD Wrap (last BD) */
     80                               
     81#define OETH_RX_BD_MISS         0x0080 /* Rx BD Miss Status */
     82#define OETH_RX_BD_OVERRUN      0x0040 /* Rx BD Overrun Status */
     83#define OETH_RX_BD_INVSIMB      0x0020 /* Rx BD Invalid Symbol Status */
     84#define OETH_RX_BD_DRIBBLE      0x0010 /* Rx BD Dribble Nibble Status */
     85#define OETH_RX_BD_TOOLONG      0x0008 /* Rx BD Too Long Status */
     86#define OETH_RX_BD_SHORT        0x0004 /* Rx BD Too Short Frame Status */
     87#define OETH_RX_BD_CRCERR       0x0002 /* Rx BD CRC Error Status */
     88#define OETH_RX_BD_LATECOL      0x0001 /* Rx BD Late Collision Status */
     89#define OETH_RX_BD_STATS        (OETH_RX_BD_MISS                | \
     90                                OETH_RX_BD_OVERRUN              | \
     91                                OETH_RX_BD_INVSIMB              | \
     92                                OETH_RX_BD_DRIBBLE              | \
     93                                OETH_RX_BD_TOOLONG              | \
     94                                OETH_RX_BD_SHORT                | \
     95                                OETH_RX_BD_CRCERR               | \
     96                                OETH_RX_BD_LATECOL)
     97
     98/* MODER Register */
     99#define OETH_MODER_RXEN         0x00000001 /* Receive Enable  */
     100#define OETH_MODER_TXEN         0x00000002 /* Transmit Enable */
     101#define OETH_MODER_NOPRE        0x00000004 /* No Preamble  */
     102#define OETH_MODER_BRO          0x00000008 /* Reject Broadcast */
     103#define OETH_MODER_IAM          0x00000010 /* Use Individual Hash */
     104#define OETH_MODER_PRO          0x00000020 /* Promiscuous (receive all) */
     105#define OETH_MODER_IFG          0x00000040 /* Min. IFG not required */
     106#define OETH_MODER_LOOPBCK      0x00000080 /* Loop Back */
     107#define OETH_MODER_NOBCKOF      0x00000100 /* No Backoff */
     108#define OETH_MODER_EXDFREN      0x00000200 /* Excess Defer */
     109#define OETH_MODER_FULLD        0x00000400 /* Full Duplex */
     110#define OETH_MODER_RST          0x00000800 /* Reset MAC */
     111#define OETH_MODER_DLYCRCEN     0x00001000 /* Delayed CRC Enable */
     112#define OETH_MODER_CRCEN        0x00002000 /* CRC Enable */
     113#define OETH_MODER_HUGEN        0x00004000 /* Huge Enable */
     114#define OETH_MODER_PAD          0x00008000 /* Pad Enable */
     115#define OETH_MODER_RECSMALL     0x00010000 /* Receive Small */
     116 
     117/* Interrupt Source Register */
     118#define OETH_INT_TXB            0x00000001 /* Transmit Buffer IRQ */
     119#define OETH_INT_TXE            0x00000002 /* Transmit Error IRQ */
     120#define OETH_INT_RXF            0x00000004 /* Receive Frame IRQ */
     121#define OETH_INT_RXE            0x00000008 /* Receive Error IRQ */
     122#define OETH_INT_BUSY           0x00000010 /* Busy IRQ */
     123#define OETH_INT_TXC            0x00000020 /* Transmit Control Frame IRQ */
     124#define OETH_INT_RXC            0x00000040 /* Received Control Frame IRQ */
     125
     126/* Interrupt Mask Register */
     127#define OETH_INT_MASK_TXB       0x00000001 /* Transmit Buffer IRQ Mask */
     128#define OETH_INT_MASK_TXE       0x00000002 /* Transmit Error IRQ Mask */
     129#define OETH_INT_MASK_RXF       0x00000004 /* Receive Frame IRQ Mask */
     130#define OETH_INT_MASK_RXE       0x00000008 /* Receive Error IRQ Mask */
     131#define OETH_INT_MASK_BUSY      0x00000010 /* Busy IRQ Mask */
     132#define OETH_INT_MASK_TXC       0x00000020 /* Transmit Control Frame IRQ Mask */
     133#define OETH_INT_MASK_RXC       0x00000040 /* Received Control Frame IRQ Mask */
     134 
     135/* Control Module Mode Register */
     136#define OETH_CTRLMODER_PASSALL  0x00000001 /* Pass Control Frames */
     137#define OETH_CTRLMODER_RXFLOW   0x00000002 /* Receive Control Flow Enable */
     138#define OETH_CTRLMODER_TXFLOW   0x00000004 /* Transmit Control Flow Enable */
     139                               
     140/* MII Mode Register */       
     141#define OETH_MIIMODER_CLKDIV    0x000000FF /* Clock Divider */
     142#define OETH_MIIMODER_NOPRE     0x00000100 /* No Preamble */
     143#define OETH_MIIMODER_RST       0x00000200 /* MIIM Reset */
     144 
     145/* MII Command Register */
     146#define OETH_MIICOMMAND_SCANSTAT  0x00000001 /* Scan Status */
     147#define OETH_MIICOMMAND_RSTAT     0x00000002 /* Read Status */
     148#define OETH_MIICOMMAND_WCTRLDATA 0x00000004 /* Write Control Data */
     149 
     150/* MII Address Register */
     151#define OETH_MIIADDRESS_FIAD    0x0000001F /* PHY Address */
     152#define OETH_MIIADDRESS_RGAD    0x00001F00 /* RGAD Address */
     153 
     154/* MII Status Register */
     155#define OETH_MIISTATUS_LINKFAIL 0x00000001 /* Link Fail */
     156#define OETH_MIISTATUS_BUSY     0x00000002 /* MII Busy */
     157#define OETH_MIISTATUS_NVALID   0x00000004 /* Data in MII Status Register is invalid */
     158
     159/* Attatch routine */
     160
     161int rtems_open_eth_driver_attach (
     162    struct rtems_bsdnet_ifconfig *config,
     163    open_eth_configuration_t *chip
     164);
     165
     166/*
     167#ifdef CPU_U32_FIX
     168void ipalign(struct mbuf *m);
     169#endif
     170
     171*/
     172#endif /* _OPEN_ETH_ */
     173