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diff --git a/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h b/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
index f7017b7688..06960692c5 100644
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l2c_310_invalidate_1_line( const void *d_addr ) |
945 | 945 | static inline void |
946 | 946 | l2c_310_invalidate_range( const void* d_addr, const size_t n_bytes ) |
947 | 947 | { |
948 | | /* Back starting address up to start of a line and invalidate until ADDR_LAST */ |
949 | | uint32_t adx = (uint32_t)d_addr |
950 | | & ~L2C_310_DATA_LINE_MASK; |
951 | | const uint32_t ADDR_LAST = |
952 | | (uint32_t)( (size_t)d_addr + n_bytes - 1 ); |
953 | | uint32_t block_end = |
954 | | L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES ); |
| 948 | uint32_t adx = (uint32_t)d_addr; |
| 949 | uint32_t end = |
| 950 | (uint32_t)( (size_t)d_addr + n_bytes ); |
955 | 951 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
956 | 952 | |
957 | 953 | if ( n_bytes == 0 ) { |
958 | 954 | return; |
959 | 955 | } |
960 | 956 | |
961 | | for (; |
962 | | adx <= ADDR_LAST; |
963 | | adx = block_end + 1, |
964 | | block_end = L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES )) { |
| 957 | if ( adx & L2C_310_DATA_LINE_MASK ) { |
| 958 | /* flush start line in case of misalignment */ |
| 959 | adx &= ~L2C_310_DATA_LINE_MASK; |
| 960 | l2c_310_flush_1_line( l2cc, adx ); |
| 961 | adx += CPU_DATA_CACHE_ALIGNMENT; |
| 962 | } |
| 963 | |
| 964 | if ( end & L2C_310_DATA_LINE_MASK ) { |
| 965 | /* flush end line in case of misalignment */ |
| 966 | end &= ~L2C_310_DATA_LINE_MASK; |
| 967 | l2c_310_flush_1_line( l2cc, end ); |
| 968 | } |
| 969 | |
| 970 | while (adx < end) { |
| 971 | uint32_t block_end = L2C_310_MIN( end, adx + L2C_310_MAX_LOCKING_BYTES ); |
965 | 972 | rtems_interrupt_lock_context lock_context; |
966 | 973 | |
967 | 974 | rtems_interrupt_lock_acquire( &l2c_310_lock, &lock_context ); |
968 | 975 | |
969 | | for (; adx <= block_end; adx += CPU_DATA_CACHE_ALIGNMENT ) { |
| 976 | for (; adx < block_end; adx += CPU_DATA_CACHE_ALIGNMENT ) { |
970 | 977 | /* Invalidate L2 cache line */ |
971 | 978 | l2cc->inv_pa = adx; |
972 | 979 | } |
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diff --git a/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h b/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h
index 9caa2685bc..f2927a2766 100644
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static inline void arm_cache_l1_invalidate_data_range( |
268 | 268 | ) |
269 | 269 | { |
270 | 270 | if ( n_bytes != 0 ) { |
271 | | uint32_t adx = (uint32_t) d_addr |
272 | | & ~ARM_CACHE_L1_DATA_LINE_MASK; |
273 | | const uint32_t end = |
274 | | (uint32_t)( (size_t)d_addr + n_bytes -1); |
| 271 | uint32_t adx = (uint32_t) d_addr; |
| 272 | uint32_t end = |
| 273 | (uint32_t)( (size_t)d_addr + n_bytes ); |
275 | 274 | |
276 | 275 | arm_cache_l1_errata_764369_handler(); |
277 | 276 | |
278 | | /* Back starting address up to start of a line and invalidate until end */ |
279 | | for (; |
280 | | adx <= end; |
281 | | adx += ARM_CACHE_L1_CPU_DATA_ALIGNMENT ) { |
282 | | /* Invalidate the Instruction cache line */ |
283 | | arm_cp15_data_cache_invalidate_line( (void*)adx ); |
| 277 | if (adx & ARM_CACHE_L1_DATA_LINE_MASK) { |
| 278 | /* flush start line in case of misalignment */ |
| 279 | adx &= ~ARM_CACHE_L1_DATA_LINE_MASK; |
| 280 | arm_cp15_data_cache_clean_and_invalidate_line( (void*)adx ); |
| 281 | adx += ARM_CACHE_L1_CPU_DATA_ALIGNMENT; |
284 | 282 | } |
| 283 | |
| 284 | if (end & ARM_CACHE_L1_DATA_LINE_MASK) { |
| 285 | /* flush end line in case of misalignment */ |
| 286 | end &= ~ARM_CACHE_L1_DATA_LINE_MASK; |
| 287 | arm_cp15_data_cache_clean_and_invalidate_line( (void*)end ); |
| 288 | } |
| 289 | |
| 290 | while (adx < end) { |
| 291 | /* Invalidate the Data cache line */ |
| 292 | arm_cp15_data_cache_invalidate_line( (void*)adx ); |
| 293 | adx += ARM_CACHE_L1_CPU_DATA_ALIGNMENT; |
| 294 | } |
| 295 | |
285 | 296 | /* Wait for L1 invalidate to complete */ |
286 | 297 | _ARM_Data_synchronization_barrier(); |
287 | 298 | } |
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