1 | This patch implements PR288 for the following 'new exception processing' |
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2 | PPC BSPs: |
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3 | - eth_comm |
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4 | - mbx8xx |
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5 | - powerpc/shared (including motorola_powerpc) |
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6 | |
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7 | Until now, those BSPs maintained their own version of _ISR_Nest_level |
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8 | in a register (SPRG0). This is _illegal_ because the system relies |
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9 | on _ISR_Nest_level to (e.g. for watchdog timers). |
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10 | |
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11 | Therefore, (until everybody [i.e. BSPs not shipped with RTEMS] |
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12 | properly implements PR288), has been added: |
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13 | |
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14 | - fixed BSPs must put a special value into SPRG0 during bspstart |
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15 | which is verified by the 'new exception processing' CPU_Initialize() |
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16 | to catch buggy BSPs which haven't implemented the fix yet. |
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17 | |
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18 | This is a severe bug - I experienced serious watchdog chain corruption. |
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19 | |
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20 | As a consequence, |
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21 | |
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22 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE |
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23 | |
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24 | has been changed to |
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25 | |
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26 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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27 | |
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28 | and the PPC specific routine has been removed. |
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29 | |
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30 | NOTE: in addition to this fix, PR430 must be applied to prevent |
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31 | watchdog chain corruption. |
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32 | |
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33 | Till Straumann <strauman@slac.stanford.edu>, 2003/7/10 |
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34 | |
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35 | Index: c/src/lib/libbsp/powerpc/eth_comm/irq/irq_asm.S |
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36 | =================================================================== |
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37 | RCS file: /afs/slac/g/spear/cvsrep/rtems/src-20030128/c/src/lib/libbsp/powerpc/eth_comm/irq/irq_asm.S,v |
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38 | retrieving revision 1.1.1.2 |
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39 | diff -c -r1.1.1.2 irq_asm.S |
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40 | *** c/src/lib/libbsp/powerpc/eth_comm/irq/irq_asm.S 29 Jan 2003 22:52:46 -0000 1.1.1.2 |
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41 | --- c/src/lib/libbsp/powerpc/eth_comm/irq/irq_asm.S 12 Jul 2003 19:01:34 -0000 |
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42 | *************** |
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43 | *** 9,14 **** |
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44 | --- 9,17 ---- |
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45 | * Modified to support the MCP750. |
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46 | * Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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47 | * |
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48 | + * Till Straumann <strauman@slac.stanford.edu>, 2003/7: |
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49 | + * - store isr nesting level in _ISR_Nest_level rather than |
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50 | + * SPRG0 - RTEMS relies on that variable. |
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51 | * |
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52 | * irq_asm.S,v 1.2 2002/04/18 20:54:49 joel Exp |
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53 | */ |
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54 | *************** |
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55 | *** 136,145 **** |
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56 | --- 139,156 ---- |
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57 | * store part of _Thread_Dispatch_disable_level address in R15 |
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58 | */ |
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59 | addis r15,0, _Thread_Dispatch_disable_level@ha |
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60 | + #if BROKEN_ISR_NEST_LEVEL |
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61 | /* |
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62 | * Get current nesting level in R2 |
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63 | */ |
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64 | mfspr r2, SPRG0 |
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65 | + #else |
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66 | + /* |
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67 | + * Retrieve current nesting level from _ISR_Nest_level |
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68 | + */ |
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69 | + lis r7, _ISR_Nest_level@ha |
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70 | + lwz r2, _ISR_Nest_level@l(r7) |
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71 | + #endif |
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72 | /* |
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73 | * Check if stack switch is necessary |
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74 | */ |
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75 | *************** |
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76 | *** 156,165 **** |
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77 | * Start Incrementing _Thread_Dispatch_disable_level R4 = _Thread_Dispatch_disable_level |
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78 | */ |
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79 | lwz r6,_Thread_Dispatch_disable_level@l(r15) |
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80 | /* |
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81 | ! * store new nesting level in SPRG0 |
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82 | */ |
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83 | mtspr SPRG0, r2 |
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84 | |
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85 | addi r6, r6, 1 |
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86 | mfmsr r5 |
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87 | --- 167,181 ---- |
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88 | * Start Incrementing _Thread_Dispatch_disable_level R4 = _Thread_Dispatch_disable_level |
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89 | */ |
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90 | lwz r6,_Thread_Dispatch_disable_level@l(r15) |
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91 | + #if BROKEN_ISR_NEST_LEVEL |
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92 | /* |
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93 | ! * Store new nesting level in SPRG0 |
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94 | */ |
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95 | mtspr SPRG0, r2 |
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96 | + #else |
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97 | + /* store new nesting level in _ISR_Nest_level */ |
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98 | + stw r2, _ISR_Nest_level@l(r7) |
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99 | + #endif |
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100 | |
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101 | addi r6, r6, 1 |
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102 | mfmsr r5 |
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103 | *************** |
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104 | *** 183,196 **** |
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105 | --- 199,221 ---- |
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106 | * value as an easy exit condition because if interrupt nesting level > 1 |
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107 | * then _Thread_Dispatch_disable_level > 1 |
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108 | */ |
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109 | + #if BROKEN_ISR_NEST_LEVEL |
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110 | mfspr r2, SPRG0 |
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111 | + #else |
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112 | + lis r7, _ISR_Nest_level@ha |
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113 | + lwz r2, _ISR_Nest_level@l(r7) |
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114 | + #endif |
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115 | /* |
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116 | * start decrementing _Thread_Dispatch_disable_level |
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117 | */ |
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118 | lwz r3,_Thread_Dispatch_disable_level@l(r15) |
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119 | addi r2, r2, -1 /* Continue decrementing nesting level */ |
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120 | addi r3, r3, -1 /* Continue decrementing _Thread_Dispatch_disable_level */ |
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121 | + #if BROKEN_ISR_NEST_LEVEL |
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122 | mtspr SPRG0, r2 /* End decrementing nesting level */ |
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123 | + #else |
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124 | + stw r2, _ISR_Nest_level@l(r7) /* End decrementing nesting level */ |
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125 | + #endif |
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126 | stw r3,_Thread_Dispatch_disable_level@l(r15) /* End decrementing _Thread_Dispatch_disable_level */ |
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127 | cmpwi r3, 0 |
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128 | /* |
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129 | Index: c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c |
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130 | =================================================================== |
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131 | RCS file: /afs/slac/g/spear/cvsrep/rtems/src-20030128/c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c,v |
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132 | retrieving revision 1.1.1.2 |
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133 | diff -c -r1.1.1.2 bspstart.c |
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134 | *** c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c 29 Jan 2003 22:52:47 -0000 1.1.1.2 |
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135 | --- c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c 12 Jul 2003 19:03:35 -0000 |
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136 | *************** |
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137 | *** 25,30 **** |
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138 | --- 25,31 ---- |
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139 | #include <rtems/libcsupport.h> |
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140 | #include <info.h> |
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141 | #include <libcpu/cpuIdent.h> |
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142 | + #include <libcpu/spr.h> |
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143 | #include <rtems/bspIo.h> |
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144 | |
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145 | boardinfo_t M860_binfo; |
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146 | *************** |
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147 | *** 108,113 **** |
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148 | --- 109,116 ---- |
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149 | #endif |
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150 | } |
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151 | |
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152 | + SPR_RW(SPRG0) |
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153 | + SPR_RW(SPRG1) |
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154 | |
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155 | void bsp_start(void) |
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156 | { |
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157 | *************** |
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158 | *** 117,123 **** |
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159 | ppc_cpu_id_t myCpu; |
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160 | ppc_cpu_revision_t myCpuRevision; |
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161 | register unsigned char* intrStack; |
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162 | - register unsigned int intrNestingLevel = 0; |
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163 | extern void cpu_init(void); |
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164 | |
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165 | /* |
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166 | --- 120,125 ---- |
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167 | *************** |
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168 | *** 134,141 **** |
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169 | */ |
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170 | |
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171 | intrStack = (((unsigned char*)&intrStackPtr) - CPU_MINIMUM_STACK_FRAME_SIZE); |
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172 | ! asm volatile ("mtspr 273, %0" : "=r" (intrStack) : "0" (intrStack)); |
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173 | ! asm volatile ("mtspr 272, %0" : "=r" (intrNestingLevel) : "0" (intrNestingLevel)); |
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174 | |
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175 | /* |
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176 | * Install our own set of exception vectors |
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177 | --- 136,146 ---- |
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178 | */ |
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179 | |
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180 | intrStack = (((unsigned char*)&intrStackPtr) - CPU_MINIMUM_STACK_FRAME_SIZE); |
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181 | ! |
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182 | ! _write_SPRG1((unsigned int)intrStack); |
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183 | ! |
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184 | ! /* Signal them that this BSP has fixed PR288 - eventually, this should go away */ |
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185 | ! _write_SPRG0(PPC_BSP_HAS_FIXED_PR288); |
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186 | |
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187 | /* |
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188 | * Install our own set of exception vectors |
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189 | Index: c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_asm.S |
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190 | =================================================================== |
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191 | RCS file: /afs/slac/g/spear/cvsrep/rtems/src-20030128/c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_asm.S,v |
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192 | retrieving revision 1.1.1.3 |
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193 | retrieving revision 1.2 |
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194 | diff -c -r1.1.1.3 -r1.2 |
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195 | *** c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_asm.S 29 Jan 2003 22:52:56 -0000 1.1.1.3 |
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196 | --- c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_asm.S 12 Jul 2003 05:30:34 -0000 1.2 |
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197 | *************** |
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198 | *** 9,14 **** |
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199 | --- 9,17 ---- |
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200 | * Modified to support the MCP750. |
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201 | * Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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202 | * |
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203 | + * Till Straumann <strauman@slac.stanford.edu>, 2003/7: |
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204 | + * - store isr nesting level in _ISR_Nest_level rather than |
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205 | + * SPRG0 - RTEMS relies on that variable. |
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206 | * |
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207 | * irq_asm.S,v 1.3 2002/04/18 20:54:54 joel Exp |
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208 | */ |
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209 | *************** |
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210 | *** 176,185 **** |
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211 | --- 179,196 ---- |
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212 | * store part of _Thread_Dispatch_disable_level address in R15 |
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213 | */ |
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214 | addis r15,0, _Thread_Dispatch_disable_level@ha |
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215 | + #if BROKEN_ISR_NEST_LEVEL |
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216 | /* |
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217 | * Get current nesting level in R2 |
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218 | */ |
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219 | mfspr r2, SPRG0 |
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220 | + #else |
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221 | + /* |
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222 | + * Retrieve current nesting level from _ISR_Nest_level |
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223 | + */ |
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224 | + lis r7, _ISR_Nest_level@ha |
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225 | + lwz r2, _ISR_Nest_level@l(r7) |
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226 | + #endif |
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227 | /* |
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228 | * Check if stack switch is necessary |
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229 | */ |
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230 | *************** |
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231 | *** 196,205 **** |
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232 | * Start Incrementing _Thread_Dispatch_disable_level R4 = _Thread_Dispatch_disable_level |
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233 | */ |
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234 | lwz r6,_Thread_Dispatch_disable_level@l(r15) |
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235 | /* |
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236 | ! * store new nesting level in SPRG0 |
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237 | */ |
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238 | mtspr SPRG0, r2 |
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239 | |
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240 | addi r6, r6, 1 |
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241 | mfmsr r5 |
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242 | --- 207,221 ---- |
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243 | * Start Incrementing _Thread_Dispatch_disable_level R4 = _Thread_Dispatch_disable_level |
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244 | */ |
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245 | lwz r6,_Thread_Dispatch_disable_level@l(r15) |
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246 | + #if BROKEN_ISR_NEST_LEVEL |
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247 | /* |
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248 | ! * Store new nesting level in SPRG0 |
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249 | */ |
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250 | mtspr SPRG0, r2 |
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251 | + #else |
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252 | + /* store new nesting level in _ISR_Nest_level */ |
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253 | + stw r2, _ISR_Nest_level@l(r7) |
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254 | + #endif |
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255 | |
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256 | addi r6, r6, 1 |
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257 | mfmsr r5 |
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258 | *************** |
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259 | *** 223,236 **** |
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260 | --- 239,261 ---- |
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261 | * value as an easy exit condition because if interrupt nesting level > 1 |
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262 | * then _Thread_Dispatch_disable_level > 1 |
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263 | */ |
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264 | + #if BROKEN_ISR_NEST_LEVEL |
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265 | mfspr r2, SPRG0 |
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266 | + #else |
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267 | + lis r7, _ISR_Nest_level@ha |
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268 | + lwz r2, _ISR_Nest_level@l(r7) |
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269 | + #endif |
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270 | /* |
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271 | * start decrementing _Thread_Dispatch_disable_level |
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272 | */ |
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273 | lwz r3,_Thread_Dispatch_disable_level@l(r15) |
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274 | addi r2, r2, -1 /* Continue decrementing nesting level */ |
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275 | addi r3, r3, -1 /* Continue decrementing _Thread_Dispatch_disable_level */ |
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276 | + #if BROKEN_ISR_NEST_LEVEL |
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277 | mtspr SPRG0, r2 /* End decrementing nesting level */ |
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278 | + #else |
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279 | + stw r2, _ISR_Nest_level@l(r7) /* End decrementing nesting level */ |
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280 | + #endif |
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281 | stw r3,_Thread_Dispatch_disable_level@l(r15) /* End decrementing _Thread_Dispatch_disable_level */ |
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282 | cmpwi r3, 0 |
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283 | /* |
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284 | Index: c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c |
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285 | =================================================================== |
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286 | RCS file: /afs/slac/g/spear/cvsrep/rtems/src-20030128/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c,v |
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287 | retrieving revision 1.1.1.2 |
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288 | retrieving revision 1.2 |
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289 | diff -c -r1.1.1.2 -r1.2 |
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290 | *** c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c 29 Jan 2003 22:52:57 -0000 1.1.1.2 |
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291 | --- c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c 12 Jul 2003 05:30:37 -0000 1.2 |
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292 | *************** |
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293 | *** 26,31 **** |
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294 | --- 26,36 ---- |
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295 | #include <rtems/libcsupport.h> |
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296 | #include <rtems/bspIo.h> |
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297 | #include <libcpu/cpuIdent.h> |
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298 | + #include <libcpu/spr.h> |
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299 | + |
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300 | + |
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301 | + SPR_RW(SPRG0) |
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302 | + SPR_RW(SPRG1) |
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303 | |
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304 | /* |
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305 | * The original table from the application (in ROM) and our copy of it with |
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306 | *************** |
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307 | *** 134,140 **** |
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308 | ppc_cpu_id_t myCpu; |
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309 | ppc_cpu_revision_t myCpuRevision; |
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310 | register unsigned char* intrStack; |
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311 | - register unsigned int intrNestingLevel = 0; |
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312 | |
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313 | /* |
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314 | * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function |
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315 | --- 139,144 ---- |
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316 | *************** |
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317 | *** 166,173 **** |
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318 | */ |
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319 | |
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320 | intrStack = (((unsigned char*)&intrStackPtr) - CPU_MINIMUM_STACK_FRAME_SIZE); |
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321 | ! asm volatile ("mtspr 273, %0" : "=r" (intrStack) : "0" (intrStack)); |
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322 | ! asm volatile ("mtspr 272, %0" : "=r" (intrNestingLevel) : "0" (intrNestingLevel)); |
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323 | |
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324 | /* |
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325 | * Install our own set of exception vectors |
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326 | --- 170,178 ---- |
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327 | */ |
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328 | |
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329 | intrStack = (((unsigned char*)&intrStackPtr) - CPU_MINIMUM_STACK_FRAME_SIZE); |
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330 | ! _write_SPRG1((unsigned int)intrStack); |
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331 | ! /* signal them that we have fixed PR288 - eventually, this should go away */ |
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332 | ! _write_SPRG0(PPC_BSP_HAS_FIXED_PR288); |
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333 | |
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334 | /* |
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335 | * Install our own set of exception vectors |
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336 | Index: c/src/lib/libbsp/powerpc/mpc8260ads/startup/bspstart.c |
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337 | =================================================================== |
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338 | RCS file: /afs/slac/g/spear/cvsrep/rtems/src-20030128/c/src/lib/libbsp/powerpc/mpc8260ads/startup/bspstart.c,v |
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339 | retrieving revision 1.1.1.2 |
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340 | retrieving revision 1.2 |
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341 | diff -c -r1.1.1.2 -r1.2 |
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342 | *** c/src/lib/libbsp/powerpc/mpc8260ads/startup/bspstart.c 29 Jan 2003 22:53:04 -0000 1.1.1.2 |
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343 | --- c/src/lib/libbsp/powerpc/mpc8260ads/startup/bspstart.c 12 Jul 2003 05:30:57 -0000 1.2 |
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344 | *************** |
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345 | *** 47,52 **** |
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346 | --- 47,53 ---- |
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347 | #include <rtems/score/thread.h> |
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348 | #include <rtems/bspIo.h> |
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349 | #include <libcpu/cpuIdent.h> |
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350 | + #include <libcpu/spr.h> |
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351 | |
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352 | #include <string.h> |
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353 | |
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354 | *************** |
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355 | *** 55,60 **** |
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356 | --- 56,63 ---- |
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357 | #endif |
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358 | |
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359 | |
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360 | + SPR_RW(SPRG0) |
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361 | + SPR_RW(SPRG1) |
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362 | |
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363 | /* |
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364 | * The original table from the application (in ROM) and our copy of it with |
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365 | *************** |
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366 | *** 219,225 **** |
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367 | ppc_cpu_id_t myCpu; |
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368 | ppc_cpu_revision_t myCpuRevision; |
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369 | register unsigned char* intrStack; |
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370 | - register unsigned int intrNestingLevel = 0; |
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371 | |
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372 | |
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373 | /* Set MPC8260ADS board LEDS and Uart enable lines */ |
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374 | --- 222,227 ---- |
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375 | *************** |
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376 | *** 248,255 **** |
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377 | */ |
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378 | |
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379 | intrStack = (((unsigned char*)&intrStackPtr) - CPU_MINIMUM_STACK_FRAME_SIZE); |
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380 | ! asm volatile ("mtspr 273, %0" : "=r" (intrStack) : "0" (intrStack)); |
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381 | ! asm volatile ("mtspr 272, %0" : "=r" (intrNestingLevel) : "0" (intrNestingLevel)); |
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382 | |
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383 | /* |
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384 | printk( "About to call initialize_exceptions\n" ); |
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385 | --- 250,258 ---- |
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386 | */ |
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387 | |
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388 | intrStack = (((unsigned char*)&intrStackPtr) - CPU_MINIMUM_STACK_FRAME_SIZE); |
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389 | ! _write_SPRG1((unsigned int)intrStack); |
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390 | ! /* signal that we have fixed PR288 - eventually, this should go away */ |
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391 | ! _write_SPRG0(PPC_BSP_HAS_FIXED_PR288); |
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392 | |
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393 | /* |
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394 | printk( "About to call initialize_exceptions\n" ); |
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395 | Index: c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S |
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396 | =================================================================== |
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397 | RCS file: /afs/slac/g/spear/cvsrep/rtems/src-20030128/c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S,v |
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398 | retrieving revision 1.3 |
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399 | retrieving revision 1.4 |
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400 | diff -c -r1.3 -r1.4 |
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401 | *** c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S 21 Apr 2003 23:09:41 -0000 1.3 |
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402 | --- c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S 12 Jul 2003 05:31:12 -0000 1.4 |
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403 | *************** |
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404 | *** 9,14 **** |
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405 | --- 9,17 ---- |
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406 | * Modified to support the MCP750. |
---|
407 | * Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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408 | * |
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409 | + * Till Straumann <strauman@slac.stanford.edu>, 2003/7: |
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410 | + * - store isr nesting level in _ISR_Nest_level rather than |
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411 | + * SPRG0 - RTEMS relies on that variable. |
---|
412 | * |
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413 | * irq_asm.S,v 1.5.4.1 2003/02/20 21:48:25 joel Exp |
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414 | */ |
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415 | *************** |
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416 | *** 140,149 **** |
---|
417 | --- 143,160 ---- |
---|
418 | * store part of _Thread_Dispatch_disable_level address in R15 |
---|
419 | */ |
---|
420 | addis r15,0, _Thread_Dispatch_disable_level@ha |
---|
421 | + #if BROKEN_ISR_NEST_LEVEL |
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422 | /* |
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423 | * Get current nesting level in R3 |
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424 | */ |
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425 | mfspr r3, SPRG0 |
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426 | + #else |
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427 | + /* |
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428 | + * Retrieve current nesting level from _ISR_Nest_level |
---|
429 | + */ |
---|
430 | + lis r7, _ISR_Nest_level@ha |
---|
431 | + lwz r3, _ISR_Nest_level@l(r7) |
---|
432 | + #endif |
---|
433 | /* |
---|
434 | * Check if stack switch is necessary |
---|
435 | */ |
---|
436 | *************** |
---|
437 | *** 160,169 **** |
---|
438 | * Start Incrementing _Thread_Dispatch_disable_level R4 = _Thread_Dispatch_disable_level |
---|
439 | */ |
---|
440 | lwz r6,_Thread_Dispatch_disable_level@l(r15) |
---|
441 | /* |
---|
442 | ! * store new nesting level in SPRG0 |
---|
443 | */ |
---|
444 | mtspr SPRG0, r3 |
---|
445 | |
---|
446 | addi r6, r6, 1 |
---|
447 | mfmsr r5 |
---|
448 | --- 171,185 ---- |
---|
449 | * Start Incrementing _Thread_Dispatch_disable_level R4 = _Thread_Dispatch_disable_level |
---|
450 | */ |
---|
451 | lwz r6,_Thread_Dispatch_disable_level@l(r15) |
---|
452 | + #if BROKEN_ISR_NEST_LEVEL |
---|
453 | /* |
---|
454 | ! * Store new nesting level in SPRG0 |
---|
455 | */ |
---|
456 | mtspr SPRG0, r3 |
---|
457 | + #else |
---|
458 | + /* store new nesting level in _ISR_Nest_level */ |
---|
459 | + stw r3, _ISR_Nest_level@l(r7) |
---|
460 | + #endif |
---|
461 | |
---|
462 | addi r6, r6, 1 |
---|
463 | mfmsr r5 |
---|
464 | *************** |
---|
465 | *** 187,200 **** |
---|
466 | --- 203,225 ---- |
---|
467 | * value as an easy exit condition because if interrupt nesting level > 1 |
---|
468 | * then _Thread_Dispatch_disable_level > 1 |
---|
469 | */ |
---|
470 | + #if BROKEN_ISR_NEST_LEVEL |
---|
471 | mfspr r4, SPRG0 |
---|
472 | + #else |
---|
473 | + lis r7, _ISR_Nest_level@ha |
---|
474 | + lwz r4, _ISR_Nest_level@l(r7) |
---|
475 | + #endif |
---|
476 | /* |
---|
477 | * start decrementing _Thread_Dispatch_disable_level |
---|
478 | */ |
---|
479 | lwz r3,_Thread_Dispatch_disable_level@l(r15) |
---|
480 | addi r4, r4, -1 /* Continue decrementing nesting level */ |
---|
481 | addi r3, r3, -1 /* Continue decrementing _Thread_Dispatch_disable_level */ |
---|
482 | + #if BROKEN_ISR_NEST_LEVEL |
---|
483 | mtspr SPRG0, r4 /* End decrementing nesting level */ |
---|
484 | + #else |
---|
485 | + stw r4, _ISR_Nest_level@l(r7) /* End decrementing nesting level */ |
---|
486 | + #endif |
---|
487 | stw r3,_Thread_Dispatch_disable_level@l(r15) /* End decrementing _Thread_Dispatch_disable_level */ |
---|
488 | cmpwi r3, 0 |
---|
489 | /* |
---|
490 | Index: c/src/lib/libbsp/powerpc/shared/startup/bspstart.c |
---|
491 | =================================================================== |
---|
492 | RCS file: /afs/slac/g/spear/cvsrep/rtems/src-20030128/c/src/lib/libbsp/powerpc/shared/startup/bspstart.c,v |
---|
493 | retrieving revision 1.9 |
---|
494 | retrieving revision 1.11 |
---|
495 | diff -c -r1.9 -r1.11 |
---|
496 | *** c/src/lib/libbsp/powerpc/shared/startup/bspstart.c 13 Jun 2003 02:27:31 -0000 1.9 |
---|
497 | --- c/src/lib/libbsp/powerpc/shared/startup/bspstart.c 12 Jul 2003 05:31:14 -0000 1.11 |
---|
498 | *************** |
---|
499 | *** 45,52 **** |
---|
500 | extern void BSP_pgtbl_activate(); |
---|
501 | extern void BSP_vme_config(); |
---|
502 | |
---|
503 | ! SPR_RW(SPR0) |
---|
504 | ! SPR_RW(SPR1) |
---|
505 | |
---|
506 | /* |
---|
507 | * Copy of residuals passed by firmware |
---|
508 | --- 45,52 ---- |
---|
509 | extern void BSP_pgtbl_activate(); |
---|
510 | extern void BSP_vme_config(); |
---|
511 | |
---|
512 | ! SPR_RW(SPRG0) |
---|
513 | ! SPR_RW(SPRG1) |
---|
514 | |
---|
515 | /* |
---|
516 | * Copy of residuals passed by firmware |
---|
517 | *************** |
---|
518 | *** 179,185 **** |
---|
519 | unsigned char *stack; |
---|
520 | unsigned l2cr; |
---|
521 | register unsigned char* intrStack; |
---|
522 | - register unsigned int intrNestingLevel = 0; |
---|
523 | unsigned char *work_space_start; |
---|
524 | ppc_cpu_id_t myCpu; |
---|
525 | ppc_cpu_revision_t myCpuRevision; |
---|
526 | --- 179,184 ---- |
---|
527 | *************** |
---|
528 | *** 219,225 **** |
---|
529 | |
---|
530 | /* |
---|
531 | * Initialize the interrupt related settings |
---|
532 | - * SPRG0 = interrupt nesting level count |
---|
533 | * SPRG1 = software managed IRQ stack |
---|
534 | * |
---|
535 | * This could be done latter (e.g in IRQ_INIT) but it helps to understand |
---|
536 | --- 218,223 ---- |
---|
537 | *************** |
---|
538 | *** 233,240 **** |
---|
539 | /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */ |
---|
540 | *((unsigned32 *)intrStack) = 0; |
---|
541 | |
---|
542 | ! _write_SPR1((unsigned int)intrStack); |
---|
543 | ! _write_SPR0(intrNestingLevel); |
---|
544 | /* |
---|
545 | * Initialize default raw exception hanlders. See vectors/vectors_init.c |
---|
546 | */ |
---|
547 | --- 231,241 ---- |
---|
548 | /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */ |
---|
549 | *((unsigned32 *)intrStack) = 0; |
---|
550 | |
---|
551 | ! _write_SPRG1((unsigned int)intrStack); |
---|
552 | ! |
---|
553 | ! /* signal them that we have fixed PR288 - eventually, this should go away */ |
---|
554 | ! _write_SPRG0(PPC_BSP_HAS_FIXED_PR288); |
---|
555 | ! |
---|
556 | /* |
---|
557 | * Initialize default raw exception hanlders. See vectors/vectors_init.c |
---|
558 | */ |
---|
559 | Index: c/src/lib/libbsp/powerpc/support/new_exception_processing/cpu.c |
---|
560 | =================================================================== |
---|
561 | RCS file: /afs/slac/g/spear/cvsrep/rtems/src-20030128/c/src/lib/libbsp/powerpc/support/new_exception_processing/cpu.c,v |
---|
562 | retrieving revision 1.5 |
---|
563 | retrieving revision 1.6 |
---|
564 | diff -c -r1.5 -r1.6 |
---|
565 | *** c/src/lib/libbsp/powerpc/support/new_exception_processing/cpu.c 21 Apr 2003 23:09:56 -0000 1.5 |
---|
566 | --- c/src/lib/libbsp/powerpc/support/new_exception_processing/cpu.c 12 Jul 2003 05:31:54 -0000 1.6 |
---|
567 | *************** |
---|
568 | *** 50,55 **** |
---|
569 | --- 50,63 ---- |
---|
570 | ) |
---|
571 | { |
---|
572 | _CPU_Table = *cpu_table; |
---|
573 | + |
---|
574 | + { unsigned hasFixed = 0; |
---|
575 | + /* assert that our BSP has fixed PR288 */ |
---|
576 | + __asm__ __volatile__ ("mfspr %0, %2":"=r"(hasFixed):"0"(hasFixed),"i"(SPRG0)); |
---|
577 | + if ( PPC_BSP_HAS_FIXED_PR288 != hasFixed ) { |
---|
578 | + BSP_panic("This BSP needs to fix PR#288"); |
---|
579 | + } |
---|
580 | + } |
---|
581 | } |
---|
582 | |
---|
583 | /*PAGE |
---|
584 | *************** |
---|
585 | *** 141,169 **** |
---|
586 | |
---|
587 | void _CPU_Install_interrupt_stack( void ) |
---|
588 | { |
---|
589 | - } |
---|
590 | - |
---|
591 | - /*PAGE |
---|
592 | - * |
---|
593 | - * This is the PowerPC specific implementation of the routine which |
---|
594 | - * returns TRUE if an interrupt is in progress. |
---|
595 | - */ |
---|
596 | - |
---|
597 | - boolean _ISR_Is_in_progress( void ) |
---|
598 | - { |
---|
599 | - /* |
---|
600 | - * Until the patch on PR288 is in all new exception BSPs, this is |
---|
601 | - * the safest thing to do. |
---|
602 | - */ |
---|
603 | - #ifdef mpc8260 |
---|
604 | - return (_ISR_Nest_level != 0); |
---|
605 | - #else |
---|
606 | - register unsigned int isr_nesting_level; |
---|
607 | - /* |
---|
608 | - * Move from special purpose register 0 (mfspr SPRG0, r3) |
---|
609 | - */ |
---|
610 | - asm volatile ("mfspr %0, 272" : "=r" (isr_nesting_level)); |
---|
611 | - return isr_nesting_level; |
---|
612 | - #endif |
---|
613 | } |
---|
614 | |
---|
615 | --- 149,153 ---- |
---|
616 | Index: cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h |
---|
617 | =================================================================== |
---|
618 | RCS file: /afs/slac/g/spear/cvsrep/rtems/src-20030128/cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h,v |
---|
619 | retrieving revision 1.4 |
---|
620 | retrieving revision 1.5 |
---|
621 | diff -c -r1.4 -r1.5 |
---|
622 | *** cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h 30 Jan 2003 00:50:23 -0000 1.4 |
---|
623 | --- cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h 12 Jul 2003 05:33:25 -0000 1.5 |
---|
624 | *************** |
---|
625 | *** 539,548 **** |
---|
626 | |
---|
627 | /* |
---|
628 | * This is defined if the port has a special way to report the ISR nesting |
---|
629 | ! * level. Most ports maintain the variable _ISR_Nest_level. |
---|
630 | */ |
---|
631 | |
---|
632 | ! #define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE |
---|
633 | |
---|
634 | /* |
---|
635 | * Should be large enough to run all RTEMS tests. This insures |
---|
636 | --- 539,550 ---- |
---|
637 | |
---|
638 | /* |
---|
639 | * This is defined if the port has a special way to report the ISR nesting |
---|
640 | ! * level. Most ports maintain the variable _ISR_Nest_level. Note that |
---|
641 | ! * this is not an option - RTEMS/score _relies_ on _ISR_Nest_level |
---|
642 | ! * being maintained (e.g. watchdog queues). |
---|
643 | */ |
---|
644 | |
---|
645 | ! #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
---|
646 | |
---|
647 | /* |
---|
648 | * Should be large enough to run all RTEMS tests. This insures |
---|
649 | *************** |
---|
650 | *** 830,836 **** |
---|
651 | --- 832,847 ---- |
---|
652 | * _CPU_Initialize |
---|
653 | * |
---|
654 | * This routine performs CPU dependent initialization. |
---|
655 | + * |
---|
656 | + * Until all new-exception processing BSPs have fixed |
---|
657 | + * PR288, we let the good BSPs pass |
---|
658 | + * |
---|
659 | + * PPC_BSP_HAS_FIXED_PR288 |
---|
660 | + * |
---|
661 | + * in SPRG0 and let _CPU_Initialize assert this. |
---|
662 | */ |
---|
663 | + |
---|
664 | + #define PPC_BSP_HAS_FIXED_PR288 0x600dbabe |
---|
665 | |
---|
666 | void _CPU_Initialize( |
---|
667 | rtems_cpu_table *cpu_table, |
---|