![[RTEMS Logo]](/images/logo.png){kind=logo}
Ticket #2457: 0001-powerpc-ep1a-Remove.patch
| File 0001-powerpc-ep1a-Remove.patch, 200.6 KB (added by Aun-Ali Zaidi, on 12/09/15 at 03:58:00) |
|---|
-
c/src/lib/libbsp/powerpc/acinclude.m4
From 6e2580fc483606de58dce36d910be8fcc583964c Mon Sep 17 00:00:00 2001 From: Aun-Ali Zaidi <admin@kodeit.net> Date: Tue, 8 Dec 2015 21:47:08 -0600 Subject: [PATCH] powerpc/ep1a: Remove updates #2457. --- c/src/lib/libbsp/powerpc/acinclude.m4 | 6 +- c/src/lib/libbsp/powerpc/ep1a/Makefile.am | 100 -- c/src/lib/libbsp/powerpc/ep1a/bsp_specs | 14 - c/src/lib/libbsp/powerpc/ep1a/configure.ac | 46 - c/src/lib/libbsp/powerpc/ep1a/console/alloc360.c | 110 --- c/src/lib/libbsp/powerpc/ep1a/console/config.c | 439 --------- c/src/lib/libbsp/powerpc/ep1a/console/console.h | 20 - c/src/lib/libbsp/powerpc/ep1a/console/init68360.c | 35 - c/src/lib/libbsp/powerpc/ep1a/console/m68360.h | 978 ------------------- .../lib/libbsp/powerpc/ep1a/console/mc68360_scc.c | 904 ----------------- c/src/lib/libbsp/powerpc/ep1a/console/ns16550cfg.c | 53 - c/src/lib/libbsp/powerpc/ep1a/console/ns16550cfg.h | 43 - c/src/lib/libbsp/powerpc/ep1a/console/polled_io.c | 1026 -------------------- .../libbsp/powerpc/ep1a/console/printk_support.c | 49 - c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.c | 402 -------- c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.h | 163 ---- c/src/lib/libbsp/powerpc/ep1a/include/bsp.h | 209 ---- c/src/lib/libbsp/powerpc/ep1a/include/tm27.h | 64 -- c/src/lib/libbsp/powerpc/ep1a/irq/irq_init.c | 216 ----- .../lib/libbsp/powerpc/ep1a/irq/openpic_xxx_irq.c | 234 ----- c/src/lib/libbsp/powerpc/ep1a/make/custom/ep1a.cfg | 17 - c/src/lib/libbsp/powerpc/ep1a/pci/no_host_bridge.c | 28 - c/src/lib/libbsp/powerpc/ep1a/preinstall.am | 143 --- c/src/lib/libbsp/powerpc/ep1a/start/start.S | 146 --- c/src/lib/libbsp/powerpc/ep1a/startup/bspstart.c | 353 ------- c/src/lib/libbsp/powerpc/ep1a/startup/linkcmds | 208 ---- c/src/lib/libbsp/powerpc/ep1a/vme/VMEConfig.h | 113 --- 27 files changed, 2 insertions(+), 6117 deletions(-) delete mode 100644 c/src/lib/libbsp/powerpc/ep1a/Makefile.am delete mode 100644 c/src/lib/libbsp/powerpc/ep1a/bsp_specs delete mode 100644 c/src/lib/libbsp/powerpc/ep1a/configure.ac delete mode 100644 c/src/lib/libbsp/powerpc/ep1a/console/alloc360.c delete mode 100644 c/src/lib/libbsp/powerpc/ep1a/console/config.c delete mode 100644 c/src/lib/libbsp/powerpc/ep1a/console/console.h delete mode 100644 c/src/lib/libbsp/powerpc/ep1a/console/init68360.c delete mode 100644 c/src/lib/libbsp/powerpc/ep1a/console/m68360.h delete mode 100644 c/src/lib/libbsp/powerpc/ep1a/console/mc68360_scc.c delete mode 100644 c/src/lib/libbsp/powerpc/ep1a/console/ns16550cfg.c delete mode 100644 c/src/lib/libbsp/powerpc/ep1a/console/ns16550cfg.h delete mode 100644 c/src/lib/libbsp/powerpc/ep1a/console/polled_io.c delete mode 100644 c/src/lib/libbsp/powerpc/ep1a/console/printk_support.c delete mode 100644 c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.c delete mode 100644 c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.h delete mode 100644 c/src/lib/libbsp/powerpc/ep1a/include/bsp.h delete mode 100644 c/src/lib/libbsp/powerpc/ep1a/include/tm27.h delete mode 100644 c/src/lib/libbsp/powerpc/ep1a/irq/irq_init.c delete mode 100644 c/src/lib/libbsp/powerpc/ep1a/irq/openpic_xxx_irq.c delete mode 100644 c/src/lib/libbsp/powerpc/ep1a/make/custom/ep1a.cfg delete mode 100644 c/src/lib/libbsp/powerpc/ep1a/pci/no_host_bridge.c delete mode 100644 c/src/lib/libbsp/powerpc/ep1a/preinstall.am delete mode 100644 c/src/lib/libbsp/powerpc/ep1a/start/start.S delete mode 100644 c/src/lib/libbsp/powerpc/ep1a/startup/bspstart.c delete mode 100644 c/src/lib/libbsp/powerpc/ep1a/startup/linkcmds delete mode 100644 c/src/lib/libbsp/powerpc/ep1a/vme/VMEConfig.h diff --git a/c/src/lib/libbsp/powerpc/acinclude.m4 b/c/src/lib/libbsp/powerpc/acinclude.m4 index 6442399..b0a2513 100644
a b AC_DEFUN([RTEMS_CHECK_BSPDIR], 4 4 case "$1" in 5 5 beatnik ) 6 6 AC_CONFIG_SUBDIRS([beatnik]);; 7 ep1a )8 AC_CONFIG_SUBDIRS([ep1a]);;9 7 gen5200 ) 10 8 AC_CONFIG_SUBDIRS([gen5200]);; 11 9 gen83xx ) … … AC_DEFUN([RTEMS_CHECK_BSPDIR], 38 36 AC_CONFIG_SUBDIRS([t32mppc]);; 39 37 tqm8xx ) 40 38 AC_CONFIG_SUBDIRS([tqm8xx]);; 41 virtex )42 AC_CONFIG_SUBDIRS([virtex]);;43 39 virtex4 ) 44 40 AC_CONFIG_SUBDIRS([virtex4]);; 45 41 virtex5 ) 46 42 AC_CONFIG_SUBDIRS([virtex5]);; 43 virtex ) 44 AC_CONFIG_SUBDIRS([virtex]);; 47 45 *) 48 46 AC_MSG_ERROR([Invalid BSP]);; 49 47 esac -
deleted file c/src/lib/libbsp/powerpc/ep1a/Makefile.am
diff --git a/c/src/lib/libbsp/powerpc/ep1a/Makefile.am b/c/src/lib/libbsp/powerpc/ep1a/Makefile.am deleted file mode 100644 index b1d0394..0000000
+ - 1 ACLOCAL_AMFLAGS = -I ../../../../aclocal2 3 include $(top_srcdir)/../../../../automake/compile.am4 5 include_bspdir = $(includedir)/bsp6 7 dist_project_lib_DATA = bsp_specs8 9 include_HEADERS = include/bsp.h10 include_HEADERS += include/tm27.h11 12 nodist_include_HEADERS = include/bspopts.h13 nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h14 DISTCLEANFILES = include/bspopts.h15 nodist_include_HEADERS += ../../shared/include/coverhd.h16 17 ###18 dist_project_lib_DATA += startup/linkcmds19 20 noinst_LIBRARIES = libbspstart.a21 libbspstart_a_SOURCES = start/start.S22 project_lib_DATA = start.$(OBJEXT)23 24 libbspstart_a_SOURCES += ../../powerpc/shared/start/rtems_crti.S25 project_lib_DATA += rtems_crti.$(OBJEXT)26 27 noinst_LIBRARIES += libbsp.a28 libbsp_a_SOURCES =29 30 # startup31 libbsp_a_SOURCES += startup/bspstart.c ../../shared/bootcard.c \32 ../../shared/bsppost.c ../../shared/bsppredriverhook.c \33 ../../powerpc/shared/startup/bspgetworkarea.c ../../shared/bsplibc.c \34 ../../powerpc/shared/startup/sbrk.c \35 ../../shared/bspclean.c ../../shared/gnatinstallhandler.c \36 ../../powerpc/shared/startup/pgtbl_setup.c \37 ../../powerpc/shared/startup/pgtbl_activate.c \38 ../../powerpc/shared/showbats.c39 40 # pclock41 libbsp_a_SOURCES += ../../powerpc/shared/clock/p_clock.c42 43 include_bsp_HEADERS = ../../powerpc/shared/console/uart.h \44 ../../powerpc/shared/motorola/motorola.h \45 ../../powerpc/shared/residual/residual.h \46 ../../powerpc/shared/residual/pnp.h \47 ../../powerpc/shared/console/consoleIo.h console/rsPMCQ1.h \48 ../../shared/console_private.h49 50 # console51 libbsp_a_SOURCES += console/ns16550cfg.c \52 console/mc68360_scc.c console/rsPMCQ1.c console/alloc360.c \53 console/init68360.c console/config.c console/printk_support.c \54 ../../shared/console.c ../../shared/console_select.c \55 ../../shared/console_read.c ../../shared/console_write.c \56 ../../shared/console_control.c57 58 include_bsp_HEADERS += ../../powerpc/shared/openpic/openpic.h59 # openpic60 libbsp_a_SOURCES += ../../powerpc/shared/openpic/openpic.h \61 ../../powerpc/shared/openpic/openpic.c62 63 include_bsp_HEADERS += ../../powerpc/shared/pci/pci.h64 # pci65 libbsp_a_SOURCES += pci/no_host_bridge.c ../../powerpc/shared/pci/pci.c \66 ../../powerpc/shared/pci/pcifinddevice.c67 68 include_bsp_HEADERS += ../../powerpc/shared/irq/irq.h \69 ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h70 # irq71 libbsp_a_SOURCES += irq/irq_init.c irq/openpic_xxx_irq.c ../../powerpc/shared/irq/i8259.c72 73 include_bsp_HEADERS += ../../shared/vmeUniverse/vmeUniverse.h \74 vme/VMEConfig.h \75 ../../shared/vmeUniverse/vme_am_defs.h \76 ../../shared/vmeUniverse/VME.h \77 ../../shared/vmeUniverse/vmeUniverseDMA.h\78 ../../shared/vmeUniverse/bspVmeDmaList.h\79 ../../shared/vmeUniverse/VMEDMA.h80 81 # vme82 libbsp_a_SOURCES += ../../shared/vmeUniverse/vmeUniverse.c \83 ../../shared/vmeUniverse/bspVmeDmaList.c \84 ../shared/vme/vmeconfig.c \85 ../shared/vme/vme_universe.c \86 ../../shared/vmeUniverse/vme_am_defs.h87 88 libbsp_a_LIBADD = \89 ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \90 ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \91 ../../../libcpu/@RTEMS_CPU@/shared/stack.rel \92 ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \93 ../../../libcpu/@RTEMS_CPU@/mpc6xx/clock.rel \94 ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \95 ../../../libcpu/@RTEMS_CPU@/@exceptions@/irq_bspsupport.rel \96 ../../../libcpu/@RTEMS_CPU@/mpc6xx/mmu.rel \97 ../../../libcpu/@RTEMS_CPU@/mpc6xx/timer.rel98 99 include $(srcdir)/preinstall.am100 include $(top_srcdir)/../../../../automake/local.am -
deleted file c/src/lib/libbsp/powerpc/ep1a/bsp_specs
diff --git a/c/src/lib/libbsp/powerpc/ep1a/bsp_specs b/c/src/lib/libbsp/powerpc/ep1a/bsp_specs deleted file mode 100644 index d11921e..0000000
+ - 1 %rename endfile old_endfile2 %rename startfile old_startfile3 %rename link old_link4 5 *startfile:6 %{!qrtems: %(old_startfile)} \7 %{!nostdlib: %{qrtems: ecrti%O%s rtems_crti%O%s crtbegin.o%s start.o%s \8 -e __rtems_entry_point -u __vectors}}9 10 *link:11 %{!qrtems: %(old_link)} %{qrtems: -dp -Bstatic}12 13 *endfile:14 %{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s ecrtn.o%s} -
deleted file c/src/lib/libbsp/powerpc/ep1a/configure.ac
diff --git a/c/src/lib/libbsp/powerpc/ep1a/configure.ac b/c/src/lib/libbsp/powerpc/ep1a/configure.ac deleted file mode 100644 index c76623d..0000000
+ - 1 ## Process this file with autoconf to produce a configure script.2 3 AC_PREREQ([2.69])4 AC_INIT([rtems-c-src-lib-libbsp-powerpc-ep1a],[_RTEMS_VERSION],[https://devel.rtems.org/newticket])5 AC_CONFIG_SRCDIR([bsp_specs])6 RTEMS_TOP(../../../../../..)7 8 RTEMS_CANONICAL_TARGET_CPU9 AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2])10 RTEMS_BSP_CONFIGURE11 12 RTEMS_PROG_CC_FOR_TARGET13 RTEMS_CANONICALIZE_TOOLS14 RTEMS_PROG_CCAS15 16 RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([*],[])17 RTEMS_BSPOPTS_HELP_DATA_CACHE_ENABLED18 19 RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([*],[])20 RTEMS_BSPOPTS_HELP_INSTRUCTION_CACHE_ENABLED21 22 RTEMS_BSPOPTS_SET([CONSOLE_USE_INTERRUPTS],[*],[0])23 RTEMS_BSPOPTS_HELP([CONSOLE_USE_INTERRUPTS],24 [whether using console interrupts])25 26 RTEMS_BSPOPTS_SET([CONFIGURE_MALLOC_BSP_SUPPORTS_SBRK], [*], [1])27 RTEMS_BSPOPTS_HELP([CONFIGURE_MALLOC_BSP_SUPPORTS_SBRK],28 [If defined then the BSP may reduce the available memory size29 initially. This can be useful for debugging (reduce the core30 size) or dynamic loading (std gcc text offsets/jumps are < +/-32M).31 Note that the policy can still be defined by the application32 (see sbrk.c, BSP_sbrk_policy). By undefining33 CONFIGURE_MALLOC_BSP_SUPPORTS_SBRK this feature is removed34 and a little memory is saved.])35 36 RTEMS_CHECK_NETWORKING37 AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")38 39 RTEMS_BSP_CLEANUP_OPTIONS(0, 0)40 41 # Explicitly list all Makefiles here42 AC_CONFIG_FILES([Makefile])43 44 RTEMS_PPC_EXCEPTIONS45 46 AC_OUTPUT -
deleted file c/src/lib/libbsp/powerpc/ep1a/console/alloc360.c
diff --git a/c/src/lib/libbsp/powerpc/ep1a/console/alloc360.c b/c/src/lib/libbsp/powerpc/ep1a/console/alloc360.c deleted file mode 100644 index edc13ff..0000000
+ - 1 /*2 * MC68360 buffer descriptor allocation routines3 *4 * W. Eric Norum5 * Saskatchewan Accelerator Laboratory6 * University of Saskatchewan7 * Saskatoon, Saskatchewan, CANADA8 * eric@skatter.usask.ca9 *10 * COPYRIGHT (c) 2008.11 * On-Line Applications Research Corporation (OAR).12 *13 * The license and distribution terms for this file may be14 * found in the file LICENSE in this distribution or at15 * http://www.rtems.org/license/LICENSE.16 */17 18 #include <rtems.h>19 #include <bsp.h>20 #include "m68360.h"21 #include <rtems/error.h>22 #include "rsPMCQ1.h"23 #include <rtems/bspIo.h>24 25 26 #define DEBUG_PRINT 127 28 void M360SetupMemory( M68360_t ptr )29 {30 volatile m360_t *m360;31 32 m360 = ptr->m360;33 34 #if DEBUG_PRINT35 printk("m360->mcr:0x%08x Q1_360_SIM_MCR:0x%08x\n",36 (unsigned int)&(m360->mcr), ((unsigned int)m360+Q1_360_SIM_MCR));37 #endif38 ptr->bdregions[0].base = &m360->dpram1[0];39 ptr->bdregions[0].size = sizeof m360->dpram1;40 ptr->bdregions[0].used = 0;41 42 ptr->bdregions[1].base = &m360->dpram3[0];43 ptr->bdregions[1].size = sizeof m360->dpram3;44 ptr->bdregions[1].used = 0;45 46 ptr->bdregions[2].base = &m360->dpram0[0];47 ptr->bdregions[2].size = sizeof m360->dpram0;48 ptr->bdregions[2].used = 0;49 50 ptr->bdregions[3].base = &m360->dpram2[0];51 ptr->bdregions[3].size = sizeof m360->dpram2;52 ptr->bdregions[3].used = 0;53 }54 55 56 /*57 * Send a command to the CPM RISC processer58 */59 void *60 M360AllocateBufferDescriptors (M68360_t ptr, int count)61 {62 unsigned int i;63 rtems_interrupt_level level;64 volatile unsigned char *bdp = NULL;65 unsigned int want = count * sizeof(m360BufferDescriptor_t);66 int have;67 68 /*69 * Running with interrupts disabled is usually considered bad70 * form, but this routine is probably being run as part of an71 * initialization sequence so the effect shouldn't be too severe.72 */73 rtems_interrupt_disable(level);74 75 for (i = 0 ; i < M360_NUM_DPRAM_REAGONS ; i++) {76 77 /*78 * Verify that the region exists.79 * This test is necessary since some chips have80 * less dual-port RAM.81 */82 if (ptr->bdregions[i].used == 0) {83 volatile unsigned char *cp = ptr->bdregions[i].base;84 *cp = 0xAA;85 if (*cp != 0xAA) {86 ptr->bdregions[i].used = ptr->bdregions[i].size;87 continue;88 }89 *cp = 0x55;90 if (*cp != 0x55) {91 ptr->bdregions[i].used = ptr->bdregions[i].size;92 continue;93 }94 *cp = 0x0;95 }96 97 have = ptr->bdregions[i].size - ptr->bdregions[i].used;98 if (have >= want) {99 bdp = ptr->bdregions[i].base + ptr->bdregions[i].used;100 ptr->bdregions[i].used += want;101 break;102 }103 }104 rtems_interrupt_enable(level);105 if (bdp == NULL){106 printk("rtems_panic can't allocate %d buffer descriptor(s).\n");107 rtems_panic ("Can't allocate %d buffer descriptor(s).\n", count);108 }109 return (void *)bdp;110 } -
deleted file c/src/lib/libbsp/powerpc/ep1a/console/config.c
diff --git a/c/src/lib/libbsp/powerpc/ep1a/console/config.c b/c/src/lib/libbsp/powerpc/ep1a/console/config.c deleted file mode 100644 index 8253c69..0000000
+ - 1 /*2 * This file contains the TTY driver table for the EP1A3 *4 * COPYRIGHT (c) 1989-2008.5 * On-Line Applications Research Corporation (OAR).6 *7 * The license and distribution terms for this file may be8 * found in the file LICENSE in this distribution or at9 * http://www.rtems.org/license/LICENSE.10 */11 12 #include <libchip/serial.h>13 #include <libchip/ns16550.h>14 #include "ns16550cfg.h"15 #include <bsp.h>16 #include <libcpu/io.h>17 #include "m68360.h"18 19 /*20 * Based on BSP configuration information decide whether to do polling IO21 * or interrupt driven IO.22 */23 #define NS16550_FUNCTIONS &ns16550_fns_polled24 #define MC68360_SCC_FUNCTIONS &mc68360_scc_fns25 26 /*27 * Configuration specific probe routines28 */29 static bool config_68360_scc_base_probe_1(int minor);30 static bool config_68360_scc_base_probe_2(int minor);31 static bool config_68360_scc_base_probe_3(int minor);32 static bool config_68360_scc_base_probe_4(int minor);33 static bool config_68360_scc_base_probe_5(int minor);34 static bool config_68360_scc_base_probe_6(int minor);35 static bool config_68360_scc_base_probe_7(int minor);36 static bool config_68360_scc_base_probe_8(int minor);37 static bool config_68360_scc_base_probe_9(int minor);38 static bool config_68360_scc_base_probe_10(int minor);39 static bool config_68360_scc_base_probe_11(int minor);40 static bool config_68360_scc_base_probe_12(int minor);41 42 extern const console_fns mc68360_scc_fns;43 44 /*45 * The following table configures the console drivers used in this BSP.46 *47 * The first entry which, when probed, is available, will be named /dev/console,48 * all others being given the name indicated.49 *50 * Each field is interpreted thus:51 *52 * sDeviceName This is the name of the device.53 * pDeviceFns This is a pointer to the set of driver routines to use.54 * pDeviceFlow This is a pointer to the set of flow control routines to55 * use. Serial device drivers will typically supply RTSCTS56 * and DTRCTS handshake routines for DCE to DCE communication,57 * however for DCE to DTE communication, no such routines58 * should be necessary as RTS will be driven automatically59 * when the transmitter is active.60 * ulMargin The high water mark in the input buffer is set to the buffer61 * size less ulMargin. Once this level is reached, the driver's62 * flow control routine used to stop the remote transmitter will63 * be called. This figure should be greater than or equal to64 * the number of stages of FIFO between the transmitter and65 * receiver.66 * ulHysteresis After the high water mark specified by ulMargin has been67 * reached, the driver's routine to re-start the remote68 * transmitter will be called once the level in the input69 * buffer has fallen by ulHysteresis bytes.70 * pDeviceParams This contains either device specific data or a pointer to a71 * device specific structure containing additional information72 * not provided in this table.73 * ulCtrlPort1 This is the primary control port number for the device. This74 * may be used to specify different instances of the same device75 * type.76 * ulCtrlPort2 This is the secondary control port number, of use when a given77 * device has more than one available channel.78 * ulDataPort This is the port number for the data port of the device79 * ulIntVector This encodes the interrupt vector of the device.80 *81 */82 console_tbl Console_Configuration_Ports[] = {83 /*84 * NS16550 Chips provide first COM1 and COM2 Ports.85 */86 {87 "/dev/com1", /* sDeviceName */88 SERIAL_NS16550, /* deviceType */89 NS16550_FUNCTIONS, /* pDeviceFns */90 NULL, /* deviceProbe */91 &ns16550_flow_RTSCTS, /* pDeviceFlow */92 16, /* ulMargin */93 8, /* ulHysteresis */94 (void *)9600, /* baud rate */ /* pDeviceParams */95 UART_BASE_COM1, /* ulCtrlPort1 */96 0, /* ulCtrlPort2 */97 UART_BASE_COM1, /* ulDataPort */98 Read_ns16550_register, /* getRegister */99 Write_ns16550_register, /* setRegister */100 NULL, /* getData */101 NULL, /* setData */102 7372800, /* ulClock */103 0 /* ulIntVector */104 },105 {106 "/dev/com2", /* sDeviceName */107 SERIAL_NS16550, /* deviceType */108 NS16550_FUNCTIONS, /* pDeviceFns */109 NULL, /* deviceProbe */110 &ns16550_flow_RTSCTS, /* pDeviceFlow */111 16, /* ulMargin */112 8, /* ulHysteresis */113 (void *)9600, /* baud rate */ /* pDeviceParams */114 UART_BASE_COM2, /* ulCtrlPort1-Filled in at runtime */115 0, /* ulCtrlPort2 */116 UART_BASE_COM2, /* ulDataPort-Filled in at runtime*/117 Read_ns16550_register, /* getRegister */118 Write_ns16550_register, /* setRegister */119 NULL, /* getData */120 NULL, /* setData */121 7372800, /* ulClock */122 0 /* ulIntVector */123 },124 /*125 * Up to 12 serial ports are provided by MC68360 SCC ports.126 * EP1A may have one MC68360 providing 4 ports (A,B,C,D).127 */128 {129 "/dev/rs232_2", /* sDeviceName */130 SERIAL_CUSTOM, /* deviceType */131 MC68360_SCC_FUNCTIONS, /* pDeviceFns */132 config_68360_scc_base_probe_1, /* deviceProbe */133 NULL, /* pDeviceFlow */134 16, /* ulMargin */135 8, /* ulHysteresis */136 (void *)9600, /* baud rate */ /* pDeviceParams */137 0, /* ulCtrlPort1 */138 0, /* ulCtrlPort2 */139 0, /* ulDataPort */140 NULL, /* getRegister */141 NULL, /* setRegister */142 NULL, /* getData */143 NULL, /* setData */144 0, /* ulClock */145 0 /* ulIntVector */146 },147 {148 "/dev/rs422_1", /* sDeviceName */149 SERIAL_CUSTOM, /* deviceType */150 MC68360_SCC_FUNCTIONS, /* pDeviceFns */151 config_68360_scc_base_probe_2, /* deviceProbe */152 NULL, /* pDeviceFlow */153 16, /* ulMargin */154 8, /* ulHysteresis */155 (void *)9600, /* baud rate */ /* pDeviceParams */156 0, /* ulCtrlPort1 */157 0, /* ulCtrlPort2 */158 0, /* ulDataPort */159 NULL, /* getRegister */160 NULL, /* setRegister */161 NULL, /* getData */162 NULL, /* setData */163 0, /* ulClock */164 0 /* ulIntVector */165 },166 {167 "/dev/rs422_2", /* sDeviceName */168 SERIAL_CUSTOM, /* deviceType */169 MC68360_SCC_FUNCTIONS, /* pDeviceFns */170 config_68360_scc_base_probe_3, /* deviceProbe */171 NULL, /* pDeviceFlow */172 16, /* ulMargin */173 8, /* ulHysteresis */174 (void *)9600, /* baud rate */ /* pDeviceParams */175 0, /* ulCtrlPort1 */176 0, /* ulCtrlPort2 */177 0, /* ulDataPort */178 NULL, /* getRegister */179 NULL, /* setRegister */180 NULL, /* getData */181 NULL, /* setData */182 0, /* ulClock */183 0 /* ulIntVector */184 },185 {186 "/dev/ep1a_d", /* sDeviceName */187 SERIAL_CUSTOM, /* deviceType */188 MC68360_SCC_FUNCTIONS, /* pDeviceFns */189 config_68360_scc_base_probe_4, /* deviceProbe */190 NULL, /* pDeviceFlow */191 16, /* ulMargin */192 8, /* ulHysteresis */193 (void *)9600, /* baud rate */ /* pDeviceParams */194 0, /* ulCtrlPort1 */195 0, /* ulCtrlPort2 */196 0, /* ulDataPort */197 NULL, /* getRegister */198 NULL, /* setRegister */199 NULL, /* getData */200 NULL, /* setData */201 0, /* ulClock */202 0 /* ulIntVector */203 },204 /*205 * PMC1 may have one MC16550 providing 4 ports (A,B,C,D).206 */207 {208 "/dev/rs422_3", /* sDeviceName */209 SERIAL_CUSTOM, /* deviceType */210 MC68360_SCC_FUNCTIONS, /* pDeviceFns */211 config_68360_scc_base_probe_5, /* deviceProbe */212 NULL, /* pDeviceFlow */213 16, /* ulMargin */214 8, /* ulHysteresis */215 (void *)9600, /* baud rate */ /* pDeviceParams */216 0, /* ulCtrlPort1 */217 0, /* ulCtrlPort2 */218 0, /* ulDataPort */219 NULL, /* getRegister */220 NULL, /* setRegister */221 NULL, /* getData */222 NULL, /* setData */223 0, /* ulClock */224 0 /* ulIntVector */225 },226 {227 "/dev/rs422_4", /* sDeviceName */228 SERIAL_CUSTOM, /* deviceType */229 MC68360_SCC_FUNCTIONS, /* pDeviceFns */230 config_68360_scc_base_probe_6, /* deviceProbe */231 NULL, /* pDeviceFlow */232 16, /* ulMargin */233 8, /* ulHysteresis */234 (void *)9600, /* baud rate */ /* pDeviceParams */235 0, /* ulCtrlPort1 */236 0, /* ulCtrlPort2 */237 0, /* ulDataPort */238 NULL, /* getRegister */239 NULL, /* setRegister */240 NULL, /* getData */241 NULL, /* setData */242 0, /* ulClock */243 0 /* ulIntVector */244 },245 {246 "/dev/rs422_5", /* sDeviceName */247 SERIAL_CUSTOM, /* deviceType */248 MC68360_SCC_FUNCTIONS, /* pDeviceFns */249 config_68360_scc_base_probe_7, /* deviceProbe */250 NULL, /* pDeviceFlow */251 16, /* ulMargin */252 8, /* ulHysteresis */253 (void *)9600, /* baud rate */ /* pDeviceParams */254 0, /* ulCtrlPort1 */255 0, /* ulCtrlPort2 */256 0, /* ulDataPort */257 NULL, /* getRegister */258 NULL, /* setRegister */259 NULL, /* getData */260 NULL, /* setData */261 0, /* ulClock */262 0 /* ulIntVector */263 },264 {265 "/dev/rs422_6", /* sDeviceName */266 SERIAL_CUSTOM, /* deviceType */267 MC68360_SCC_FUNCTIONS, /* pDeviceFns */268 config_68360_scc_base_probe_8, /* deviceProbe */269 NULL, /* pDeviceFlow */270 16, /* ulMargin */271 8, /* ulHysteresis */272 (void *)9600, /* baud rate */ /* pDeviceParams */273 0, /* ulCtrlPort1 */274 0, /* ulCtrlPort2 */275 0, /* ulDataPort */276 NULL, /* getRegister */277 NULL, /* setRegister */278 NULL, /* getData */279 NULL, /* setData */280 0, /* ulClock */281 0 /* ulIntVector */282 },283 /*284 * PMC2 may have one MC16550 providing 4 ports (A,B,C,D).285 */286 {287 "/dev/rs232_3", /* sDeviceName */288 SERIAL_CUSTOM, /* deviceType */289 MC68360_SCC_FUNCTIONS, /* pDeviceFns */290 config_68360_scc_base_probe_9, /* deviceProbe */291 NULL, /* pDeviceFlow */292 16, /* ulMargin */293 8, /* ulHysteresis */294 (void *)9600, /* baud rate */ /* pDeviceParams */295 0, /* ulCtrlPort1 */296 0, /* ulCtrlPort2 */297 0, /* ulDataPort */298 NULL, /* getRegister */299 NULL, /* setRegister */300 NULL, /* getData */301 NULL, /* setData */302 0, /* ulClock */303 0 /* ulIntVector */304 },305 {306 "/dev/rs232_4", /* sDeviceName */307 SERIAL_CUSTOM, /* deviceType */308 MC68360_SCC_FUNCTIONS, /* pDeviceFns */309 config_68360_scc_base_probe_10, /* deviceProbe */310 NULL, /* pDeviceFlow */311 16, /* ulMargin */312 8, /* ulHysteresis */313 (void *)9600, /* baud rate */ /* pDeviceParams */314 0, /* ulCtrlPort1 */315 0, /* ulCtrlPort2 */316 0, /* ulDataPort */317 NULL, /* getRegister */318 NULL, /* setRegister */319 NULL, /* getData */320 NULL, /* setData */321 0, /* ulClock */322 0 /* ulIntVector */323 },324 {325 "/dev/rs232_5", /* sDeviceName */326 SERIAL_CUSTOM, /* deviceType */327 MC68360_SCC_FUNCTIONS, /* pDeviceFns */328 config_68360_scc_base_probe_11, /* deviceProbe */329 NULL, /* pDeviceFlow */330 16, /* ulMargin */331 8, /* ulHysteresis */332 (void *)9600, /* baud rate */ /* pDeviceParams */333 0, /* ulCtrlPort1 */334 0, /* ulCtrlPort2 */335 0, /* ulDataPort */336 NULL, /* getRegister */337 NULL, /* setRegister */338 NULL, /* getData */339 NULL, /* setData */340 0, /* ulClock */341 0 /* ulIntVector */342 },343 {344 "/dev/rs232_6", /* sDeviceName */345 SERIAL_CUSTOM, /* deviceType */346 MC68360_SCC_FUNCTIONS, /* pDeviceFns */347 config_68360_scc_base_probe_12, /* deviceProbe */348 NULL, /* pDeviceFlow */349 16, /* ulMargin */350 8, /* ulHysteresis */351 (void *)9600, /* baud rate */ /* pDeviceParams */352 0, /* ulCtrlPort1 */353 0, /* ulCtrlPort2 */354 0, /* ulDataPort */355 NULL, /* getRegister */356 NULL, /* setRegister */357 NULL, /* getData */358 NULL, /* setData */359 0, /* ulClock */360 0 /* ulIntVector */361 }362 };363 364 /*365 * Define a variable that contains the number of statically configured366 * console devices.367 */368 unsigned long Console_Configuration_Count = \369 (sizeof(Console_Configuration_Ports)/sizeof(console_tbl));370 371 static bool config_68360_scc_base_probe(int minor, unsigned long busNo, unsigned long slotNo, int channel)372 {373 M68360_t chip = M68360_chips;374 375 /*376 * Find out if the chip is installed.377 */378 while (chip) {379 if ((chip->board_data->slotNo == slotNo) && (chip->board_data->busNo == busNo))380 break;381 chip = chip->next;382 }383 384 if (!chip)385 return false;386 387 Console_Port_Tbl[minor]->pDeviceParams = &chip->port[ channel-1 ];388 chip->port[ channel-1 ].minor = minor;389 return true;390 }391 392 static bool config_68360_scc_base_probe_1( int minor ) {393 return config_68360_scc_base_probe(minor, 0, 11, 1);394 }395 396 static bool config_68360_scc_base_probe_2( int minor ) {397 return config_68360_scc_base_probe(minor, 0, 11, 2);398 }399 400 static bool config_68360_scc_base_probe_3( int minor ) {401 return config_68360_scc_base_probe( minor, 0, 11, 3);402 }403 404 static bool config_68360_scc_base_probe_4( int minor ) {405 return config_68360_scc_base_probe( minor, 0, 11, 4);406 }407 408 static bool config_68360_scc_base_probe_5( int minor ) {409 return config_68360_scc_base_probe( minor, 0, 16, 1);410 }411 412 static bool config_68360_scc_base_probe_6( int minor ) {413 return config_68360_scc_base_probe( minor, 0, 16, 2);414 }415 416 static bool config_68360_scc_base_probe_7( int minor ) {417 return config_68360_scc_base_probe( minor, 0, 16, 3);418 }419 420 static bool config_68360_scc_base_probe_8( int minor ) {421 return config_68360_scc_base_probe( minor, 0, 16, 4);422 }423 424 static bool config_68360_scc_base_probe_9( int minor ) {425 return config_68360_scc_base_probe( minor, 0, 15, 1);426 }427 428 static bool config_68360_scc_base_probe_10( int minor ) {429 return config_68360_scc_base_probe( minor, 0, 15, 2);430 }431 432 static bool config_68360_scc_base_probe_11( int minor ) {433 return config_68360_scc_base_probe( minor, 0, 15, 3);434 }435 436 static bool config_68360_scc_base_probe_12( int minor ) {437 return config_68360_scc_base_probe( minor, 0, 15, 4);438 }439 -
deleted file c/src/lib/libbsp/powerpc/ep1a/console/console.h
diff --git a/c/src/lib/libbsp/powerpc/ep1a/console/console.h b/c/src/lib/libbsp/powerpc/ep1a/console/console.h deleted file mode 100644 index c2354d2..0000000
+ - 1 /*2 * This driver uses the termios pseudo driver.3 *4 * COPYRIGHT (c) 1989-2008.5 * On-Line Applications Research Corporation (OAR).6 *7 * The license and distribution terms for this file may be8 * found in the file LICENSE in this distribution or at9 * http://www.rtems.org/license/LICENSE.10 */11 12 #include <rtems/ringbuf.h>13 #include <libchip/serial.h>14 #include <libchip/ns16550.h>15 16 extern console_tbl Console_Port_Tbl[];17 extern console_data Console_Port_Data[];18 extern unsigned long Console_Port_Count;19 20 bool Console_Port_Tbl_Init_ppc8245(int minor); -
deleted file c/src/lib/libbsp/powerpc/ep1a/console/init68360.c
diff --git a/c/src/lib/libbsp/powerpc/ep1a/console/init68360.c b/c/src/lib/libbsp/powerpc/ep1a/console/init68360.c deleted file mode 100644 index bafcf8d..0000000
+ - 1 /*2 * MC68360 support routines - reduced from gen68360 BSP3 *4 * W. Eric Norum5 * Saskatchewan Accelerator Laboratory6 * University of Saskatchewan7 * Saskatoon, Saskatchewan, CANADA8 * eric@skatter.usask.ca9 *10 * COPYRIGHT (c) 1989-1999.11 * On-Line Applications Research Corporation (OAR).12 *13 * The license and distribution terms for this file may be14 * found in the file LICENSE in this distribution or at15 * http://www.rtems.org/license/LICENSE.16 */17 18 #include <rtems.h>19 #include <bsp.h>20 #include "m68360.h"21 22 /*23 * Send a command to the CPM RISC processer24 */25 26 void M360ExecuteRISC( volatile m360_t *m360, uint16_t command)27 {28 uint16_t sr;29 30 rtems_interrupt_disable(sr);31 while (m360->cr & M360_CR_FLG)32 continue;33 m360->cr = command | M360_CR_FLG;34 rtems_interrupt_enable(sr);35 } -
deleted file c/src/lib/libbsp/powerpc/ep1a/console/m68360.h
diff --git a/c/src/lib/libbsp/powerpc/ep1a/console/m68360.h b/c/src/lib/libbsp/powerpc/ep1a/console/m68360.h deleted file mode 100644 index 3645486..0000000
+ - 1 /*2 * MOTOROLA MC68360 QUAD INTEGRATED COMMUNICATIONS CONTROLLER (QUICC)3 *4 * HARDWARE DECLARATIONS5 *6 *7 * Submitted By:8 *9 * W. Eric Norum10 * Saskatchewan Accelerator Laboratory11 * University of Saskatchewan12 * 107 North Road13 * Saskatoon, Saskatchewan, CANADA14 * S7N 5C615 *16 * eric@skatter.usask.ca17 *18 *19 * COPYRIGHT (c) 1989-1999.20 * On-Line Applications Research Corporation (OAR).21 *22 * The license and distribution terms for this file may be23 * found in the file LICENSE in this distribution or at24 * http://www.rtems.org/license/LICENSE.25 */26 27 #ifndef __MC68360_h28 #define __MC68360_h29 30 #include "rsPMCQ1.h"31 32 /*33 *************************************************************************34 * REGISTER SUBBLOCKS *35 *************************************************************************36 */37 38 /*39 * Memory controller registers40 */41 typedef struct m360MEMCRegisters_ {42 uint32_t br;43 uint32_t or;44 uint32_t _pad[2];45 } m360MEMCRegisters_t;46 47 48 #define M360_GSMR_RFW 0x0000002049 50 #define M360_GSMR_RINV 0x0200000051 #define M360_GSMR_TINV 0x0100000052 #define M360_GSMR_TDCR_16X 0x0002000053 #define M360_GSMR_RDCR_16X 0x0000800054 #define M360_GSMR_DIAG_LLOOP 0x0000004055 #define M360_GSMR_ENR 0x0000002056 #define M360_GSMR_ENT 0x0000001057 #define M360_GSMR_MODE_UART 0x0000000458 59 #define M360_PSMR_FLC 0x800060 #define M360_PSMR_SL_1 0x000061 #define M360_PSMR_SL_2 0x400062 #define M360_PSMR_CL5 0x000063 #define M360_PSMR_CL6 0x100064 #define M360_PSMR_CL7 0x200065 #define M360_PSMR_CL8 0x300066 #define M360_PSMR_UM_NORMAL 0x000067 #define M360_PSMR_FRZ 0x020068 #define M360_PSMR_RZS 0x010069 #define M360_PSMR_SYN 0x008070 #define M360_PSMR_DRT 0x004071 #define M360_PSMR_PEN 0x001072 #define M360_PSMR_RPM_ODD 0x000073 #define M360_PSMR_RPM_LOW 0x000474 #define M360_PSMR_RPM_EVEN 0x000875 #define M360_PSMR_RPM_HI 0x000c76 #define M360_PSMR_TPM_ODD 0x000077 #define M360_PSMR_TPM_LOW 0x000178 #define M360_PSMR_TPM_EVEN 0x000279 #define M360_PSMR_TPM_HI 0x000380 81 /*82 * Serial Communications Controller registers83 */84 typedef struct m360SCCRegisters_ {85 uint32_t gsmr_l;86 uint32_t gsmr_h;87 uint16_t psmr;88 uint16_t _pad0;89 uint16_t todr;90 uint16_t dsr;91 uint16_t scce;92 uint16_t _pad1;93 uint16_t sccm;94 uint8_t _pad2;95 uint8_t sccs;96 uint32_t _pad3[2];97 } m360SCCRegisters_t;98 99 /*100 * Serial Management Controller registers101 */102 typedef struct m360SMCRegisters_ {103 uint16_t _pad0;104 uint16_t smcmr;105 uint16_t _pad1;106 uint8_t smce;107 uint8_t _pad2;108 uint16_t _pad3;109 uint8_t smcm;110 uint8_t _pad4;111 uint32_t _pad5;112 } m360SMCRegisters_t;113 114 115 /*116 *************************************************************************117 * Miscellaneous Parameters *118 *************************************************************************119 */120 typedef struct m360MiscParms_ {121 uint16_t rev_num;122 uint16_t _res1;123 uint32_t _res2;124 uint32_t _res3;125 } m360MiscParms_t;126 127 /*128 *************************************************************************129 * RISC Timers *130 *************************************************************************131 */132 typedef struct m360TimerParms_ {133 uint16_t tm_base;134 uint16_t _tm_ptr;135 uint16_t _r_tmr;136 uint16_t _r_tmv;137 uint32_t tm_cmd;138 uint32_t tm_cnt;139 } m360TimerParms_t;140 141 /*142 * RISC Controller Configuration Register (RCCR)143 * All other bits in this register are either reserved or144 * used only with a Motorola-supplied RAM microcode packge.145 */146 #define M360_RCCR_TIME (1<<15) /* Enable timer */147 #define M360_RCCR_TIMEP(x) ((x)<<8) /* Timer period */148 149 /*150 * Command register151 * Set up this register before issuing a M360_CR_OP_SET_TIMER command.152 */153 #define M360_TM_CMD_V (1<<31) /* Set to enable timer */154 #define M360_TM_CMD_R (1<<30) /* Set for automatic restart */155 #define M360_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */156 #define M360_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */157 158 /*159 *************************************************************************160 * DMA Controllers *161 *************************************************************************162 */163 typedef struct m360IDMAparms_ {164 uint16_t ibase;165 uint16_t ibptr;166 uint32_t _istate;167 uint32_t _itemp;168 } m360IDMAparms_t;169 170 /*171 *************************************************************************172 * Serial Communication Controllers *173 *************************************************************************174 */175 typedef struct m360SCCparms_ {176 uint16_t rbase;177 uint16_t tbase;178 uint8_t rfcr;179 uint8_t tfcr;180 uint16_t mrblr;181 uint32_t _rstate;182 uint32_t _pad0;183 uint16_t _rbptr;184 uint16_t _pad1;185 uint32_t _pad2;186 uint32_t _tstate;187 uint32_t _pad3;188 uint16_t _tbptr;189 uint16_t _pad4;190 uint32_t _pad5;191 uint32_t _rcrc;192 uint32_t _tcrc;193 union {194 struct {195 uint32_t _res0;196 uint32_t _res1;197 uint16_t max_idl;198 uint16_t _idlc;199 uint16_t brkcr;200 uint16_t parec;201 uint16_t frmec;202 uint16_t nosec;203 uint16_t brkec;204 uint16_t brklen;205 uint16_t uaddr[2];206 uint16_t _rtemp;207 uint16_t toseq;208 uint16_t character[8];209 uint16_t rccm;210 uint16_t rccr;211 uint16_t rlbc;212 } uart;213 struct {214 uint32_t crc_p;215 uint32_t crc_c;216 } transparent;217 218 } un;219 } m360SCCparms_t;220 221 typedef struct m360SCCENparms_ {222 uint16_t rbase;223 uint16_t tbase;224 uint8_t rfcr;225 uint8_t tfcr;226 uint16_t mrblr;227 uint32_t _rstate;228 uint32_t _pad0;229 uint16_t _rbptr;230 uint16_t _pad1;231 uint32_t _pad2;232 uint32_t _tstate;233 uint32_t _pad3;234 uint16_t _tbptr;235 uint16_t _pad4;236 uint32_t _pad5;237 uint32_t _rcrc;238 uint32_t _tcrc;239 union {240 struct {241 uint32_t _res0;242 uint32_t _res1;243 uint16_t max_idl;244 uint16_t _idlc;245 uint16_t brkcr;246 uint16_t parec;247 uint16_t frmec;248 uint16_t nosec;249 uint16_t brkec;250 uint16_t brklen;251 uint16_t uaddr[2];252 uint16_t _rtemp;253 uint16_t toseq;254 uint16_t character[8];255 uint16_t rccm;256 uint16_t rccr;257 uint16_t rlbc;258 } uart;259 struct {260 uint32_t c_pres;261 uint32_t c_mask;262 uint32_t crcec;263 uint32_t alec;264 uint32_t disfc;265 uint16_t pads;266 uint16_t ret_lim;267 uint16_t _ret_cnt;268 uint16_t mflr;269 uint16_t minflr;270 uint16_t maxd1;271 uint16_t maxd2;272 uint16_t _maxd;273 uint16_t dma_cnt;274 uint16_t _max_b;275 uint16_t gaddr1;276 uint16_t gaddr2;277 uint16_t gaddr3;278 uint16_t gaddr4;279 uint32_t _tbuf0data0;280 uint32_t _tbuf0data1;281 uint32_t _tbuf0rba0;282 uint32_t _tbuf0crc;283 uint16_t _tbuf0bcnt;284 uint16_t paddr_h;285 uint16_t paddr_m;286 uint16_t paddr_l;287 uint16_t p_per;288 uint16_t _rfbd_ptr;289 uint16_t _tfbd_ptr;290 uint16_t _tlbd_ptr;291 uint32_t _tbuf1data0;292 uint32_t _tbuf1data1;293 uint32_t _tbuf1rba0;294 uint32_t _tbuf1crc;295 uint16_t _tbuf1bcnt;296 uint16_t _tx_len;297 uint16_t iaddr1;298 uint16_t iaddr2;299 uint16_t iaddr3;300 uint16_t iaddr4;301 uint16_t _boff_cnt;302 uint16_t taddr_h;303 uint16_t taddr_m;304 uint16_t taddr_l;305 } ethernet;306 struct {307 uint32_t crc_p;308 uint32_t crc_c;309 } transparent;310 } un;311 } m360SCCENparms_t;312 313 /*314 * Receive and transmit function code register bits315 * These apply to the function code registers of all devices, not just SCC.316 */317 #define M360_RFCR_MOT (1<<4)318 #define M360_RFCR_DMA_SPACE 0x8319 #define M360_TFCR_MOT (1<<4)320 #define M360_TFCR_DMA_SPACE 0x8321 322 /*323 *************************************************************************324 * Serial Management Controllers *325 *************************************************************************326 */327 typedef struct m360SMCparms_ {328 uint16_t rbase;329 uint16_t tbase;330 uint8_t rfcr;331 uint8_t tfcr;332 uint16_t mrblr;333 uint32_t _rstate;334 uint32_t _pad0;335 uint16_t _rbptr;336 uint16_t _pad1;337 uint32_t _pad2;338 uint32_t _tstate;339 uint32_t _pad3;340 uint16_t _tbptr;341 uint16_t _pad4;342 uint32_t _pad5;343 union {344 struct {345 uint16_t max_idl;346 uint16_t _pad0;347 uint16_t brklen;348 uint16_t brkec;349 uint16_t brkcr;350 uint16_t _r_mask;351 } uart;352 struct {353 uint16_t _pad0[5];354 } transparent;355 } un;356 } m360SMCparms_t;357 358 /*359 * Mode register360 */361 #define M360_SMCMR_CLEN(x) ((x)<<11) /* Character length */362 #define M360_SMCMR_2STOP (1<<10) /* 2 stop bits */363 #define M360_SMCMR_PARITY (1<<9) /* Enable parity */364 #define M360_SMCMR_EVEN (1<<8) /* Even parity */365 #define M360_SMCMR_SM_GCI (0<<4) /* GCI Mode */366 #define M360_SMCMR_SM_UART (2<<4) /* UART Mode */367 #define M360_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */368 #define M360_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */369 #define M360_SMCMR_DM_ECHO (2<<2) /* Echo mode */370 #define M360_SMCMR_TEN (1<<1) /* Enable transmitter */371 #define M360_SMCMR_REN (1<<0) /* Enable receiver */372 373 /*374 * Event and mask registers (SMCE, SMCM)375 */376 #define M360_SMCE_BRK (1<<4)377 #define M360_SMCE_BSY (1<<2)378 #define M360_SMCE_TX (1<<1)379 #define M360_SMCE_RX (1<<0)380 381 /*382 *************************************************************************383 * Serial Peripheral Interface *384 *************************************************************************385 */386 typedef struct m360SPIparms_ {387 uint16_t rbase;388 uint16_t tbase;389 uint8_t rfcr;390 uint8_t tfcr;391 uint16_t mrblr;392 uint32_t _rstate;393 uint32_t _pad0;394 uint16_t _rbptr;395 uint16_t _pad1;396 uint32_t _pad2;397 uint32_t _tstate;398 uint32_t _pad3;399 uint16_t _tbptr;400 uint16_t _pad4;401 uint32_t _pad5;402 } m360SPIparms_t;403 404 /*405 * Mode register (SPMODE)406 */407 #define M360_SPMODE_LOOP (1<<14) /* Local loopback mode */408 #define M360_SPMODE_CI (1<<13) /* Clock invert */409 #define M360_SPMODE_CP (1<<12) /* Clock phase */410 #define M360_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */411 #define M360_SPMODE_REV (1<<10) /* Reverse data */412 #define M360_SPMODE_MASTER (1<<9) /* SPI is master */413 #define M360_SPMODE_EN (1<<8) /* Enable SPI */414 #define M360_SPMODE_CLEN(x) ((x)<<4) /* Character length */415 #define M360_SPMODE_PM(x) (x) /* Prescaler modulus */416 417 /*418 * Mode register (SPCOM)419 */420 #define M360_SPCOM_STR (1<<7) /* Start transmit */421 422 /*423 * Event and mask registers (SPIE, SPIM)424 */425 #define M360_SPIE_MME (1<<5) /* Multi-master error */426 #define M360_SPIE_TXE (1<<4) /* Tx error */427 #define M360_SPIE_BSY (1<<2) /* Busy condition*/428 #define M360_SPIE_TXB (1<<1) /* Tx buffer */429 #define M360_SPIE_RXB (1<<0) /* Rx buffer */430 431 /*432 *************************************************************************433 * SDMA (SCC, SMC, SPI) Buffer Descriptors *434 *************************************************************************435 */436 typedef struct m360BufferDescriptor_ {437 uint16_t status;438 uint16_t length;439 uint32_t buffer; /* this is a void * to the 360 */440 } m360BufferDescriptor_t;441 442 /*443 * Bits in receive buffer descriptor status word444 */445 #define M360_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */446 #define M360_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */447 #define M360_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */448 #define M360_BD_LAST (1<<11) /* Ethernet, SPI */449 #define M360_BD_CONTROL_CHAR (1<<11) /* SCC UART */450 #define M360_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */451 #define M360_BD_ADDRESS (1<<10) /* SCC UART */452 #define M360_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */453 #define M360_BD_MISS (1<<8) /* Ethernet */454 #define M360_BD_IDLE (1<<8) /* SCC UART, SMC UART */455 #define M360_BD_ADDRSS_MATCH (1<<7) /* SCC UART */456 #define M360_BD_LONG (1<<5) /* Ethernet */457 #define M360_BD_BREAK (1<<5) /* SCC UART, SMC UART */458 #define M360_BD_NONALIGNED (1<<4) /* Ethernet */459 #define M360_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */460 #define M360_BD_SHORT (1<<3) /* Ethernet */461 #define M360_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */462 #define M360_BD_CRC_ERROR (1<<2) /* Ethernet */463 #define M360_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */464 #define M360_BD_COLLISION (1<<0) /* Ethernet */465 #define M360_BD_CARRIER_LOST (1<<0) /* SCC UART */466 #define M360_BD_MASTER_ERROR (1<<0) /* SPI */467 468 /*469 * Bits in transmit buffer descriptor status word470 * Many bits have the same meaning as those in receiver buffer descriptors.471 */472 #define M360_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */473 #define M360_BD_PAD (1<<14) /* Ethernet */474 #define M360_BD_CTS_REPORT (1<<11) /* SCC UART */475 #define M360_BD_TX_CRC (1<<10) /* Ethernet */476 #define M360_BD_DEFER (1<<9) /* Ethernet */477 #define M360_BD_HEARTBEAT (1<<8) /* Ethernet */478 #define M360_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */479 #define M360_BD_LATE_COLLISION (1<<7) /* Ethernet */480 #define M360_BD_NO_STOP_BIT (1<<7) /* SCC UART */481 #define M360_BD_RETRY_LIMIT (1<<6) /* Ethernet */482 #define M360_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */483 #define M360_BD_UNDERRUN (1<<1) /* Ethernet, SPI */484 #define M360_BD_CARRIER_LOST (1<<0) /* Ethernet */485 #define M360_BD_CTS_LOST (1<<0) /* SCC UART */486 487 /*488 *************************************************************************489 * IDMA Buffer Descriptors *490 *************************************************************************491 */492 typedef struct m360IDMABufferDescriptor_ {493 uint16_t status;494 uint16_t _pad;495 uint32_t length;496 void *source;497 void *destination;498 } m360IDMABufferDescriptor_t;499 500 /*501 *************************************************************************502 * RISC Communication Processor Module Command Register (CR) *503 *************************************************************************504 */505 #define M360_CR_RST (1<<15) /* Reset communication processor */506 #define M360_CR_OP_INIT_RX_TX (0<<8) /* SCC, SMC UART, SMC GCI, SPI */507 #define M360_CR_OP_INIT_RX (1<<8) /* SCC, SMC UART, SPI */508 #define M360_CR_OP_INIT_TX (2<<8) /* SCC, SMC UART, SPI */509 #define M360_CR_OP_INIT_HUNT (3<<8) /* SCC, SMC UART */510 #define M360_CR_OP_STOP_TX (4<<8) /* SCC, SMC UART */511 #define M360_CR_OP_GR_STOP_TX (5<<8) /* SCC */512 #define M360_CR_OP_INIT_IDMA (5<<8) /* IDMA */513 #define M360_CR_OP_RESTART_TX (6<<8) /* SCC, SMC UART */514 #define M360_CR_OP_CLOSE_RX_BD (7<<8) /* SCC, SMC UART, SPI */515 #define M360_CR_OP_SET_GRP_ADDR (8<<8) /* SCC */516 #define M360_CR_OP_SET_TIMER (8<<8) /* Timer */517 #define M360_CR_OP_GCI_TIMEOUT (9<<8) /* SMC GCI */518 #define M360_CR_OP_RESERT_BCS (10<<8) /* SCC */519 #define M360_CR_OP_GCI_ABORT (10<<8) /* SMC GCI */520 #define M360_CR_CHAN_SCC1 (0<<4) /* Channel selection */521 #define M360_CR_CHAN_SCC2 (4<<4)522 #define M360_CR_CHAN_SPI (5<<4)523 #define M360_CR_CHAN_TIMER (5<<4)524 #define M360_CR_CHAN_SCC3 (8<<4)525 #define M360_CR_CHAN_SMC1 (9<<4)526 #define M360_CR_CHAN_IDMA1 (9<<4)527 #define M360_CR_CHAN_SCC4 (12<<4)528 #define M360_CR_CHAN_SMC2 (13<<4)529 #define M360_CR_CHAN_IDMA2 (13<<4)530 #define M360_CR_FLG (1<<0) /* Command flag */531 532 /*533 *************************************************************************534 * System Protection Control Register (SYPCR) *535 *************************************************************************536 */537 #define M360_SYPCR_SWE (1<<7) /* Software watchdog enable */538 #define M360_SYPCR_SWRI (1<<6) /* Software watchdog reset select */539 #define M360_SYPCR_SWT1 (1<<5) /* Software watchdog timing bit 1 */540 #define M360_SYPCR_SWT0 (1<<4) /* Software watchdog timing bit 0 */541 #define M360_SYPCR_DBFE (1<<3) /* Double bus fault monitor enable */542 #define M360_SYPCR_BME (1<<2) /* Bus monitor external enable */543 #define M360_SYPCR_BMT1 (1<<1) /* Bus monitor timing bit 1 */544 #define M360_SYPCR_BMT0 (1<<0) /* Bus monitor timing bit 0 */545 546 /*547 *************************************************************************548 * Memory Control Registers *549 *************************************************************************550 */551 #define M360_GMR_RCNT(x) ((x)<<24) /* Refresh count */552 #define M360_GMR_RFEN (1<<23) /* Refresh enable */553 #define M360_GMR_RCYC(x) ((x)<<21) /* Refresh cycle length */554 #define M360_GMR_PGS(x) ((x)<<18) /* Page size */555 #define M360_GMR_DPS_32BIT (0<<16) /* DRAM port size */556 #define M360_GMR_DPS_16BIT (1<<16)557 #define M360_GMR_DPS_8BIT (2<<16)558 #define M360_GMR_DPS_DSACK (3<<16)559 #define M360_GMR_WBT40 (1<<15) /* Wait between 040 transfers */560 #define M360_GMR_WBTQ (1<<14) /* Wait between 360 transfers */561 #define M360_GMR_SYNC (1<<13) /* Synchronous external access */562 #define M360_GMR_EMWS (1<<12) /* External master wait state */563 #define M360_GMR_OPAR (1<<11) /* Odd parity */564 #define M360_GMR_PBEE (1<<10) /* Parity bus error enable */565 #define M360_GMR_TSS40 (1<<9) /* TS* sample for 040 */566 #define M360_GMR_NCS (1<<8) /* No CPU space */567 #define M360_GMR_DWQ (1<<7) /* Delay write for 360 */568 #define M360_GMR_DW40 (1<<6) /* Delay write for 040 */569 #define M360_GMR_GAMX (1<<5) /* Global address mux enable */570 571 #define M360_MEMC_BR_FC(x) ((x)<<7) /* Function code limit */572 #define M360_MEMC_BR_TRLXQ (1<<6) /* Relax timing requirements */573 #define M360_MEMC_BR_BACK40 (1<<5) /* Burst acknowledge to 040 */574 #define M360_MEMC_BR_CSNT40 (1<<4) /* CS* negate timing for 040 */575 #define M360_MEMC_BR_CSNTQ (1<<3) /* CS* negate timing for 360 */576 #define M360_MEMC_BR_PAREN (1<<2) /* Enable parity checking */577 #define M360_MEMC_BR_WP (1<<1) /* Write Protect */578 #define M360_MEMC_BR_V (1<<0) /* Base/Option register are valid */579 580 #define M360_MEMC_OR_TCYC(x) ((x)<<28) /* Cycle length (clocks) */581 #define M360_MEMC_OR_WAITS(x) M360_MEMC_OR_TCYC((x)+1)582 #define M360_MEMC_OR_2KB 0x0FFFF800 /* Address range */583 #define M360_MEMC_OR_4KB 0x0FFFF000584 #define M360_MEMC_OR_8KB 0x0FFFE000585 #define M360_MEMC_OR_16KB 0x0FFFC000586 #define M360_MEMC_OR_32KB 0x0FFF8000587 #define M360_MEMC_OR_64KB 0x0FFF0000588 #define M360_MEMC_OR_128KB 0x0FFE0000589 #define M360_MEMC_OR_256KB 0x0FFC0000590 #define M360_MEMC_OR_512KB 0x0FF80000591 #define M360_MEMC_OR_1MB 0x0FF00000592 #define M360_MEMC_OR_2MB 0x0FE00000593 #define M360_MEMC_OR_4MB 0x0FC00000594 #define M360_MEMC_OR_8MB 0x0F800000595 #define M360_MEMC_OR_16MB 0x0F000000596 #define M360_MEMC_OR_32MB 0x0E000000597 #define M360_MEMC_OR_64MB 0x0C000000598 #define M360_MEMC_OR_128MB 0x08000000599 #define M360_MEMC_OR_256MB 0x00000000600 #define M360_MEMC_OR_FCMC(x) ((x)<<7) /* Function code mask */601 #define M360_MEMC_OR_BCYC(x) ((x)<<5) /* Burst cycle length (clocks) */602 #define M360_MEMC_OR_PGME (1<<3) /* Page mode enable */603 #define M360_MEMC_OR_32BIT (0<<1) /* Port size */604 #define M360_MEMC_OR_16BIT (1<<1)605 #define M360_MEMC_OR_8BIT (2<<1)606 #define M360_MEMC_OR_DSACK (3<<1)607 #define M360_MEMC_OR_DRAM (1<<0) /* Dynamic RAM select */608 609 /*610 *************************************************************************611 * SI Mode Register (SIMODE) *612 *************************************************************************613 */614 #define M360_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */615 #define M360_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */616 #define M360_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */617 #define M360_SI_SMC2_BRG2 (1<<28)618 #define M360_SI_SMC2_BRG3 (2<<28)619 #define M360_SI_SMC2_BRG4 (3<<28)620 #define M360_SI_SMC2_CLK5 (0<<28)621 #define M360_SI_SMC2_CLK6 (1<<28)622 #define M360_SI_SMC2_CLK7 (2<<28)623 #define M360_SI_SMC2_CLK8 (3<<28)624 #define M360_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */625 #define M360_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */626 #define M360_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */627 #define M360_SI_SMC1_BRG2 (1<<12)628 #define M360_SI_SMC1_BRG3 (2<<12)629 #define M360_SI_SMC1_BRG4 (3<<12)630 #define M360_SI_SMC1_CLK1 (0<<12)631 #define M360_SI_SMC1_CLK2 (1<<12)632 #define M360_SI_SMC1_CLK3 (2<<12)633 #define M360_SI_SMC1_CLK4 (3<<12)634 635 /*636 *************************************************************************637 * SDMA Configuration Register (SDMA) *638 *************************************************************************639 */640 #define M360_SDMA_FREEZE (2<<13) /* Freeze on next bus cycle */641 #define M360_SDMA_SISM_7 (7<<8) /* Normal interrupt service mask */642 #define M360_SDMA_SAID_4 (4<<4) /* Normal arbitration ID */643 #define M360_SDMA_INTE (1<<1) /* SBER interrupt enable */644 #define M360_SDMA_INTB (1<<0) /* SBKP interrupt enable */645 646 /*647 *************************************************************************648 * Baud (sic) Rate Generators *649 *************************************************************************650 */651 #define M360_BRG_RST (1<<17) /* Reset generator */652 #define M360_BRG_EN (1<<16) /* Enable generator */653 #define M360_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */654 #define M360_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */655 #define M360_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */656 #define M360_BRG_ATB (1<<13) /* Autobaud */657 #define M360_BRG_115200 (13<<1) /* Assume 25 MHz clock */658 #define M360_BRG_57600 (26<<1)659 #define M360_BRG_38400 (40<<1)660 #define M360_BRG_19200 (80<<1)661 #define M360_BRG_9600 (162<<1)662 #define M360_BRG_4800 (324<<1)663 #define M360_BRG_2400 (650<<1)664 #define M360_BRG_1200 (1301<<1)665 #define M360_BRG_600 (2603<<1)666 #define M360_BRG_300 ((324<<1) | 1)667 #define M360_BRG_150 ((650<<1) | 1)668 #define M360_BRG_75 ((1301<<1) | 1)669 670 /*671 *************************************************************************672 * sccm Bit Settings *673 *************************************************************************674 */675 #define M360_SCCE_TX 0x02676 #define M360_SCCE_RX 0x01677 678 #define M360_CR_INIT_TX_RX_PARAMS 0x0000679 #define M360_CR_CH_NUM 0x0040680 681 #define M360_NUM_DPRAM_REAGONS 4682 /*683 *************************************************************************684 * MC68360 DUAL-PORT RAM AND REGISTERS *685 *************************************************************************686 */687 typedef struct m360_ {688 /*689 * Dual-port RAM690 */691 volatile uint8_t dpram0[0x400]; /* Microcode program */692 volatile uint8_t dpram1[0x200];693 volatile uint8_t dpram2[0x100]; /* Microcode scratch */694 volatile uint8_t dpram3[0x100]; /* Not on REV A or B masks */695 volatile uint8_t _rsv0[0xC00-0x800];696 volatile m360SCCENparms_t scc1p;697 volatile uint8_t _rsv1[0xCB0-0xC00-sizeof(m360SCCENparms_t)];698 volatile m360MiscParms_t miscp;699 volatile uint8_t _rsv2[0xD00-0xCB0-sizeof(m360MiscParms_t)];700 volatile m360SCCparms_t scc2p;701 volatile uint8_t _rsv3[0xD80-0xD00-sizeof(m360SCCparms_t)];702 volatile m360SPIparms_t spip;703 volatile uint8_t _rsv4[0xDB0-0xD80-sizeof(m360SPIparms_t)];704 volatile m360TimerParms_t tmp;705 volatile uint8_t _rsv5[0xE00-0xDB0-sizeof(m360TimerParms_t)];706 volatile m360SCCparms_t scc3p;707 volatile uint8_t _rsv6[0xE70-0xE00-sizeof(m360SCCparms_t)];708 volatile m360IDMAparms_t idma1p;709 volatile uint8_t _rsv7[0xE80-0xE70-sizeof(m360IDMAparms_t)];710 volatile m360SMCparms_t smc1p;711 volatile uint8_t _rsv8[0xF00-0xE80-sizeof(m360SMCparms_t)];712 volatile m360SCCparms_t scc4p;713 volatile uint8_t _rsv9[0xF70-0xF00-sizeof(m360SCCparms_t)];714 volatile m360IDMAparms_t idma2p;715 volatile uint8_t _rsv10[0xF80-0xF70-sizeof(m360IDMAparms_t)];716 volatile m360SMCparms_t smc2p;717 volatile uint8_t _rsv11[0x1000-0xF80-sizeof(m360SMCparms_t)];718 719 /*720 * SIM Block721 */722 volatile uint32_t mcr;723 volatile uint32_t _pad00;724 volatile uint8_t avr;725 volatile uint8_t rsr;726 volatile uint16_t _pad01;727 volatile uint8_t clkocr;728 volatile uint8_t _pad02;729 volatile uint16_t _pad03;730 volatile uint16_t pllcr;731 volatile uint16_t _pad04;732 volatile uint16_t cdvcr;733 volatile uint16_t pepar;734 volatile uint32_t _pad05[2];735 volatile uint16_t _pad06;736 volatile uint8_t sypcr;737 volatile uint8_t swiv;738 volatile uint16_t _pad07;739 volatile uint16_t picr;740 volatile uint16_t _pad08;741 volatile uint16_t pitr;742 volatile uint16_t _pad09;743 volatile uint8_t _pad10;744 volatile uint8_t swsr;745 volatile uint32_t bkar;746 volatile uint32_t bcar;747 volatile uint32_t _pad11[2];748 749 /*750 * MEMC Block751 */752 volatile uint32_t gmr;753 volatile uint16_t mstat;754 volatile uint16_t _pad12;755 volatile uint32_t _pad13[2];756 volatile m360MEMCRegisters_t memc[8];757 volatile uint8_t _pad14[0xF0-0xD0];758 volatile uint8_t _pad15[0x100-0xF0];759 volatile uint8_t _pad16[0x500-0x100];760 761 /*762 * IDMA1 Block763 */764 volatile uint16_t iccr;765 volatile uint16_t _pad17;766 volatile uint16_t cmr1;767 volatile uint16_t _pad18;768 volatile uint32_t sapr1;769 volatile uint32_t dapr1;770 volatile uint32_t bcr1;771 volatile uint8_t fcr1;772 volatile uint8_t _pad19;773 volatile uint8_t cmar1;774 volatile uint8_t _pad20;775 volatile uint8_t csr1;776 volatile uint8_t _pad21;777 volatile uint16_t _pad22;778 779 /*780 * SDMA Block781 */782 volatile uint8_t sdsr;783 volatile uint8_t _pad23;784 volatile uint16_t sdcr;785 volatile uint32_t sdar;786 787 /*788 * IDMA2 Block789 */790 volatile uint16_t _pad24;791 volatile uint16_t cmr2;792 volatile uint32_t sapr2;793 volatile uint32_t dapr2;794 volatile uint32_t bcr2;795 volatile uint8_t fcr2;796 volatile uint8_t _pad26;797 volatile uint8_t cmar2;798 volatile uint8_t _pad27;799 volatile uint8_t csr2;800 volatile uint8_t _pad28;801 volatile uint16_t _pad29;802 volatile uint32_t _pad30;803 804 /*805 * CPIC Block806 */807 volatile uint32_t cicr;808 volatile uint32_t cipr;809 volatile uint32_t cimr;810 volatile uint32_t cisr;811 812 /*813 * Parallel I/O Block814 */815 volatile uint16_t padir;816 volatile uint16_t papar;817 volatile uint16_t paodr;818 volatile uint16_t padat;819 volatile uint32_t _pad31[2];820 volatile uint16_t pcdir;821 volatile uint16_t pcpar;822 volatile uint16_t pcso;823 volatile uint16_t pcdat;824 volatile uint16_t pcint;825 volatile uint16_t _pad32;826 volatile uint32_t _pad33[5];827 828 /*829 * TIMER Block830 */831 volatile uint16_t tgcr;832 volatile uint16_t _pad34;833 volatile uint32_t _pad35[3];834 volatile uint16_t tmr1;835 volatile uint16_t tmr2;836 volatile uint16_t trr1;837 volatile uint16_t trr2;838 volatile uint16_t tcr1;839 volatile uint16_t tcr2;840 volatile uint16_t tcn1;841 volatile uint16_t tcn2;842 volatile uint16_t tmr3;843 volatile uint16_t tmr4;844 volatile uint16_t trr3;845 volatile uint16_t trr4;846 volatile uint16_t tcr3;847 volatile uint16_t tcr4;848 volatile uint16_t tcn3;849 volatile uint16_t tcn4;850 volatile uint16_t ter1;851 volatile uint16_t ter2;852 volatile uint16_t ter3;853 volatile uint16_t ter4;854 volatile uint32_t _pad36[2];855 856 /*857 * CP Block858 */859 volatile uint16_t cr;860 volatile uint16_t _pad37;861 volatile uint16_t rccr;862 volatile uint16_t _pad38;863 volatile uint32_t _pad39[3];864 volatile uint16_t _pad40;865 volatile uint16_t rter;866 volatile uint16_t _pad41;867 volatile uint16_t rtmr;868 volatile uint32_t _pad42[5];869 870 /*871 * BRG Block872 */873 volatile uint32_t brgc1;874 volatile uint32_t brgc2;875 volatile uint32_t brgc3;876 volatile uint32_t brgc4;877 878 /*879 * SCC Block880 */881 volatile m360SCCRegisters_t scc1;882 volatile m360SCCRegisters_t scc2;883 volatile m360SCCRegisters_t scc3;884 volatile m360SCCRegisters_t scc4;885 886 /*887 * SMC Block888 */889 volatile m360SMCRegisters_t smc1;890 volatile m360SMCRegisters_t smc2;891 892 /*893 * SPI Block894 */895 volatile uint16_t spmode;896 volatile uint16_t _pad43[2];897 volatile uint8_t spie;898 volatile uint8_t _pad44;899 volatile uint16_t _pad45;900 volatile uint8_t spim;901 volatile uint8_t _pad46[2];902 volatile uint8_t spcom;903 volatile uint16_t _pad47[2];904 905 /*906 * PIP Block907 */908 volatile uint16_t pipc;909 volatile uint16_t _pad48;910 volatile uint16_t ptpr;911 volatile uint32_t pbdir;912 volatile uint32_t pbpar;913 volatile uint16_t _pad49;914 volatile uint16_t pbodr;915 volatile uint32_t pbdat;916 volatile uint32_t _pad50[6];917 918 /*919 * SI Block920 */921 volatile uint32_t simode;922 volatile uint8_t sigmr;923 volatile uint8_t _pad51;924 volatile uint8_t sistr;925 volatile uint8_t sicmr;926 volatile uint32_t _pad52;927 volatile uint32_t sicr;928 volatile uint16_t _pad53;929 volatile uint16_t sirp[2];930 volatile uint16_t _pad54;931 volatile uint32_t _pad55[2];932 volatile uint8_t siram[256];933 } m360_t;934 935 struct bdregions_t {936 volatile unsigned char *base;937 unsigned int size;938 unsigned int used;939 };940 941 #define M68360_RX_BUF_SIZE 1942 #define M68360_TX_BUF_SIZE 0x100943 944 struct _m68360_per_chip;945 typedef struct _m68360_per_chip *M68360_t;946 947 typedef struct _m68360_per_port {948 uint32_t channel;949 M68360_t chip;950 volatile uint32_t *pBRGC; /* m360->brgc# */951 volatile m360SCCparms_t *pSCCB; /* m360->scc#p */952 volatile m360SCCRegisters_t *pSCCR; /* m360->scc# */953 uint32_t baud;954 int minor;955 volatile uint8_t *rxBuf;956 volatile uint8_t *txBuf;957 volatile m360BufferDescriptor_t *sccRxBd;958 volatile m360BufferDescriptor_t *sccTxBd;959 }m68360_per_port_t, *M68360_serial_ports_t;960 961 typedef struct _m68360_per_chip {962 struct _m68360_per_chip *next;963 struct bdregions_t bdregions[4];964 volatile m360_t *m360; /* Pointer to base Address */965 int m360_interrupt;966 int m360_clock_rate;967 PPMCQ1BoardData board_data;968 m68360_per_port_t port[4];969 } m68360_per_chip_t;970 971 extern M68360_t M68360_chips;972 973 void M360SetupMemory( M68360_t ptr );974 void *M360AllocateBufferDescriptors (M68360_t ptr, int count);975 void M360ExecuteRISC( volatile m360_t *m360, uint16_t command);976 int mc68360_scc_create_chip( PPMCQ1BoardData BoardData, uint8_t int_vector );977 978 #endif /* __MC68360_h */ -
deleted file c/src/lib/libbsp/powerpc/ep1a/console/mc68360_scc.c
diff --git a/c/src/lib/libbsp/powerpc/ep1a/console/mc68360_scc.c b/c/src/lib/libbsp/powerpc/ep1a/console/mc68360_scc.c deleted file mode 100644 index b2dab2b..0000000
+ - 1 /* This file contains the termios TTY driver for the2 * Motorola MC68360 SCC ports.3 */4 5 /*6 * COPYRIGHT (c) 1989-2008.7 * On-Line Applications Research Corporation (OAR).8 *9 * The license and distribution terms for this file may be10 * found in the file LICENSE in this distribution or at11 * http://www.rtems.org/license/LICENSE.12 */13 14 #include <stdio.h>15 #include <termios.h>16 #include <bsp.h>17 #include <libcpu/io.h>18 #include <rtems/libio.h>19 #include <bsp/pci.h>20 #include <bsp/irq.h>21 #include <libchip/serial.h>22 #include "m68360.h"23 #include <libchip/sersupp.h>24 #include <stdlib.h>25 #include <rtems/bspIo.h>26 #include <string.h>27 28 /* #define DEBUG_360 */29 30 #if 1 /* XXX */31 int EP1A_READ_LENGTH_GREATER_THAN_1 = 0;32 33 #define MC68360_LENGTH_SIZE 40034 int mc68360_length_array[ MC68360_LENGTH_SIZE ];35 int mc68360_length_count=0;36 #endif37 38 39 M68360_t M68360_chips = NULL;40 41 #define SYNC eieio42 #define mc68360_scc_Is_422( _minor ) \43 (Console_Port_Tbl[minor]->sDeviceName[7] == '4' )44 45 static void scc_write8(46 const char *name,47 volatile uint8_t *address,48 uint8_t value49 )50 {51 #ifdef DEBUG_36052 printk( "WR8 %s 0x%08x 0x%02x\n", name, address, value );53 #endif54 *address = value;55 }56 57 static uint16_t scc_read16(58 const char *name,59 volatile uint16_t *address60 )61 {62 uint16_t value;63 64 #ifdef DEBUG_36065 printk( "RD16 %s 0x%08x ", name, address );66 #endif67 value = *address;68 #ifdef DEBUG_36069 printk( "0x%04x\n", value );70 #endif71 72 return value;73 }74 75 static void scc_write16(76 const char *name,77 volatile uint16_t *address,78 uint16_t value79 )80 {81 #ifdef DEBUG_36082 printk( "WR16 %s 0x%08x 0x%04x\n", name, address, value );83 #endif84 *address = value;85 }86 87 static uint32_t scc_read32(88 const char *name,89 volatile uint32_t *address90 )91 {92 uint32_t value;93 94 #ifdef DEBUG_36095 printk( "RD32 %s 0x%08x ", name, address );96 #endif97 value = *address;98 #ifdef DEBUG_36099 printk( "0x%08x\n", value );100 #endif101 102 return value;103 }104 105 static void scc_write32(106 const char *name,107 volatile uint32_t *address,108 uint32_t value109 )110 {111 #ifdef DEBUG_360112 printk( "WR32 %s 0x%08x 0x%08x\n", name, address, value );113 #endif114 *address = value;115 }116 117 #define TX_BUFFER_ADDRESS( _ptr ) \118 ((char *)ptr->txBuf - (char *)ptr->chip->board_data->baseaddr)119 #define RX_BUFFER_ADDRESS( _ptr ) \120 ((char *)ptr->rxBuf - (char *)ptr->chip->board_data->baseaddr)121 122 123 /**************************************************************************124 * Function: mc68360_sccBRGC *125 **************************************************************************126 * Description: *127 * *128 * This function is called to compute the divisor register values for *129 * a given baud rate. *130 * *131 * *132 * Inputs: *133 * *134 * int baud - Baud rate (in bps). *135 * *136 * Output: *137 * *138 * int - baud rate generator configuration. *139 * *140 **************************************************************************/141 static int142 mc68360_sccBRGC(int baud, int m360_clock_rate)143 {144 int data;145 146 /*147 * configure baud rate generator for 16x bit rate, where.....148 * b = desired baud rate149 * clk = system clock (33mhz)150 * d = clock dividor value151 *152 * for b > 300 : d = clk/(b*16)153 * for b<= 300 : d = (clk/ (b*16*16))-1)154 */155 156 SYNC();157 if( baud > 300 ) data = 33333333 / (baud * 16 );158 else data = (33333333 / (baud * 16 * 16) ) - 1;159 data *= 2;160 data &= 0x00001ffe ;161 162 /* really data = 0x010000 | data | ((baud>300)? 0 : 1 ) ; */163 data |= ((baud>300)? 0 : 1 ) ;164 data |= 0x010000 ;165 166 return data;167 }168 169 170 /*171 * sccInterruptHandler172 *173 * This is the interrupt service routine for the console UART. It174 * handles both receive and transmit interrupts. The bulk of the175 * work is done by termios.176 *177 */178 static void mc68360_sccInterruptHandler( M68360_t chip )179 {180 volatile m360_t *m360;181 int port;182 uint16_t status;183 uint16_t length;184 int i;185 char data;186 int clear_isr;187 188 189 #ifdef DEBUG_360190 printk("mc68360_sccInterruptHandler\n");191 #endif192 for (port=0; port<4; port++) {193 194 clear_isr = FALSE;195 m360 = chip->m360;196 197 /*198 * XXX - Can we add something here to check if this is our interrupt.199 * XXX - We need a parameter here so that we know which 360 instead of200 * looping through them all!201 */202 203 /*204 * Handle a RX interrupt.205 */206 if ( scc_read16("scce", &chip->port[port].pSCCR->scce) & 0x1)207 {208 clear_isr = TRUE;209 scc_write16("scce", &chip->port[port].pSCCR->scce, 0x1 );210 status =scc_read16( "sccRxBd->status", &chip->port[port].sccRxBd->status);211 while ((status & M360_BD_EMPTY) == 0)212 {213 length= scc_read16("sccRxBd->length",&chip->port[port].sccRxBd->length);214 if (length > 1)215 EP1A_READ_LENGTH_GREATER_THAN_1 = length;216 217 for (i=0;i<length;i++) {218 data= chip->port[port].rxBuf[i];219 rtems_termios_enqueue_raw_characters(220 Console_Port_Data[ chip->port[port].minor ].termios_data,221 &data,222 1);223 }224 scc_write16( "sccRxBd->status", &chip->port[port].sccRxBd->status,225 M360_BD_EMPTY | M360_BD_WRAP | M360_BD_INTERRUPT );226 status =scc_read16( "sccRxBd->status", &chip->port[port].sccRxBd->status);227 }228 }229 230 /*231 * Handle a TX interrupt.232 */233 if (scc_read16("scce", &chip->port[port].pSCCR->scce) & 0x2)234 {235 clear_isr = TRUE;236 scc_write16("scce", &chip->port[port].pSCCR->scce, 0x2);237 status = scc_read16("sccTxBd->status", &chip->port[port].sccTxBd->status);238 if ((status & M360_BD_EMPTY) == 0)239 {240 scc_write16("sccTxBd->status",&chip->port[port].sccTxBd->status,0);241 #if 1242 rtems_termios_dequeue_characters(243 Console_Port_Data[chip->port[port].minor].termios_data,244 chip->port[port].sccTxBd->length);245 #else246 mc68360_scc_write_support_int(chip->port[port].minor,"*****", 5);247 #endif248 }249 }250 251 /*252 * Clear SCC interrupt-in-service bit.253 */254 if ( clear_isr )255 scc_write32( "cisr", &m360->cisr, (0x80000000 >> chip->port[port].channel) );256 }257 }258 259 /*260 * mc68360_scc_open261 *262 * This function opens a port for communication.263 *264 * Default state is 9600 baud, 8 bits, No parity, and 1 stop bit.265 */266 static int mc68360_scc_open(267 int major,268 int minor,269 void * arg270 )271 {272 M68360_serial_ports_t ptr;273 uint32_t data;274 275 #ifdef DEBUG_360276 printk("mc68360_scc_open %d\n", minor);277 #endif278 279 ptr = Console_Port_Tbl[minor]->pDeviceParams;280 281 /*282 * Enable the receiver and the transmitter.283 */284 SYNC();285 data = scc_read32( "pSCCR->gsmr_l", &ptr->pSCCR->gsmr_l);286 scc_write32( "pSCCR->gsmr_l", &ptr->pSCCR->gsmr_l,287 (data | M360_GSMR_ENR | M360_GSMR_ENT) );288 289 data = PMCQ1_Read_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_INT_MASK );290 data &= (~PMCQ1_INT_MASK_QUICC);291 PMCQ1_Write_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_INT_MASK, data );292 293 data = PMCQ1_Read_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_INT_STATUS );294 data &= (~PMCQ1_INT_STATUS_QUICC);295 PMCQ1_Write_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_INT_STATUS, data );296 297 return RTEMS_SUCCESSFUL;298 }299 300 static uint32_t mc68360_scc_calculate_pbdat( M68360_t chip )301 {302 uint32_t i;303 uint32_t pbdat_data;304 int minor;305 uint32_t type422data[4] = {306 0x00440, 0x00880, 0x10100, 0x20200307 };308 309 pbdat_data = 0x3;310 for (i=0; i<4; i++) {311 minor = chip->port[i].minor;312 if mc68360_scc_Is_422( minor )313 pbdat_data |= type422data[i];314 }315 316 return pbdat_data;317 }318 319 /*320 * mc68360_scc_initialize_interrupts321 *322 * This routine initializes the console's receive and transmit323 * ring buffers and loads the appropriate vectors to handle the interrupts.324 */325 static void mc68360_scc_initialize_interrupts(int minor)326 {327 M68360_serial_ports_t ptr;328 volatile m360_t *m360;329 uint32_t data;330 uint32_t buffers_start;331 uint32_t tmp_u32;332 333 #ifdef DEBUG_360334 printk("mc68360_scc_initialize_interrupts: minor %d\n", minor );335 printk("Console_Port_Tbl[minor]->pDeviceParams 0x%08x\n",336 Console_Port_Tbl[minor]->pDeviceParams );337 #endif338 339 ptr = Console_Port_Tbl[minor]->pDeviceParams;340 m360 = ptr->chip->m360;341 342 #ifdef DEBUG_360343 printk("m360 0x%08x baseaddr 0x%08x\n",344 m360, ptr->chip->board_data->baseaddr);345 #endif346 347 buffers_start = ptr->chip->board_data->baseaddr + 0x00200000 +348 ( (M68360_RX_BUF_SIZE + M68360_TX_BUF_SIZE) * (ptr->channel-1));349 ptr->rxBuf = (uint8_t *) buffers_start;350 ptr->txBuf = (uint8_t *)(buffers_start + M68360_RX_BUF_SIZE);351 #ifdef DEBUG_360352 printk("rxBuf 0x%08x txBuf 0x%08x\n", ptr->rxBuf, ptr->txBuf );353 #endif354 /*355 * Set Channel Drive Enable bits in EPLD356 */357 data = PMCQ1_Read_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_DRIVER_ENABLE );358 SYNC();359 data = data & ~(PMCQ1_DRIVER_ENABLE_3 | PMCQ1_DRIVER_ENABLE_2 |360 PMCQ1_DRIVER_ENABLE_1 | PMCQ1_DRIVER_ENABLE_0);361 PMCQ1_Write_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_DRIVER_ENABLE, data);362 data = PMCQ1_Read_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_DRIVER_ENABLE );363 SYNC();364 365 /*366 * Disable the receiver and the transmitter.367 */368 369 SYNC();370 tmp_u32 = scc_read32( "gsmr_l", &ptr->pSCCR->gsmr_l );371 tmp_u32 &= (~(M360_GSMR_ENR | M360_GSMR_ENT ) ) ;372 scc_write32( "gsmr_l", &ptr->pSCCR->gsmr_l, tmp_u32 );373 374 /*375 * Disable Interrupt Error and Interrupt Breakpoint376 * Set SAID to 4 XXX - Shouldn't it be 7 for slave mode377 * Set SAISM to 7378 */379 SYNC();380 scc_write16( "sdcr", &m360->sdcr, 0x0740 );381 382 /*383 * Clear status -- reserved interrupt, SDMA channel error, SDMA breakpoint384 */385 scc_write8( "sdsr", &m360->sdsr, 0x07 );386 SYNC();387 388 /*389 * Initialize timer information in RISC Controller Configuration Register390 */391 scc_write16( "rccr", &m360->rccr, 0x8100 );392 SYNC();393 394 /*395 * XXX396 */397 scc_write16( "papar", &m360->papar, 0xffff );398 scc_write16( "padir", &m360->padir, 0x5500 ); /* From Memo */399 scc_write16( "paodr", &m360->paodr, 0x0000 );400 SYNC();401 402 /*403 * XXX404 */405 406 #if 0407 scc_write32( "pbpar", &m360->pbpar, 0x00000000 );408 scc_write32( "pbdir", &m360->pbdir, 0x0003ffff );409 scc_write32( "pbdat", &m360->pbdat, 0x0000003f );410 SYNC();411 #else412 data = mc68360_scc_calculate_pbdat( ptr->chip );413 scc_write32( "pbpar", &m360->pbpar, 0x00000000 );414 scc_write32( "pbdat", &m360->pbdat, data );415 SYNC();416 scc_write32( "pbdir", &m360->pbdir, 0x0003fc3 );417 SYNC();418 #endif419 420 421 /*422 * XXX423 */424 scc_write16( "pcpar", &m360->pcpar, 0x0000 );425 scc_write16( "pcdir", &m360->pcdir, 0x0000 );426 scc_write16( "pcso", &m360->pcso, 0x0000 );427 SYNC();428 429 /*430 * configure baud rate generator for 16x bit rate, where.....431 * b = desired baud rate432 * clk = system clock (33mhz)433 * d = clock dividor value434 *435 * for b > 300 : d = clk/(b*16)436 * for b<= 300 : d = (clk/ (b*16*16))-1)437 */438 SYNC();439 if( ptr->baud > 300 ) data = 33333333 / (ptr->baud * 16 );440 else data = (33333333 / (ptr->baud * 16 * 16) ) - 1;441 data *= 2 ;442 data &= 0x00001ffe ;443 444 /* really data = 0x010000 | data | ((baud>300)? 0 : 1 ) ; */445 data |= ((ptr->baud>300)? 0 : 1 ) ;446 data |= 0x010000 ;447 448 scc_write32( "pBRGC", ptr->pBRGC, data );449 450 data = (((ptr->channel-1)*8) | (ptr->channel-1)) ;451 data = data << ((ptr->channel-1)*8) ;452 data |= scc_read32( "sicr", &m360->sicr );453 scc_write32( "sicr", &m360->sicr, data );454 455 /*456 * initialise SCC parameter ram457 */458 SYNC();459 scc_write16( "pSCCB->rbase", &ptr->pSCCB->rbase,460 (char *)(ptr->sccRxBd) - (char *)m360 );461 scc_write16( "pSCCB->tbase", &ptr->pSCCB->tbase,462 (char *)(ptr->sccTxBd) - (char *)m360 );463 464 scc_write8( "pSCCB->rfcr", &ptr->pSCCB->rfcr, 0x15 ); /* 0x15 0x18 */465 scc_write8( "pSCCB->tfcr", &ptr->pSCCB->tfcr, 0x15 ); /* 0x15 0x18 */466 467 scc_write16( "pSCCB->mrblr", &ptr->pSCCB->mrblr, M68360_RX_BUF_SIZE );468 469 /*470 * initialise tx and rx scc parameters471 */472 SYNC();473 data = M360_CR_INIT_TX_RX_PARAMS | 0x01;474 data |= (M360_CR_CH_NUM * (ptr->channel-1) );475 scc_write16( "CR", &m360->cr, data );476 477 /*478 * initialise uart specific parameter RAM479 */480 SYNC();481 scc_write16( "pSCCB->un.uart.max_idl", &ptr->pSCCB->un.uart.max_idl, 15000 );482 scc_write16( "pSCCB->un.uart.brkcr", &ptr->pSCCB->un.uart.brkcr, 0x0001 );483 scc_write16( "pSCCB->un.uart.parec", &ptr->pSCCB->un.uart.parec, 0x0000 );484 485 scc_write16( "pSCCB->un,uart.frmec", &ptr->pSCCB->un.uart.frmec, 0x0000 );486 487 scc_write16( "pSCCB->un.uart.nosec", &ptr->pSCCB->un.uart.nosec, 0x0000 );488 scc_write16( "pSCCB->un.uart.brkec", &ptr->pSCCB->un.uart.brkec, 0x0000 );489 scc_write16( "pSCCB->un.uart.uaddr0", &ptr->pSCCB->un.uart.uaddr[0], 0x0000 );490 scc_write16( "pSCCB->un.uart.uaddr1", &ptr->pSCCB->un.uart.uaddr[1], 0x0000 );491 scc_write16( "pSCCB->un.uart.toseq", &ptr->pSCCB->un.uart.toseq, 0x0000 );492 scc_write16( "pSCCB->un.uart.char0",493 &ptr->pSCCB->un.uart.character[0], 0x0039 );494 scc_write16( "pSCCB->un.uart.char1",495 &ptr->pSCCB->un.uart.character[1], 0x8000 );496 scc_write16( "pSCCB->un.uart.char2",497 &ptr->pSCCB->un.uart.character[2], 0x8000 );498 scc_write16( "pSCCB->un.uart.char3",499 &ptr->pSCCB->un.uart.character[3], 0x8000 );500 scc_write16( "pSCCB->un.uart.char4",501 &ptr->pSCCB->un.uart.character[4], 0x8000 );502 scc_write16( "pSCCB->un.uart.char5",503 &ptr->pSCCB->un.uart.character[5], 0x8000 );504 scc_write16( "pSCCB->un.uart.char6",505 &ptr->pSCCB->un.uart.character[6], 0x8000 );506 scc_write16( "pSCCB->un.uart.char7",507 &ptr->pSCCB->un.uart.character[7], 0x8000 );508 509 scc_write16( "pSCCB->un.uart.rccm", &ptr->pSCCB->un.uart.rccm, 0xc0ff );510 511 /*512 * setup buffer descriptor stuff513 */514 SYNC();515 scc_write16( "sccRxBd->status", &ptr->sccRxBd->status, 0x0000 );516 SYNC();517 scc_write16( "sccRxBd->length", &ptr->sccRxBd->length, 0x0000 );518 scc_write16( "sccRxBd->status", &ptr->sccRxBd->status,519 M360_BD_EMPTY | M360_BD_WRAP | M360_BD_INTERRUPT );520 /* XXX Radstone Example writes RX buffer ptr as two u16's */521 scc_write32( "sccRxBd->buffer", &ptr->sccRxBd->buffer,522 RX_BUFFER_ADDRESS( ptr ) );523 524 SYNC();525 scc_write16( "sccTxBd->status", &ptr->sccTxBd->status, 0x0000 );526 SYNC();527 scc_write16( "sccTxBd->length", &ptr->sccTxBd->length, 0x0000 );528 /* XXX Radstone Example writes TX buffer ptr as two u16's */529 scc_write32( "sccTxBd->buffer", &ptr->sccTxBd->buffer,530 TX_BUFFER_ADDRESS( ptr ) );531 532 /*533 * clear previous events and set interrupt priorities534 */535 scc_write16( "pSCCR->scce", &ptr->pSCCR->scce, 0x1bef ); /* From memo */536 SYNC();537 SYNC();538 scc_write32( "cicr", &m360->cicr, 0x001b9f40 );539 SYNC();540 541 /* scc_write32( "cicr", &m360->cicr, scc_read32( "cicr", &m360->cicr ) ); */542 543 scc_write16( "pSCCR->sccm", &ptr->pSCCR->sccm, M360_SCCE_TX | M360_SCCE_RX );544 545 data = scc_read32("cimr", &m360->cimr);546 data |= (0x80000000 >> ptr->channel);547 scc_write32( "cimr", &m360->cimr, data );548 SYNC();549 scc_write32( "cipr", &m360->cipr, scc_read32( "cipr", &m360->cipr ) );550 551 scc_write32( "pSCCR->gsmr_h", &ptr->pSCCR->gsmr_h, M360_GSMR_RFW );552 scc_write32( "pSCCR->gsmr_l", &ptr->pSCCR->gsmr_l,553 (M360_GSMR_TDCR_16X | M360_GSMR_RDCR_16X | M360_GSMR_MODE_UART) );554 555 scc_write16( "pSCCR->dsr", &ptr->pSCCR->dsr, 0x7e7e );556 SYNC();557 558 scc_write16( "pSCCR->psmr", &ptr->pSCCR->psmr,559 (M360_PSMR_CL8 | M360_PSMR_UM_NORMAL | M360_PSMR_TPM_ODD) );560 SYNC();561 562 #if 0 /* XXX - ??? */563 /*564 * Enable the receiver and the transmitter.565 */566 567 SYNC();568 data = scc_read32( "pSCCR->gsmr_l", &ptr->pSCCR->gsmr_l);569 scc_write32( "pSCCR->gsmr_l", &ptr->pSCCR->gsmr_l,570 (data | M360_GSMR_ENR | M360_GSMR_ENT) );571 572 data = PMCQ1_Read_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_INT_MASK );573 data &= (~PMCQ1_INT_MASK_QUICC);574 PMCQ1_Write_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_INT_MASK, data );575 576 data = PMCQ1_Read_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_INT_STATUS );577 data &= (~PMCQ1_INT_STATUS_QUICC);578 PMCQ1_Write_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_INT_STATUS, data );579 #endif580 }581 582 /*583 * mc68360_scc_write_support_int584 *585 * Console Termios output entry point when using interrupt driven output.586 */587 static ssize_t mc68360_scc_write_support_int(588 int minor,589 const char *buf,590 size_t len591 )592 {593 rtems_interrupt_level Irql;594 M68360_serial_ports_t ptr;595 596 #if 1597 mc68360_length_array[ mc68360_length_count ] = len;598 mc68360_length_count++;599 if ( mc68360_length_count >= MC68360_LENGTH_SIZE )600 mc68360_length_count=0;601 #endif602 603 ptr = Console_Port_Tbl[minor]->pDeviceParams;604 605 /*606 * We are using interrupt driven output and termios only sends us607 * one character at a time.608 */609 610 if ( !len )611 return 0;612 613 /*614 *615 */616 #ifdef DEBUG_360617 printk("mc68360_scc_write_support_int: char 0x%x length %d\n",618 (unsigned int)*buf, len );619 #endif620 /*621 * We must copy the data from the global memory space to MC68360 space622 */623 624 rtems_interrupt_disable(Irql);625 626 scc_write16( "sccTxBd->status", &ptr->sccTxBd->status, 0 );627 memcpy((void *) ptr->txBuf, buf, len);628 scc_write32( "sccTxBd->buffer", &ptr->sccTxBd->buffer,629 TX_BUFFER_ADDRESS(ptr->txBuf) );630 scc_write16( "sccTxBd->length", &ptr->sccTxBd->length, len );631 scc_write16( "sccTxBd->status", &ptr->sccTxBd->status,632 (M360_BD_READY | M360_BD_WRAP | M360_BD_INTERRUPT) );633 634 rtems_interrupt_enable(Irql);635 636 return len;637 }638 639 /*640 * mc68360_scc_write_polled641 *642 * This routine polls out the requested character.643 */644 static void mc68360_scc_write_polled(645 int minor,646 char cChar647 )648 {649 #ifdef DEBUG_360650 printk("mc68360_scc_write_polled: %c\n", cChar);651 #endif652 }653 654 /*655 * mc68681_set_attributes656 *657 * This function sets the DUART channel to reflect the requested termios658 * port settings.659 */660 static int mc68360_scc_set_attributes(661 int minor,662 const struct termios *t663 )664 {665 int baud;666 M68360_serial_ports_t ptr;667 uint16_t value;668 669 #ifdef DEBUG_360670 printk("mc68360_scc_set_attributes\n");671 #endif672 673 ptr = Console_Port_Tbl[minor]->pDeviceParams;674 675 switch (t->c_cflag & CBAUD) {676 case B50: baud = 50; break;677 case B75: baud = 75; break;678 case B110: baud = 110; break;679 case B134: baud = 134; break;680 case B150: baud = 150; break;681 case B200: baud = 200; break;682 case B300: baud = 300; break;683 case B600: baud = 600; break;684 case B1200: baud = 1200; break;685 case B1800: baud = 1800; break;686 case B2400: baud = 2400; break;687 case B4800: baud = 4800; break;688 case B9600: baud = 9600; break;689 case B19200: baud = 19200; break;690 case B38400: baud = 38400; break;691 case B57600: baud = 57600; break;692 case B115200: baud = 115200; break;693 case B230400: baud = 230400; break;694 case B460800: baud = 460800; break;695 default: baud = -1; break;696 }697 698 if (baud > 0) {699 scc_write32(700 "pBRGC",701 ptr->pBRGC,702 mc68360_sccBRGC(baud, ptr->chip->m360_clock_rate)703 );704 }705 706 /* Initial value of PSMR should be 0 */707 value = M360_PSMR_UM_NORMAL;708 709 /* set the number of data bits, 8 is most common */710 if (t->c_cflag & CSIZE) { /* was it specified? */711 switch (t->c_cflag & CSIZE) {712 case CS5: value |= M360_PSMR_CL5; break;713 case CS6: value |= M360_PSMR_CL6; break;714 case CS7: value |= M360_PSMR_CL7; break;715 case CS8: value |= M360_PSMR_CL8; break;716 }717 } else {718 value |= M360_PSMR_CL8; /* default to 8 data bits */719 }720 721 /* the number of stop bits */722 if (t->c_cflag & CSTOPB)723 value |= M360_PSMR_SL_2; /* Two stop bits */724 else725 value |= M360_PSMR_SL_1; /* One stop bit */726 727 /* Set Parity M360_PSMR_PEN bit should be clear on no parity so728 * do nothing in that case729 */730 if (t->c_cflag & PARENB) { /* enable parity detection? */731 value |= M360_PSMR_PEN;732 if (t->c_cflag & PARODD){733 value |= M360_PSMR_RPM_ODD; /* select odd parity */734 value |= M360_PSMR_TPM_ODD;735 } else {736 value |= M360_PSMR_RPM_EVEN; /* select even parity */737 value |= M360_PSMR_TPM_EVEN;738 }739 }740 741 SYNC();742 scc_write16( "pSCCR->psmr", &ptr->pSCCR->psmr, value );743 SYNC();744 745 return 0;746 }747 748 /*749 * mc68360_scc_close750 *751 * This function shuts down the requested port.752 */753 static int mc68360_scc_close(754 int major,755 int minor,756 void *arg757 )758 {759 return RTEMS_SUCCESSFUL;760 }761 762 /*763 * mc68360_scc_inbyte_nonblocking_polled764 *765 * Console Termios polling input entry point.766 */767 static int mc68360_scc_inbyte_nonblocking_polled(768 int minor769 )770 {771 return -1;772 }773 774 /*775 * mc68360_scc_write_support_polled776 *777 * Console Termios output entry point when using polled output.778 *779 */780 static ssize_t mc68360_scc_write_support_polled(781 int minor,782 const char *buf,783 size_t len784 )785 {786 printk("mc68360_scc_write_support_polled: minor %d char %c len %d\n",787 minor, buf, len );788 return len;789 }790 791 /*792 * mc68360_scc_init793 *794 * This function initializes the DUART to a quiecsent state.795 */796 static void mc68360_scc_init(int minor)797 {798 #ifdef DEBUG_360799 printk("mc68360_scc_init\n");800 #endif801 }802 803 int mc68360_scc_create_chip( PPMCQ1BoardData BoardData, uint8_t int_vector )804 {805 M68360_t chip;806 int i;807 808 #ifdef DEBUG_360809 printk("mc68360_scc_create_chip\n");810 #endif811 812 /*813 * Create console structure for this card814 * XXX - Note Does this need to be moved up to if a QUICC is fitted815 * section?816 */817 if ((chip = malloc(sizeof(struct _m68360_per_chip))) == NULL)818 {819 printk("Error Unable to allocate memory for _m68360_per_chip\n");820 return RTEMS_IO_ERROR;821 }822 823 chip->next = M68360_chips;824 chip->m360 = (void *)BoardData->baseaddr;825 chip->m360_interrupt = int_vector;826 chip->m360_clock_rate = 25000000;827 chip->board_data = BoardData;828 M68360_chips = chip;829 830 for (i=1; i<=4; i++) {831 chip->port[i-1].channel = i;832 chip->port[i-1].chip = chip;833 chip->port[i-1].baud = 9600;834 835 switch( i ) {836 case 1:837 chip->port[i-1].pBRGC = &chip->m360->brgc1;838 chip->port[i-1].pSCCB = (m360SCCparms_t *) &chip->m360->scc1p;839 chip->port[i-1].pSCCR = &chip->m360->scc1;840 M360SetupMemory( chip ); /* Do this first time through */841 break;842 case 2:843 chip->port[i-1].pBRGC = &chip->m360->brgc2;844 chip->port[i-1].pSCCB = &chip->m360->scc2p;845 chip->port[i-1].pSCCR = &chip->m360->scc2;846 break;847 case 3:848 chip->port[i-1].pBRGC = &chip->m360->brgc3;849 chip->port[i-1].pSCCB = &chip->m360->scc3p;850 chip->port[i-1].pSCCR = &chip->m360->scc3;851 break;852 case 4:853 chip->port[i-1].pBRGC = &chip->m360->brgc4;854 chip->port[i-1].pSCCB = &chip->m360->scc4p;855 chip->port[i-1].pSCCR = &chip->m360->scc4;856 break;857 default:858 printk("Invalid mc68360 channel %d\n", i);859 return RTEMS_IO_ERROR;860 }861 862 /*863 * Allocate buffer descriptors.864 */865 866 chip->port[i-1].sccRxBd = M360AllocateBufferDescriptors(chip, 1);867 chip->port[i-1].sccTxBd = M360AllocateBufferDescriptors(chip, 1);868 }869 870 rsPMCQ1QuiccIntConnect(871 chip->board_data->busNo,872 chip->board_data->slotNo,873 chip->board_data->funcNo,874 (FUNCTION_PTR) &mc68360_sccInterruptHandler,875 (uintptr_t) chip876 );877 878 return RTEMS_SUCCESSFUL;879 }880 881 const console_fns mc68360_scc_fns = {882 libchip_serial_default_probe, /* deviceProbe */883 mc68360_scc_open, /* deviceFirstOpen */884 NULL, /* deviceLastClose */885 NULL, /* deviceRead */886 mc68360_scc_write_support_int, /* deviceWrite */887 mc68360_scc_initialize_interrupts, /* deviceInitialize */888 mc68360_scc_write_polled, /* deviceWritePolled */889 mc68360_scc_set_attributes, /* deviceSetAttributes */890 TRUE /* deviceOutputUsesInterrupts */891 };892 893 const console_fns mc68360_scc_polled = {894 libchip_serial_default_probe, /* deviceProbe */895 mc68360_scc_open, /* deviceFirstOpen */896 mc68360_scc_close, /* deviceLastClose */897 mc68360_scc_inbyte_nonblocking_polled, /* deviceRead */898 mc68360_scc_write_support_polled, /* deviceWrite */899 mc68360_scc_init, /* deviceInitialize */900 mc68360_scc_write_polled, /* deviceWritePolled */901 mc68360_scc_set_attributes, /* deviceSetAttributes */902 FALSE /* deviceOutputUsesInterrupts */903 };904 -
deleted file c/src/lib/libbsp/powerpc/ep1a/console/ns16550cfg.c
diff --git a/c/src/lib/libbsp/powerpc/ep1a/console/ns16550cfg.c b/c/src/lib/libbsp/powerpc/ep1a/console/ns16550cfg.c deleted file mode 100644 index 12a423b..0000000
+ - 1 /*2 * This include file contains all console driver definitions for the ns16550.3 */4 5 /*6 * COPYRIGHT (c) 1989-2008.7 * On-Line Applications Research Corporation (OAR).8 *9 * The license and distribution terms for this file may be10 * found in the file LICENSE in this distribution or at11 * http://www.rtems.org/license/LICENSE.12 */13 14 #include <bsp.h>15 #include <libchip/serial.h>16 #include <libchip/ns16550.h>17 18 #include "ns16550cfg.h"19 20 typedef struct uart_reg21 {22 unsigned char reg;23 unsigned char pad[7];24 } uartReg;25 26 uint8_t Read_ns16550_register(27 uintptr_t ulCtrlPort,28 uint8_t ucRegNum29 )30 {31 volatile struct uart_reg *p = (volatile struct uart_reg *)ulCtrlPort;32 uint8_t ucData;33 34 ucData = p[ucRegNum].reg;35 __asm__ volatile("sync");36 return ucData;37 }38 39 void Write_ns16550_register(40 uintptr_t ulCtrlPort,41 uint8_t ucRegNum,42 uint8_t ucData43 )44 {45 volatile struct uart_reg *p = (volatile struct uart_reg *)ulCtrlPort;46 volatile int i;47 p[ucRegNum].reg = ucData;48 __asm__ volatile("sync");49 __asm__ volatile("isync");50 __asm__ volatile("eieio");51 for (i=0;i<0x08ff;i++)52 __asm__ volatile("isync");53 } -
deleted file c/src/lib/libbsp/powerpc/ep1a/console/ns16550cfg.h
diff --git a/c/src/lib/libbsp/powerpc/ep1a/console/ns16550cfg.h b/c/src/lib/libbsp/powerpc/ep1a/console/ns16550cfg.h deleted file mode 100644 index 45d5208..0000000
+ - 1 /*2 * This include file contains all console driver definitions for the ns16550.3 */4 5 /*6 * COPYRIGHT (c) 1989-2008.7 * On-Line Applications Research Corporation (OAR).8 *9 * The license and distribution terms for this file may be10 * found in the file LICENSE in this distribution or at11 * http://www.rtems.org/license/LICENSE.12 */13 14 #ifndef __NS16550_CONFIG_H15 #define __NS16550_CONFIG_H16 17 #ifdef __cplusplus18 extern "C" {19 #endif20 21 /*22 * Board specific register access routines23 */24 25 uint8_t Read_ns16550_register(26 uintptr_t ulCtrlPort,27 uint8_t ucRegNum28 );29 30 void Write_ns16550_register(31 uintptr_t ulCtrlPort,32 uint8_t ucRegNum,33 uint8_t ucData34 );35 36 extern const console_fns ns16550_fns_8245;37 extern const console_fns ns16550_fns_polled_8245;38 39 #ifdef __cplusplus40 }41 #endif42 43 #endif -
deleted file c/src/lib/libbsp/powerpc/ep1a/console/polled_io.c
diff --git a/c/src/lib/libbsp/powerpc/ep1a/console/polled_io.c b/c/src/lib/libbsp/powerpc/ep1a/console/polled_io.c deleted file mode 100644 index e0ae919..0000000
+ - 1 /*2 * polled_io.c -- Basic input/output for early boot3 *4 * Copyright (C) 1998, 1999 Gabriel Paubert, paubert@iram.es5 *6 * Modified to compile in RTEMS development environment7 * by Eric Valette8 *9 * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr10 *11 * The license and distribution terms for this file may be12 * found in the file LICENSE in this distribution or at13 * http://www.rtems.org/license/LICENSE.14 */15 16 #include <rtems/system.h>17 #include <sys/types.h>18 #include <libcpu/byteorder.h>19 #include <libcpu/page.h>20 #include <libcpu/mmu.h>21 #include <libcpu/io.h>22 #include <string.h>23 #include <stdarg.h>24 #include <bsp/consoleIo.h>25 #include <bsp.h>26 #include <libcpu/spr.h>27 28 #if 029 #ifdef BSP_KBD_IOBASE30 #define USE_KBD_SUPPORT31 #endif32 #ifdef BSP_VGA_IOBASE33 #define USE_VGA_SUPPORT34 #endif35 36 #ifdef USE_KBD_SUPPORT37 #include "keyboard.h"38 #endif39 #include "console.inl"40 41 #ifdef __BOOT__42 extern void boot_udelay();43 void * __palloc(u_long);44 void pfree(void *);45 #else46 #include <rtems/bspIo.h>47 #endif48 49 typedef unsigned long long u64;50 typedef long long s64;51 typedef unsigned int u32;52 53 #ifndef __BOOT__54 BSP_output_char_function_type BSP_output_char = debug_putc_onlcr;55 BSP_polling_getchar_function_type BSP_poll_char = NULL;56 #endif57 58 #ifdef USE_KBD_SUPPORT59 unsigned short plain_map[NR_KEYS] = {60 0xf200, 0xf01b, 0xf031, 0xf032, 0xf033, 0xf034, 0xf035, 0xf036,61 0xf037, 0xf038, 0xf039, 0xf030, 0xf02d, 0xf03d, 0xf07f, 0xf009,62 0xfb71, 0xfb77, 0xfb65, 0xfb72, 0xfb74, 0xfb79, 0xfb75, 0xfb69,63 0xfb6f, 0xfb70, 0xf05b, 0xf05d, 0xf201, 0xf702, 0xfb61, 0xfb73,64 0xfb64, 0xfb66, 0xfb67, 0xfb68, 0xfb6a, 0xfb6b, 0xfb6c, 0xf03b,65 0xf027, 0xf060, 0xf700, 0xf05c, 0xfb7a, 0xfb78, 0xfb63, 0xfb76,66 0xfb62, 0xfb6e, 0xfb6d, 0xf02c, 0xf02e, 0xf02f, 0xf700, 0xf30c,67 0xf703, 0xf020, 0xf207, 0xf100, 0xf101, 0xf102, 0xf103, 0xf104,68 0xf105, 0xf106, 0xf107, 0xf108, 0xf109, 0xf208, 0xf209, 0xf307,69 0xf308, 0xf309, 0xf30b, 0xf304, 0xf305, 0xf306, 0xf30a, 0xf301,70 0xf302, 0xf303, 0xf300, 0xf310, 0xf206, 0xf200, 0xf03c, 0xf10a,71 0xf10b, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,72 0xf30e, 0xf702, 0xf30d, 0xf01c, 0xf701, 0xf205, 0xf114, 0xf603,73 0xf118, 0xf601, 0xf602, 0xf117, 0xf600, 0xf119, 0xf115, 0xf116,74 0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,75 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,76 };77 78 unsigned short shift_map[NR_KEYS] = {79 0xf200, 0xf01b, 0xf021, 0xf040, 0xf023, 0xf024, 0xf025, 0xf05e,80 0xf026, 0xf02a, 0xf028, 0xf029, 0xf05f, 0xf02b, 0xf07f, 0xf009,81 0xfb51, 0xfb57, 0xfb45, 0xfb52, 0xfb54, 0xfb59, 0xfb55, 0xfb49,82 0xfb4f, 0xfb50, 0xf07b, 0xf07d, 0xf201, 0xf702, 0xfb41, 0xfb53,83 0xfb44, 0xfb46, 0xfb47, 0xfb48, 0xfb4a, 0xfb4b, 0xfb4c, 0xf03a,84 0xf022, 0xf07e, 0xf700, 0xf07c, 0xfb5a, 0xfb58, 0xfb43, 0xfb56,85 0xfb42, 0xfb4e, 0xfb4d, 0xf03c, 0xf03e, 0xf03f, 0xf700, 0xf30c,86 0xf703, 0xf020, 0xf207, 0xf10a, 0xf10b, 0xf10c, 0xf10d, 0xf10e,87 0xf10f, 0xf110, 0xf111, 0xf112, 0xf113, 0xf213, 0xf203, 0xf307,88 0xf308, 0xf309, 0xf30b, 0xf304, 0xf305, 0xf306, 0xf30a, 0xf301,89 0xf302, 0xf303, 0xf300, 0xf310, 0xf206, 0xf200, 0xf03e, 0xf10a,90 0xf10b, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,91 0xf30e, 0xf702, 0xf30d, 0xf200, 0xf701, 0xf205, 0xf114, 0xf603,92 0xf20b, 0xf601, 0xf602, 0xf117, 0xf600, 0xf20a, 0xf115, 0xf116,93 0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,94 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,95 };96 97 unsigned short altgr_map[NR_KEYS] = {98 0xf200, 0xf200, 0xf200, 0xf040, 0xf200, 0xf024, 0xf200, 0xf200,99 0xf07b, 0xf05b, 0xf05d, 0xf07d, 0xf05c, 0xf200, 0xf200, 0xf200,100 0xfb71, 0xfb77, 0xf918, 0xfb72, 0xfb74, 0xfb79, 0xfb75, 0xfb69,101 0xfb6f, 0xfb70, 0xf200, 0xf07e, 0xf201, 0xf702, 0xf914, 0xfb73,102 0xf917, 0xf919, 0xfb67, 0xfb68, 0xfb6a, 0xfb6b, 0xfb6c, 0xf200,103 0xf200, 0xf200, 0xf700, 0xf200, 0xfb7a, 0xfb78, 0xf916, 0xfb76,104 0xf915, 0xfb6e, 0xfb6d, 0xf200, 0xf200, 0xf200, 0xf700, 0xf30c,105 0xf703, 0xf200, 0xf207, 0xf50c, 0xf50d, 0xf50e, 0xf50f, 0xf510,106 0xf511, 0xf512, 0xf513, 0xf514, 0xf515, 0xf208, 0xf202, 0xf911,107 0xf912, 0xf913, 0xf30b, 0xf90e, 0xf90f, 0xf910, 0xf30a, 0xf90b,108 0xf90c, 0xf90d, 0xf90a, 0xf310, 0xf206, 0xf200, 0xf07c, 0xf516,109 0xf517, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,110 0xf30e, 0xf702, 0xf30d, 0xf200, 0xf701, 0xf205, 0xf114, 0xf603,111 0xf118, 0xf601, 0xf602, 0xf117, 0xf600, 0xf119, 0xf115, 0xf116,112 0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,113 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,114 };115 116 unsigned short ctrl_map[NR_KEYS] = {117 0xf200, 0xf200, 0xf200, 0xf000, 0xf01b, 0xf01c, 0xf01d, 0xf01e,118 0xf01f, 0xf07f, 0xf200, 0xf200, 0xf01f, 0xf200, 0xf008, 0xf200,119 0xf011, 0xf017, 0xf005, 0xf012, 0xf014, 0xf019, 0xf015, 0xf009,120 0xf00f, 0xf010, 0xf01b, 0xf01d, 0xf201, 0xf702, 0xf001, 0xf013,121 0xf004, 0xf006, 0xf007, 0xf008, 0xf00a, 0xf00b, 0xf00c, 0xf200,122 0xf007, 0xf000, 0xf700, 0xf01c, 0xf01a, 0xf018, 0xf003, 0xf016,123 0xf002, 0xf00e, 0xf00d, 0xf200, 0xf20e, 0xf07f, 0xf700, 0xf30c,124 0xf703, 0xf000, 0xf207, 0xf100, 0xf101, 0xf102, 0xf103, 0xf104,125 0xf105, 0xf106, 0xf107, 0xf108, 0xf109, 0xf208, 0xf204, 0xf307,126 0xf308, 0xf309, 0xf30b, 0xf304, 0xf305, 0xf306, 0xf30a, 0xf301,127 0xf302, 0xf303, 0xf300, 0xf310, 0xf206, 0xf200, 0xf200, 0xf10a,128 0xf10b, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,129 0xf30e, 0xf702, 0xf30d, 0xf01c, 0xf701, 0xf205, 0xf114, 0xf603,130 0xf118, 0xf601, 0xf602, 0xf117, 0xf600, 0xf119, 0xf115, 0xf116,131 0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,132 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,133 };134 135 unsigned short shift_ctrl_map[NR_KEYS] = {136 0xf200, 0xf200, 0xf200, 0xf000, 0xf200, 0xf200, 0xf200, 0xf200,137 0xf200, 0xf200, 0xf200, 0xf200, 0xf01f, 0xf200, 0xf200, 0xf200,138 0xf011, 0xf017, 0xf005, 0xf012, 0xf014, 0xf019, 0xf015, 0xf009,139 0xf00f, 0xf010, 0xf200, 0xf200, 0xf201, 0xf702, 0xf001, 0xf013,140 0xf004, 0xf006, 0xf007, 0xf008, 0xf00a, 0xf00b, 0xf00c, 0xf200,141 0xf200, 0xf200, 0xf700, 0xf200, 0xf01a, 0xf018, 0xf003, 0xf016,142 0xf002, 0xf00e, 0xf00d, 0xf200, 0xf200, 0xf200, 0xf700, 0xf30c,143 0xf703, 0xf200, 0xf207, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,144 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf208, 0xf200, 0xf307,145 0xf308, 0xf309, 0xf30b, 0xf304, 0xf305, 0xf306, 0xf30a, 0xf301,146 0xf302, 0xf303, 0xf300, 0xf310, 0xf206, 0xf200, 0xf200, 0xf200,147 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,148 0xf30e, 0xf702, 0xf30d, 0xf200, 0xf701, 0xf205, 0xf114, 0xf603,149 0xf118, 0xf601, 0xf602, 0xf117, 0xf600, 0xf119, 0xf115, 0xf116,150 0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,151 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,152 };153 154 unsigned short alt_map[NR_KEYS] = {155 0xf200, 0xf81b, 0xf831, 0xf832, 0xf833, 0xf834, 0xf835, 0xf836,156 0xf837, 0xf838, 0xf839, 0xf830, 0xf82d, 0xf83d, 0xf87f, 0xf809,157 0xf871, 0xf877, 0xf865, 0xf872, 0xf874, 0xf879, 0xf875, 0xf869,158 0xf86f, 0xf870, 0xf85b, 0xf85d, 0xf80d, 0xf702, 0xf861, 0xf873,159 0xf864, 0xf866, 0xf867, 0xf868, 0xf86a, 0xf86b, 0xf86c, 0xf83b,160 0xf827, 0xf860, 0xf700, 0xf85c, 0xf87a, 0xf878, 0xf863, 0xf876,161 0xf862, 0xf86e, 0xf86d, 0xf82c, 0xf82e, 0xf82f, 0xf700, 0xf30c,162 0xf703, 0xf820, 0xf207, 0xf500, 0xf501, 0xf502, 0xf503, 0xf504,163 0xf505, 0xf506, 0xf507, 0xf508, 0xf509, 0xf208, 0xf209, 0xf907,164 0xf908, 0xf909, 0xf30b, 0xf904, 0xf905, 0xf906, 0xf30a, 0xf901,165 0xf902, 0xf903, 0xf900, 0xf310, 0xf206, 0xf200, 0xf83c, 0xf50a,166 0xf50b, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,167 0xf30e, 0xf702, 0xf30d, 0xf01c, 0xf701, 0xf205, 0xf114, 0xf603,168 0xf118, 0xf210, 0xf211, 0xf117, 0xf600, 0xf119, 0xf115, 0xf116,169 0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,170 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,171 };172 173 unsigned short ctrl_alt_map[NR_KEYS] = {174 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,175 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,176 0xf811, 0xf817, 0xf805, 0xf812, 0xf814, 0xf819, 0xf815, 0xf809,177 0xf80f, 0xf810, 0xf200, 0xf200, 0xf201, 0xf702, 0xf801, 0xf813,178 0xf804, 0xf806, 0xf807, 0xf808, 0xf80a, 0xf80b, 0xf80c, 0xf200,179 0xf200, 0xf200, 0xf700, 0xf200, 0xf81a, 0xf818, 0xf803, 0xf816,180 0xf802, 0xf80e, 0xf80d, 0xf200, 0xf200, 0xf200, 0xf700, 0xf30c,181 0xf703, 0xf200, 0xf207, 0xf500, 0xf501, 0xf502, 0xf503, 0xf504,182 0xf505, 0xf506, 0xf507, 0xf508, 0xf509, 0xf208, 0xf200, 0xf307,183 0xf308, 0xf309, 0xf30b, 0xf304, 0xf305, 0xf306, 0xf30a, 0xf301,184 0xf302, 0xf303, 0xf300, 0xf20c, 0xf206, 0xf200, 0xf200, 0xf50a,185 0xf50b, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,186 0xf30e, 0xf702, 0xf30d, 0xf200, 0xf701, 0xf205, 0xf114, 0xf603,187 0xf118, 0xf601, 0xf602, 0xf117, 0xf600, 0xf119, 0xf115, 0xf20c,188 0xf11a, 0xf10c, 0xf10d, 0xf11b, 0xf11c, 0xf110, 0xf311, 0xf11d,189 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200,190 };191 192 ushort *key_maps[MAX_NR_KEYMAPS] = {193 plain_map, shift_map, altgr_map, 0,194 ctrl_map, shift_ctrl_map, 0, 0,195 alt_map, 0, 0, 0,196 ctrl_alt_map, 0197 };198 199 unsigned int keymap_count = 7;200 201 /*202 * Philosophy: most people do not define more strings, but they who do203 * often want quite a lot of string space. So, we statically allocate204 * the default and allocate dynamically in chunks of 512 bytes.205 */206 207 char func_buf[] = {208 '\033', '[', '[', 'A', 0,209 '\033', '[', '[', 'B', 0,210 '\033', '[', '[', 'C', 0,211 '\033', '[', '[', 'D', 0,212 '\033', '[', '[', 'E', 0,213 '\033', '[', '1', '7', '~', 0,214 '\033', '[', '1', '8', '~', 0,215 '\033', '[', '1', '9', '~', 0,216 '\033', '[', '2', '0', '~', 0,217 '\033', '[', '2', '1', '~', 0,218 '\033', '[', '2', '3', '~', 0,219 '\033', '[', '2', '4', '~', 0,220 '\033', '[', '2', '5', '~', 0,221 '\033', '[', '2', '6', '~', 0,222 '\033', '[', '2', '8', '~', 0,223 '\033', '[', '2', '9', '~', 0,224 '\033', '[', '3', '1', '~', 0,225 '\033', '[', '3', '2', '~', 0,226 '\033', '[', '3', '3', '~', 0,227 '\033', '[', '3', '4', '~', 0,228 '\033', '[', '1', '~', 0,229 '\033', '[', '2', '~', 0,230 '\033', '[', '3', '~', 0,231 '\033', '[', '4', '~', 0,232 '\033', '[', '5', '~', 0,233 '\033', '[', '6', '~', 0,234 '\033', '[', 'M', 0,235 '\033', '[', 'P', 0,236 };237 238 char *funcbufptr = func_buf;239 int funcbufsize = sizeof(func_buf);240 int funcbufleft = 0; /* space left */241 242 char *func_table[MAX_NR_FUNC] = {243 func_buf + 0,244 func_buf + 5,245 func_buf + 10,246 func_buf + 15,247 func_buf + 20,248 func_buf + 25,249 func_buf + 31,250 func_buf + 37,251 func_buf + 43,252 func_buf + 49,253 func_buf + 55,254 func_buf + 61,255 func_buf + 67,256 func_buf + 73,257 func_buf + 79,258 func_buf + 85,259 func_buf + 91,260 func_buf + 97,261 func_buf + 103,262 func_buf + 109,263 func_buf + 115,264 func_buf + 120,265 func_buf + 125,266 func_buf + 130,267 func_buf + 135,268 func_buf + 140,269 func_buf + 145,270 0,271 0,272 func_buf + 149,273 0,274 };275 276 struct kbdiacr {277 unsigned char diacr, base, result;278 };279 280 struct kbdiacr accent_table[MAX_DIACR] = {281 {'`', 'A', '\300'}, {'`', 'a', '\340'},282 {'\'', 'A', '\301'}, {'\'', 'a', '\341'},283 {'^', 'A', '\302'}, {'^', 'a', '\342'},284 {'~', 'A', '\303'}, {'~', 'a', '\343'},285 {'"', 'A', '\304'}, {'"', 'a', '\344'},286 {'O', 'A', '\305'}, {'o', 'a', '\345'},287 {'0', 'A', '\305'}, {'0', 'a', '\345'},288 {'A', 'A', '\305'}, {'a', 'a', '\345'},289 {'A', 'E', '\306'}, {'a', 'e', '\346'},290 {',', 'C', '\307'}, {',', 'c', '\347'},291 {'`', 'E', '\310'}, {'`', 'e', '\350'},292 {'\'', 'E', '\311'}, {'\'', 'e', '\351'},293 {'^', 'E', '\312'}, {'^', 'e', '\352'},294 {'"', 'E', '\313'}, {'"', 'e', '\353'},295 {'`', 'I', '\314'}, {'`', 'i', '\354'},296 {'\'', 'I', '\315'}, {'\'', 'i', '\355'},297 {'^', 'I', '\316'}, {'^', 'i', '\356'},298 {'"', 'I', '\317'}, {'"', 'i', '\357'},299 {'-', 'D', '\320'}, {'-', 'd', '\360'},300 {'~', 'N', '\321'}, {'~', 'n', '\361'},301 {'`', 'O', '\322'}, {'`', 'o', '\362'},302 {'\'', 'O', '\323'}, {'\'', 'o', '\363'},303 {'^', 'O', '\324'}, {'^', 'o', '\364'},304 {'~', 'O', '\325'}, {'~', 'o', '\365'},305 {'"', 'O', '\326'}, {'"', 'o', '\366'},306 {'/', 'O', '\330'}, {'/', 'o', '\370'},307 {'`', 'U', '\331'}, {'`', 'u', '\371'},308 {'\'', 'U', '\332'}, {'\'', 'u', '\372'},309 {'^', 'U', '\333'}, {'^', 'u', '\373'},310 {'"', 'U', '\334'}, {'"', 'u', '\374'},311 {'\'', 'Y', '\335'}, {'\'', 'y', '\375'},312 {'T', 'H', '\336'}, {'t', 'h', '\376'},313 {'s', 's', '\337'}, {'"', 'y', '\377'},314 {'s', 'z', '\337'}, {'i', 'j', '\377'},315 };316 317 unsigned int accent_table_size = 68;318 319 320 321 322 /* These #defines have been copied from drivers/char/pc_keyb.h, by323 * Martin Mares (mj@ucw.cz).324 * converted to offsets by Till Straumann <strauman@slac.stanford.edu>325 */326 #define KBD_STATUS_REG 0x4 /* Status register (R) */327 #define KBD_CNTL_REG 0x4 /* Controller command register (W) */328 #define KBD_DATA_REG 0x0 /* Keyboard data register (R/W) */329 330 /*331 * Keyboard Controller Commands332 */333 334 #define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */335 #define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */336 #define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */337 #define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */338 #define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */339 #define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */340 #define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */341 #define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */342 #define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */343 344 /*345 * Keyboard Commands346 */347 348 #define KBD_CMD_ENABLE 0xF4 /* Enable scanning */349 #define KBD_CMD_DISABLE 0xF5 /* Disable scanning */350 #define KBD_CMD_RESET 0xFF /* Reset */351 352 /*353 * Keyboard Replies354 */355 356 #define KBD_REPLY_POR 0xAA /* Power on reset */357 #define KBD_REPLY_ACK 0xFA /* Command ACK */358 #define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */359 360 /*361 * Status Register Bits362 */363 364 #define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */365 #define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */366 #define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */367 #define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */368 #define KBD_STAT_PERR 0x80 /* Parity error */369 370 /*371 * Controller Mode Register Bits372 */373 374 #define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */375 #define KBD_MODE_SYS 0x04 /* The system flag (?) */376 #define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */377 #define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */378 #define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */379 #define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */380 #define KBD_MODE_RFU 0x80381 382 #endif /* USE_KBD_SUPPORT */383 384 385 /* Early messages after mm init but before console init are kept in log386 * buffers.387 */388 #define PAGE_LOG_CHARS (PAGE_SIZE-sizeof(int)-sizeof(u_long)-1)389 390 typedef struct _console_log {391 struct _console_log *next;392 int offset;393 u_char data[PAGE_LOG_CHARS];394 } console_log;395 396 #ifdef STATIC_LOG_ALLOC397 398 #define STATIC_LOG_DATA_PAGE_NB 3399 400 static u_char log_page_pool [STATIC_LOG_DATA_PAGE_NB * PAGE_SIZE];401 402 #endif403 #endif404 405 static board_memory_map mem_map = {406 (__io_ptr) _IO_BASE, /* from libcpu/io.h */407 (__io_ptr) _ISA_MEM_BASE,408 };409 410 board_memory_map *ptr_mem_map = &mem_map;411 412 void log_putc(const u_char c) {413 console_log *l;414 for(l=console_global_data.log; l; l=l->next) {415 if (l->offset<PAGE_LOG_CHARS) break;416 }417 if (!l) {418 l=__palloc(sizeof(console_log));419 memset(l, 0, sizeof(console_log));420 if (!console_global_data.log)421 console_global_data.log = l;422 else {423 console_log *p;424 for (p=console_global_data.log;425 p->next; p=p->next);426 p->next = l;427 }428 }429 l->data[l->offset++] = c;430 }431 432 /* This puts is non standard since it does not automatically add a newline433 * at the end. So it is made private to avoid confusion in other files.434 */435 static436 void puts(const u_char *s)437 {438 char c;439 440 while ( ( c = *s++ ) != '\0' ) {441 debug_putc_onlcr((const char)c);442 }443 }444 445 446 static447 void flush_log(void) {448 console_log *p, *next;449 if (console_global_data.vacuum_sent) {450 #ifdef TRACE_FLUSH_LOG451 printk("%d characters sent into oblivion before MM init!\n",452 console_global_data.vacuum_sent);453 #endif454 }455 for(p=console_global_data.log; p; p=next) {456 puts(p->data);457 next = p->next;458 pfree(p);459 }460 }461 462 #ifndef INL_CONSOLE_INB463 #error "BSP probably didn't define a console port"464 #endif465 466 void serial_putc(const u_char c)467 {468 while ((INL_CONSOLE_INB(lsr) & LSR_THRE) == 0) ;469 INL_CONSOLE_OUTB(thr, c);470 }471 472 int serial_getc(void)473 {474 while ((INL_CONSOLE_INB(lsr) & LSR_DR) == 0) ;475 return (INL_CONSOLE_INB(rbr));476 }477 478 int serial_tstc(void)479 {480 return ((INL_CONSOLE_INB(lsr) & LSR_DR) != 0);481 }482 483 #ifdef USE_VGA_SUPPORT484 static void scroll(void)485 {486 int i;487 488 memcpy ( (u_char *)vidmem, (u_char *)vidmem + console_global_data.cols * 2,489 ( console_global_data.lines - 1 ) * console_global_data.cols * 2 );490 for ( i = ( console_global_data.lines - 1 ) * console_global_data.cols * 2;491 i < console_global_data.lines * console_global_data.cols * 2;492 i += 2 )493 vidmem[i] = ' ';494 }495 496 /*497 * cursor() sets an offset (0-1999) into the 80x25 text area498 */499 static void500 cursor(int x, int y)501 {502 int pos = console_global_data.cols*y + x;503 vga_outb(14, 0x14);504 vga_outb(0x15, pos>>8);505 vga_outb(0x14, 15);506 vga_outb(0x15, pos);507 }508 509 void510 vga_putc(const u_char c)511 {512 int x,y;513 514 x = console_global_data.orig_x;515 y = console_global_data.orig_y;516 517 if ( c == '\n' ) {518 if ( ++y >= console_global_data.lines ) {519 scroll();520 y--;521 }522 } else if (c == '\b') {523 if (x > 0) {524 x--;525 }526 } else if (c == '\r') {527 x = 0;528 } else {529 vidmem [ ( x + console_global_data.cols * y ) * 2 ] = c;530 if ( ++x >= console_global_data.cols ) {531 x = 0;532 if ( ++y >= console_global_data.lines ) {533 scroll();534 y--;535 }536 }537 }538 539 cursor(x, y);540 541 console_global_data.orig_x = x;542 console_global_data.orig_y = y;543 }544 #endif /* USE_VGA_SUPPORT */545 546 #ifdef USE_KBD_SUPPORT547 /* Keyboard support */548 static int kbd_getc(void)549 {550 unsigned char dt, brk, val;551 unsigned code;552 loop:553 while((kbd_inb(KBD_STATUS_REG) & KBD_STAT_OBF) == 0) ;554 555 dt = kbd_inb(KBD_DATA_REG);556 557 brk = dt & 0x80; /* brk == 1 on key release */558 dt = dt & 0x7f; /* keycode */559 560 if (console_global_data.shfts)561 code = shift_map[dt];562 else if (console_global_data.ctls)563 code = ctrl_map[dt];564 else565 code = plain_map[dt];566 567 val = KVAL(code);568 switch (KTYP(code) & 0x0f) {569 case KT_LATIN:570 if (brk)571 break;572 if (console_global_data.alts)573 val |= 0x80;574 if (val == 0x7f) /* map delete to backspace */575 val = '\b';576 return val;577 578 case KT_LETTER:579 if (brk)580 break;581 if (console_global_data.caps)582 val -= 'a'-'A';583 return val;584 585 case KT_SPEC:586 if (brk)587 break;588 if (val == KVAL(K_CAPS))589 console_global_data.caps = !console_global_data.caps;590 else if (val == KVAL(K_ENTER)) {591 enter: /* Wait for key up */592 while (1) {593 while((kbd_inb(KBD_STATUS_REG) & KBD_STAT_OBF) == 0) ;594 dt = kbd_inb(KBD_DATA_REG);595 if (dt & 0x80) /* key up */ break;596 }597 return 10;598 }599 break;600 601 case KT_PAD:602 if (brk)603 break;604 if (val < 10)605 return val;606 if (val == KVAL(K_PENTER))607 goto enter;608 break;609 610 case KT_SHIFT:611 switch (val) {612 case KG_SHIFT:613 case KG_SHIFTL:614 case KG_SHIFTR:615 console_global_data.shfts = brk ? 0 : 1;616 break;617 case KG_ALT:618 case KG_ALTGR:619 console_global_data.alts = brk ? 0 : 1;620 break;621 case KG_CTRL:622 case KG_CTRLL:623 case KG_CTRLR:624 console_global_data.ctls = brk ? 0 : 1;625 break;626 }627 break;628 629 case KT_LOCK:630 switch (val) {631 case KG_SHIFT:632 case KG_SHIFTL:633 case KG_SHIFTR:634 if (brk)635 console_global_data.shfts = !console_global_data.shfts;636 break;637 case KG_ALT:638 case KG_ALTGR:639 if (brk)640 console_global_data.alts = !console_global_data.alts;641 break;642 case KG_CTRL:643 case KG_CTRLL:644 case KG_CTRLR:645 if (brk)646 console_global_data.ctls = !console_global_data.ctls;647 break;648 }649 break;650 }651 /* if (brk) return (0); */ /* Ignore initial 'key up' codes */652 goto loop;653 }654 655 static int kbd_get(int ms) {656 int status, data;657 while(1) {658 status = kbd_inb(KBD_STATUS_REG);659 if (status & KBD_STAT_OBF) {660 data = kbd_inb(KBD_DATA_REG);661 if (status & (KBD_STAT_GTO | KBD_STAT_PERR))662 return -1;663 else664 return data;665 }666 if (--ms < 0) return -1;667 #ifdef __BOOT__668 boot_udelay(1000);669 #else670 rtems_bsp_delay(1000);671 #endif672 }673 }674 675 static void kbd_put(u_char c, int ms, int port) {676 while (kbd_inb(KBD_STATUS_REG) & KBD_STAT_IBF) {677 if (--ms < 0) return;678 #ifdef __BOOT__679 boot_udelay(1000);680 #else681 rtems_bsp_delay(1000);682 #endif683 }684 kbd_outb(port, c);685 }686 687 int kbdreset(void)688 {689 int c;690 691 /* Flush all pending data */692 while(kbd_get(10) != -1);693 694 /* Send self-test */695 kbd_put(KBD_CCMD_SELF_TEST, 10, KBD_CNTL_REG);696 c = kbd_get(1000);697 if (c != 0x55) return 1;698 699 /* Enable then reset the KB */700 kbd_put(KBD_CCMD_KBD_ENABLE, 10, KBD_CNTL_REG);701 702 while (1) {703 kbd_put(KBD_CMD_RESET, 10, KBD_DATA_REG);704 c = kbd_get(1000);705 if (c == KBD_REPLY_ACK) break;706 if (c != KBD_REPLY_RESEND) return 2;707 }708 709 if (kbd_get(1000) != KBD_REPLY_POR) return 3;710 711 /* Disable the keyboard while setting up the controller */712 kbd_put(KBD_CMD_DISABLE, 10, KBD_DATA_REG);713 if (kbd_get(10)!=KBD_REPLY_ACK) return 4;714 715 /* Enable interrupts and keyboard controller */716 kbd_put(KBD_CCMD_WRITE_MODE, 10, KBD_CNTL_REG);717 kbd_put(KBD_MODE_KBD_INT | KBD_MODE_SYS |718 KBD_MODE_DISABLE_MOUSE | KBD_MODE_KCC,719 10, KBD_DATA_REG);720 721 /* Reenable the keyboard */722 kbd_put(KBD_CMD_ENABLE, 10, KBD_DATA_REG);723 if (kbd_get(10)!=KBD_REPLY_ACK) return 5;724 725 return 0;726 }727 728 int kbd_tstc(void)729 {730 return ((kbd_inb(KBD_STATUS_REG) & KBD_STAT_OBF) != 0);731 }732 #endif /* USE_KBD_SUPPORT */733 734 const struct console_io735 vacuum_console_functions = {736 vacuum_putc,737 vacuum_getc,738 vacuum_tstc739 };740 741 static const struct console_io742 log_console_functions = {743 log_putc,744 vacuum_getc,745 vacuum_tstc746 }747 ,748 serial_console_functions = {749 serial_putc,750 serial_getc,751 serial_tstc752 }753 #if defined(USE_KBD_SUPPORT) && defined(USE_VGA_SUPPORT)754 ,755 vga_console_functions = {756 vga_putc,757 kbd_getc,758 kbd_tstc759 }760 #endif761 ;762 763 console_io* curIo = (console_io*) &vacuum_console_functions;764 765 int select_console(ioType t) {766 static ioType curType = CONSOLE_VACUUM;767 768 switch (t) {769 case CONSOLE_VACUUM : curIo = (console_io*)&vacuum_console_functions; break;770 case CONSOLE_LOG : curIo = (console_io*)&log_console_functions; break;771 case CONSOLE_SERIAL : curIo = (console_io*)&serial_console_functions; break;772 #if defined(USE_KBD_SUPPORT) && defined(USE_VGA_SUPPORT)773 case CONSOLE_VGA : curIo = (console_io*)&vga_console_functions; break;774 #endif775 default : curIo = (console_io*)&vacuum_console_functions;break;776 }777 if (curType == CONSOLE_LOG) flush_log();778 curType = t;779 return 0;780 }781 782 /* we use this so that we can do without the ctype library */783 #define is_digit(c) ((c) >= '0' && (c) <= '9')784 785 786 /* provide this for the bootloader only; otherwise787 * use libcpu implementation788 */789 #if defined(__BOOT__)790 static int skip_atoi(const char **s)791 {792 int i=0;793 794 while (is_digit(**s))795 i = i*10 + *((*s)++) - '0';796 return i;797 }798 799 /* Based on linux/lib/vsprintf.c and modified to suit our needs,800 * bloat has been limited since we basically only need %u, %x, %s and %c.801 * But we need 64 bit values !802 */803 int k_vsprintf(char *buf, const char *fmt, va_list args);804 805 int printk(const char *fmt, ...) {806 va_list args;807 int i;808 /* Should not be a problem with 8kB of stack */809 char buf[1024];810 811 va_start(args, fmt);812 i = k_vsprintf(buf, fmt, args);813 va_end(args);814 puts(buf);815 return i;816 }817 818 #endif819 820 /* Necessary to avoid including a library, and GCC won't do this inline. */821 #define div10(num, rmd) \822 do { u32 t1, t2, t3; \823 __asm__ ("lis %4,0xcccd; " \824 "addi %4,%4,0xffffcccd; " /* Build 0xcccccccd */ \825 "mulhwu %3,%0+1,%4; " /* (num.l*cst.l).h */ \826 "mullw %2,%0,%4; " /* (num.h*cst.l).l */ \827 "addc %3,%3,%2; " \828 "mulhwu %2,%0,%4; " /* (num.h*cst.l).h */ \829 "addi %4,%4,-1; " /* Build 0xcccccccc */ \830 "mullw %1,%0,%4; " /* (num.h*cst.h).l */ \831 "adde %2,%2,%1; " \832 "mulhwu %1,%0,%4; " /* (num.h*cst.h).h */ \833 "addze %1,%1; " \834 "mullw %0,%0+1,%4; " /* (num.l*cst.h).l */ \835 "addc %3,%3,%0; " \836 "mulhwu %0,%0+1,%4; " /* (num.l*cst.h).h */ \837 "adde %2,%2,%0; " \838 "addze %1,%1; " \839 "srwi %2,%2,3; " \840 "srwi %0,%1,3; " \841 "rlwimi %2,%1,29,0,2; " \842 "mulli %4,%2,10; " \843 "sub %4,%0+1,%4; " \844 "mr %0+1,%2; " : \845 "=r" (num), "=&r" (t1), "=&r" (t2), "=&r"(t3), "=&b" (rmd) : \846 "0" (num)); \847 \848 } while(0);849 850 #define SIGN 1 /* unsigned/signed long */851 #define LARGE 2 /* use 'ABCDEF' instead of 'abcdef' */852 #define HEX 4 /* hexadecimal instead of decimal */853 #define ADDR 8 /* Value is an addres (p) */854 #define ZEROPAD 16 /* pad with zero */855 #define HALF 32856 #define LONG 64 /* long argument */857 #define LLONG 128 /* 64 bit argument */858 859 #if defined(__BOOT__)860 static char * number(char * str, int size, int type, u64 num)861 {862 char fill,sign,tmp[24];863 const char *digits="0123456789abcdef";864 int i;865 866 if (type & LARGE)867 digits = "0123456789ABCDEF";868 fill = (type & ZEROPAD) ? '0' : ' ';869 sign = 0;870 if (type & SIGN) {871 if ((s64)num <0) {872 sign = '-';873 num = -num;874 size--;875 }876 }877 878 i = 0;879 do {880 unsigned rem;881 if (type&HEX) {882 rem = num & 0x0f;883 num >>=4;884 } else {885 div10(num, rem);886 }887 tmp[i++] = digits[rem];888 } while (num != 0);889 890 size -= i;891 if (!(type&(ZEROPAD)))892 while(size-->0)893 *str++ = ' ';894 if (sign)895 *str++ = sign;896 897 while (size-- > 0)898 *str++ = fill;899 while (i-- > 0)900 *str++ = tmp[i];901 while (size-- > 0)902 *str++ = ' ';903 return str;904 }905 906 int k_vsprintf(char *buf, const char *fmt, va_list args)907 {908 int len;909 u64 num;910 int i;911 char * str;912 const char *s;913 914 int flags; /* flags to number() and private */915 916 int field_width; /* width of output field */917 918 for (str=buf ; *fmt ; ++fmt) {919 if (*fmt != '%') {920 *str++ = *fmt;921 continue;922 }923 924 /* process flags, only 0 padding needed */925 flags = 0;926 if (*++fmt == '0' ) {927 flags |= ZEROPAD;928 fmt++;929 }930 931 /* get field width */932 field_width = -1;933 if (is_digit(*fmt))934 field_width = skip_atoi(&fmt);935 936 /* get the conversion qualifier */937 if (*fmt == 'h') {938 flags |= HALF;939 fmt++;940 } else if (*fmt == 'L') {941 flags |= LLONG;942 fmt++;943 } else if (*fmt == 'l') {944 flags |= LONG;945 fmt++;946 }947 948 switch (*fmt) {949 case 'c':950 *str++ = (unsigned char) va_arg(args, int);951 while (--field_width > 0)952 *str++ = ' ';953 continue;954 955 case 's':956 s = va_arg(args, char *);957 len = strlen(s);958 959 for (i = 0; i < len; ++i)960 *str++ = *s++;961 while (len < field_width--)962 *str++ = ' ';963 continue;964 965 case 'p':966 if (field_width == -1) {967 field_width = 2*sizeof(void *);968 }969 flags |= ZEROPAD|HEX|ADDR;970 break;971 972 case 'X':973 flags |= LARGE;974 case 'x':975 flags |= HEX;976 break;977 978 case 'd':979 case 'i':980 flags |= SIGN;981 case 'u':982 break;983 984 default:985 if (*fmt != '%')986 *str++ = '%';987 if (*fmt)988 *str++ = *fmt;989 else990 --fmt;991 continue;992 }993 /* This ugly code tries to minimize the number of va_arg()994 * since they expand to a lot of code on PPC under the SYSV995 * calling conventions (but not with -mcall-aix which has996 * other problems). Arguments have at least the size of a997 * long allocated, and we use this fact to minimize bloat.998 * (and pointers are assimilated to unsigned long too).999 */1000 if (sizeof(long long) > sizeof(long) && flags & LLONG)1001 num = va_arg(args, unsigned long long);1002 else {1003 u_long n = va_arg(args, unsigned long);1004 if (flags & HALF) {1005 if (flags & SIGN)1006 n = (short) n;1007 else1008 n = (unsigned short) n;1009 } else if (! flags & LONG) {1010 /* Here the compiler correctly removes this1011 * do nothing code on 32 bit PPC.1012 */1013 if (flags & SIGN)1014 n = (int) n;1015 else1016 n = (unsigned) n;1017 }1018 if (flags & SIGN) num = (long) n; else num = n;1019 }1020 str = number(str, field_width, flags, num);1021 }1022 *str = '\0';1023 return str-buf;1024 }1025 #endif1026 #endif -
deleted file c/src/lib/libbsp/powerpc/ep1a/console/printk_support.c
diff --git a/c/src/lib/libbsp/powerpc/ep1a/console/printk_support.c b/c/src/lib/libbsp/powerpc/ep1a/console/printk_support.c deleted file mode 100644 index e5b75f4..0000000
+ - 1 /*2 * This file contains the ep1a printk support routines.3 */4 5 /*6 * COPYRIGHT (c) 2011-2014.7 * On-Line Applications Research Corporation (OAR).8 *9 * The license and distribution terms for this file may be10 * found in the file LICENSE in this distribution or at11 * http://www.rtems.org/license/LICENSE.12 */13 14 #include <bsp.h>15 #include <rtems/libio.h>16 #include <stdlib.h>17 #include <assert.h>18 #include <termios.h>19 #include <rtems/bspIo.h>20 21 rtems_device_minor_number BSPPrintkPort = 0;22 23 /* const char arg to be compatible with BSP_output_char decl. */24 static void debug_putc_onlcr(const char c)25 {26 volatile int i;27 28 /*29 * Note: Hack to get printk to work. Depends upon bit30 * and silverchip to initialize the port and just31 * forces a character to be polled out of com132 * regardless of where the console is.33 */34 volatile unsigned char *ptr = (void *)0xff800000;35 36 if ('\n'==c){37 *ptr = '\r';38 __asm__ volatile("sync");39 for (i=0;i<0x0fff;i++);40 }41 42 *ptr = c;43 __asm__ volatile("sync");44 for (i=0;i<0x0fff;i++);45 }46 47 BSP_output_char_function_type BSP_output_char = debug_putc_onlcr;48 BSP_polling_getchar_function_type BSP_poll_char = NULL;49 -
deleted file c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.c
diff --git a/c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.c b/c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.c deleted file mode 100644 index deee170..0000000
+ - 1 /* rsPMCQ1.c - Radstone PMCQ1 Common Initialisation Code2 *3 * Copyright 2000 Radstone Technology4 *5 * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY6 * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE7 * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK8 * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.9 *10 * You are hereby granted permission to use, copy, modify, and distribute11 * this file, provided that this notice, plus the above copyright notice12 * and disclaimer, appears in all copies. Radstone Technology will provide13 * no support for this code.14 *15 * COPYRIGHT (c) 2005.16 * On-Line Applications Research Corporation (OAR).17 *18 * The license and distribution terms for this file may be19 * found in the file LICENSE in this distribution or at20 * http://www.rtems.org/license/LICENSE.21 *22 */23 24 /*25 DESCRIPTION26 These functions are responsible for scanning for PMCQ1's and setting up27 the Motorola MC68360's if present.28 29 USAGE30 call rsPMCQ1Init() to perform ba sic initialisation of the PMCQ1's.31 */32 33 /* includes */34 #include <libcpu/io.h>35 #include <bsp/irq.h>36 #include <stdlib.h>37 #include <rtems/bspIo.h>38 #include <bsp/pci.h>39 #include <bsp.h>40 #include "rsPMCQ1.h"41 #include "m68360.h"42 43 /* defines */44 #if 145 #define DEBUG_36046 #endif47 48 /* Local data */49 PPMCQ1BoardData pmcq1BoardData = NULL;50 51 static unsigned char rsPMCQ1Initialized = FALSE;52 53 /* forward declarations */54 55 static void MsDelay(void)56 {57 printk(".");58 }59 60 static void write8( int addr, int data ){61 out_8((uint8_t *)addr, (uint8_t)data);62 }63 64 static void write16( int addr, int data ) {65 out_be16((uint16_t *)addr, (uint16_t)data );66 }67 68 static void write32( int addr, int data ) {69 out_be32((uint32_t *)addr, (uint32_t)data );70 }71 72 static void rsPMCQ1_scc_nullFunc(void) {}73 74 /*******************************************************************************75 * rsPMCQ1Int - handle a PMCQ1 interrupt76 *77 * This routine gets called when the QUICC or MA causes78 * an interrupt.79 *80 * RETURNS: NONE.81 */82 83 static void rsPMCQ1Int( void *ptr )84 {85 unsigned long status;86 unsigned long status1;87 unsigned long mask;88 uint32_t data;89 PPMCQ1BoardData boardData = ptr;90 91 status = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS );92 mask = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_MASK );93 94 if (((mask & PMCQ1_INT_MASK_QUICC) == 0) && (status & PMCQ1_INT_STATUS_QUICC))95 {96 /* If there is a handler call it otherwise mask the interrupt */97 if (boardData->quiccInt) {98 boardData->quiccInt(boardData->quiccArg);99 } else {100 *(volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_QUICC;101 }102 }103 104 if (((mask & PMCQ1_INT_MASK_MA) == 0) && (status & PMCQ1_INT_STATUS_MA))105 {106 /* If there is a handler call it otherwise mask the interrupt */107 if (boardData->maInt) {108 boardData->maInt(boardData->maArg);109 110 data = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS );111 data &= (~PMCQ1_INT_STATUS_MA);112 PMCQ1_Write_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS, data );113 114 } else {115 *(volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_MA;116 }117 }118 119 RTEMS_COMPILER_MEMORY_BARRIER();120 121 /* Clear Interrupt on QSPAN */122 *(volatile unsigned long *)(boardData->bridgeaddr + 0x600) = 0x00001000;123 124 /* read back the status register to ensure that the pci write has completed */125 status1 = *(volatile unsigned long *)(boardData->bridgeaddr + 0x600);126 (void) status1; /* avoid set but not used warning */127 RTEMS_COMPILER_MEMORY_BARRIER();128 129 }130 131 132 /*******************************************************************************133 *134 * rsPMCQ1MaIntConnect - connect a MiniAce interrupt routine135 *136 * This routine is called to connect a MiniAce interrupt handler137 * upto a PMCQ1.138 *139 * RETURNS: OK if PMCQ1 found, ERROR if not.140 */141 142 unsigned int rsPMCQ1MaIntConnect (143 unsigned long busNo, /* Pci Bus number of PMCQ1 */144 unsigned long slotNo, /* Pci Slot number of PMCQ1 */145 unsigned long funcNo, /* Pci Function number of PMCQ1 */146 FUNCTION_PTR routine,/* interrupt routine */147 uintptr_t arg /* argument to pass to interrupt routine */148 )149 {150 PPMCQ1BoardData boardData;151 uint32_t data;152 unsigned int status = RTEMS_IO_ERROR;153 154 for (boardData = pmcq1BoardData; boardData; boardData = boardData->pNext)155 {156 if ((boardData->busNo == busNo) && (boardData->slotNo == slotNo) &&157 (boardData->funcNo == funcNo))158 {159 boardData->maInt = routine;160 boardData->maArg = arg;161 162 data = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_MASK );163 data &= (~PMCQ1_INT_MASK_MA);164 PMCQ1_Write_EPLD(boardData->baseaddr, PMCQ1_INT_MASK, data );165 166 data = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS );167 data &= (~PMCQ1_INT_STATUS_MA);168 PMCQ1_Write_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS, data );169 170 status = RTEMS_SUCCESSFUL;171 break;172 }173 }174 175 return (status);176 }177 178 /*******************************************************************************179 *180 * rsPMCQ1QuiccIntConnect - connect a Quicc interrupt routine181 *182 * This routine is called to connect a Quicc interrupt handler183 * upto a PMCQ1.184 *185 * RETURNS: OK if PMCQ1 found, ERROR if not.186 */187 unsigned int rsPMCQ1QuiccIntConnect(188 unsigned long busNo, /* Pci Bus number of PMCQ1 */189 unsigned long slotNo, /* Pci Slot number of PMCQ1 */190 unsigned long funcNo, /* Pci Function number of PMCQ1 */191 FUNCTION_PTR routine,/* interrupt routine */192 uintptr_t arg /* argument to pass to interrupt routine */193 )194 {195 PPMCQ1BoardData boardData;196 unsigned int status = RTEMS_IO_ERROR;197 198 for (boardData = pmcq1BoardData; boardData; boardData = boardData->pNext)199 {200 if ((boardData->busNo == busNo) && (boardData->slotNo == slotNo) &&201 (boardData->funcNo == funcNo))202 {203 boardData->quiccInt = routine;204 boardData->quiccArg = arg;205 status = RTEMS_SUCCESSFUL;206 break;207 }208 }209 return (status);210 }211 212 /*******************************************************************************213 *214 * rsPMCQ1Init - initialize the PMCQ1's215 *216 * This routine is called to initialize the PCI card to a quiescent state.217 *218 * RETURNS: OK if PMCQ1 found, ERROR if not.219 */220 221 unsigned int rsPMCQ1Init(void)222 {223 int busNo;224 int slotNo;225 uint32_t baseaddr = 0;226 uint32_t bridgeaddr = 0;227 unsigned long pbti0_ctl;228 int i;229 unsigned char int_vector;230 int fun;231 uint32_t temp;232 PPMCQ1BoardData boardData;233 rtems_irq_connect_data IrqData = {234 .name = 0,235 .hdl = rsPMCQ1Int,236 .handle = NULL,237 .on = (rtems_irq_enable) rsPMCQ1_scc_nullFunc,238 .off = (rtems_irq_disable) rsPMCQ1_scc_nullFunc,239 .isOn = (rtems_irq_is_enabled) rsPMCQ1_scc_nullFunc,240 };241 242 if (rsPMCQ1Initialized)243 {244 return RTEMS_SUCCESSFUL;245 }246 for (i=0;;i++){247 if ( pci_find_device(PCI_VEN_ID_RADSTONE, PCI_DEV_ID_PMCQ1, i, &busNo, &slotNo, &fun) != 0 )248 break;249 250 pci_read_config_dword(busNo, slotNo, 0, PCI_BASE_ADDRESS_2, &baseaddr);251 pci_read_config_dword(busNo, slotNo, 0, PCI_BASE_ADDRESS_0, &bridgeaddr);252 #ifdef DEBUG_360253 printk("PMCQ1 baseaddr 0x%08x bridgeaddr 0x%08x\n", baseaddr, bridgeaddr );254 #endif255 256 /* Set function code to normal mode and enable window */257 pbti0_ctl = *(unsigned long *)(bridgeaddr + 0x100) & 0xff0fffff;258 eieio();259 *(unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00500080;260 eieio();261 262 /* Assert QBUS reset */263 *(unsigned long *)(bridgeaddr + 0x800) |= 0x00000080;264 eieio();265 266 /*267 * Hold QBus in reset for 1ms268 */269 MsDelay();270 271 /* Take QBUS out of reset */272 *(unsigned long *)(bridgeaddr + 0x800) &= ~0x00000080;273 eieio();274 275 MsDelay();276 277 /* If a QUICC is fitted initialise it */278 if (PMCQ1_Read_EPLD(baseaddr, PMCQ1_BUILD_OPTION) & PMCQ1_QUICC_FITTED)279 {280 #ifdef DEBUG_360281 printk(" Found QUICC busNo %d slotNo %d\n", busNo, slotNo);282 #endif283 284 /* Initialise MBAR (must use function code of 7) */285 *(unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00700080;286 eieio();287 288 /* place internal 8K SRAM and registers at address 0x0 */289 *(unsigned long *)(baseaddr + Q1_360_MBAR) = 0x1;290 eieio();291 292 /* Set function code to normal mode */293 *(unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00500080;294 eieio();295 296 /* Disable the SWT and perform basic initialisation */297 write8(baseaddr+Q1_360_SIM_SYPCR,0);298 eieio();299 300 write32(baseaddr+Q1_360_SIM_MCR,0xa0001029);301 write16(baseaddr+Q1_360_SIM_PICR,0);302 write16(baseaddr+Q1_360_SIM_PITR,0);303 304 write16(baseaddr+Q1_360_CPM_ICCR,0x770);305 write16(baseaddr+Q1_360_CPM_SDCR,0x770);306 write32(baseaddr+Q1_360_CPM_CICR,0x00e49f00);307 write16(baseaddr+Q1_360_SIM_PEPAR,0x2080);308 eieio();309 310 /* Enable SRAM */311 write32(baseaddr+Q1_360_SIM_GMR,0x00001000); /* external master wait state */312 eieio();313 write32(baseaddr+Q1_360_SIM_OR0,0x1ff00000); /*| MEMC_OR_FC*/314 eieio();315 write32(baseaddr+Q1_360_SIM_BR0,0);316 eieio();317 write32(baseaddr+Q1_360_SIM_OR1,(0x5ff00000 | 0x00000780)); /*| MEMC_OR_FC*/318 eieio();319 write32(baseaddr+Q1_360_SIM_BR1,(0x00000040 | 0x00000001 | 0x00200280) );320 eieio();321 }322 323 /*324 * If a second PCI window is present then make it opposite325 * endian to simplify 1553 integration.326 */327 pci_read_config_dword(busNo, slotNo, 0, PCI_BASE_ADDRESS_3, &temp);328 if (temp) {329 *(unsigned long *)(bridgeaddr + 0x110) |= 0x00500880;330 }331 332 /*333 * Create descriptor structure for this card334 */335 if ((boardData = malloc(sizeof(struct _PMCQ1BoardData))) == NULL)336 {337 printk("Error Unable to allocate memory for _PMCQ1BoardData\n");338 return(RTEMS_IO_ERROR);339 }340 341 boardData->pNext = pmcq1BoardData;342 boardData->busNo = busNo;343 boardData->slotNo = slotNo;344 boardData->funcNo = 0;345 boardData->baseaddr = baseaddr;346 boardData->bridgeaddr = bridgeaddr;347 boardData->quiccInt = NULL;348 boardData->maInt = NULL;349 pmcq1BoardData = boardData;350 mc68360_scc_create_chip( boardData, int_vector );351 352 /*353 * Connect PMCQ1 interrupt handler.354 */355 pci_read_config_byte(busNo, slotNo, 0, 0x3c, &int_vector);356 #ifdef DEBUG_360357 printk("PMCQ1 int_vector %d\n", int_vector);358 #endif359 IrqData.name = ((unsigned int)BSP_PCI_IRQ0 + int_vector);360 IrqData.handle = boardData;361 if (!BSP_install_rtems_shared_irq_handler (&IrqData)) {362 printk("Error installing interrupt handler!\n");363 rtems_fatal_error_occurred(1);364 }365 366 /*367 * Enable PMCQ1 Interrupts from QSPAN-II368 */369 370 *(unsigned long *)(bridgeaddr + 0x600) = 0x00001000;371 eieio();372 *(unsigned long *)(bridgeaddr + 0x604) |= 0x00001000;373 374 eieio();375 }376 377 if (i > 0)378 {379 rsPMCQ1Initialized = TRUE;380 }381 return((i > 0) ? RTEMS_SUCCESSFUL : RTEMS_IO_ERROR);382 }383 384 uint32_t PMCQ1_Read_EPLD( uint32_t base, uint32_t reg )385 {386 uint32_t data;387 388 data = ( *((unsigned long *) (base + reg)) );389 #ifdef DEBUG_360390 printk("EPLD Read 0x%x: 0x%08x\n", reg + base, data );391 #endif392 return data;393 }394 395 void PMCQ1_Write_EPLD( uint32_t base, uint32_t reg, uint32_t data )396 {397 *((unsigned long *) (base + reg)) = data;398 #ifdef DEBUG_360399 printk("EPLD Write 0x%x: 0x%08x\n", reg+base, data );400 #endif401 }402 -
deleted file c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.h
diff --git a/c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.h b/c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.h deleted file mode 100644 index c0c0924..0000000
+ - 1 /* rsPMCQ1.h - Radstone PMCQ1 private header2 *3 * Copyright 2000 Radstone Technology4 *5 * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY6 * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE7 * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK8 * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU.9 *10 * You are hereby granted permission to use, copy, modify, and distribute11 * this file, provided that this notice, plus the above copyright notice12 * and disclaimer, appears in all copies. Radstone Technology will provide13 * no support for this code.14 *15 * COPYRIGHT (c) 2005.16 * On-Line Applications Research Corporation (OAR).17 *18 * The license and distribution terms for this file may be19 * found in the file LICENSE in this distribution or at20 * http://www.rtems.org/license/LICENSE.21 *22 */23 24 #include <libcpu/io.h>25 #include <bsp/irq.h>26 27 /*28 modification history29 --------------------30 01a,20Dec00,jpb created31 */32 33 #ifndef __INCPMCQ1H34 #define __INCPMCQ1H35 36 /*37 * PMCQ1 definitions38 */39 40 /*41 * 360 definitions42 */43 44 #define Q1_360_MBAR 0x0003ff00 /* master base address register */45 46 #define REG_B_OFFSET 0x1000 /* offset to the internal registers */47 48 #define Q1_360_SIM_MCR (REG_B_OFFSET+0x00)49 #define Q1_360_SIM_PEPAR (REG_B_OFFSET+0x16)50 #define Q1_360_SIM_SYPCR (REG_B_OFFSET+0x22)51 #define Q1_360_SIM_PICR (REG_B_OFFSET+0x26)52 #define Q1_360_SIM_PITR (REG_B_OFFSET+0x2A)53 #define Q1_360_SIM_GMR (REG_B_OFFSET+0x40)54 #define Q1_360_SIM_BR0 (REG_B_OFFSET+0x50)55 #define Q1_360_SIM_OR0 (REG_B_OFFSET+0x54)56 #define Q1_360_SIM_BR1 (REG_B_OFFSET+0x60)57 #define Q1_360_SIM_OR1 (REG_B_OFFSET+0x64)58 59 #define Q1_360_CPM_ICCR (REG_B_OFFSET+0x500)60 #define Q1_360_CPM_SDCR (REG_B_OFFSET+0x51E)61 #define Q1_360_CPM_CICR (REG_B_OFFSET+0x540)62 63 /*64 * EPLD offsets65 *66 * Only top 4 data bits are used67 */68 #define PMCQ1_CODE_VERSION 0x00040000 /* Code Version */69 70 #define PMCQ1_BOARD_REVISION 0x00040004 /* Board Revision */71 72 #define PMCQ1_BUILD_OPTION 0x00040008 /* Build Option */73 #define PMCQ1_ACE_FITTED 0x8000000074 #define PMCQ1_QUICC_FITTED 0x4000000075 #define PMCQ1_SRAM_SIZE 0x30000000 /* 01 - 1MB */76 #define PMCQ1_SRAM_FITTED 0x2000000077 78 #define PMCQ1_INT_STATUS 0x0004000c /* Interrupt Status */79 #define PMCQ1_INT_STATUS_MA 0x2000000080 #define PMCQ1_INT_STATUS_QUICC 0x1000000081 82 #define PMCQ1_INT_MASK 0x00040010 /* Interrupt Mask */83 #define PMCQ1_INT_MASK_QUICC 0x2000000084 #define PMCQ1_INT_MASK_MA 0x1000000085 86 #define PMCQ1_RT_ADDRESS 0x00040014 /* RT Address Latch */87 88 #define PMCQ1_DRIVER_ENABLE 0x0004001c /* Channel Drive Enable */89 #define PMCQ1_DRIVER_ENABLE_3 0x8000000090 #define PMCQ1_DRIVER_ENABLE_2 0x4000000091 #define PMCQ1_DRIVER_ENABLE_1 0x2000000092 #define PMCQ1_DRIVER_ENABLE_0 0x1000000093 94 #define PMCQ1_MINIACE_REGS 0x000c000095 #define PMCQ1_MINIACE_MEM 0x0010000096 #define PMCQ1_RAM 0x0020000097 98 /*99 #define PMCQ1_Read_EPLD( _base, _reg ) ( *((unsigned long *) ((unsigned32)_base + _reg)) )100 #define PMCQ1_Write_EPLD( _base, _reg, _data ) *((unsigned long *) ((unsigned32)_base + _reg)) = _data101 */102 uint32_t PMCQ1_Read_EPLD( uint32_t base, uint32_t reg );103 void PMCQ1_Write_EPLD( uint32_t base, uint32_t reg, uint32_t data );104 105 /*106 * QSPAN-II register offsets107 */108 109 #define QSPAN2_INT_STATUS 0x00000600110 111 typedef void (*FUNCTION_PTR) (int);112 113 #define PCI_ID(v, d) ((d << 16) | v)114 115 116 #define PCI_VEN_ID_RADSTONE 0x11b5117 #define PCI_DEV_ID_PMC1553 0x0001118 #define PCI_DEV_ID_PMCF1 0x0002119 #define PCI_DEV_ID_PMCMMA 0x0003120 #define PCI_DEV_ID_PMCQ1 0x0007121 #define PCI_DEV_ID_PMCQ2 0x0008122 #define PCI_DEV_ID_PMCF1V2 0x0012123 124 125 126 typedef struct _PMCQ1BoardData127 {128 struct _PMCQ1BoardData *pNext;129 unsigned long busNo;130 unsigned long slotNo;131 unsigned long funcNo;132 unsigned long baseaddr;133 unsigned long bridgeaddr;134 FUNCTION_PTR quiccInt;135 uintptr_t quiccArg;136 FUNCTION_PTR maInt;137 uintptr_t maArg;138 } PMCQ1BoardData, *PPMCQ1BoardData;139 140 extern PPMCQ1BoardData pmcq1BoardData;141 142 /*143 * Function declarations144 */145 extern unsigned int rsPMCQ1QuiccIntConnect(146 unsigned long busNo,147 unsigned long slotNo,148 unsigned long funcNo,149 FUNCTION_PTR routine,150 uintptr_t arg151 );152 153 unsigned int rsPMCQ1Init(void);154 155 unsigned int rsPMCQ1MaIntConnect (156 unsigned long busNo, /* Pci Bus number of PMCQ1 */157 unsigned long slotNo, /* Pci Slot number of PMCQ1 */158 unsigned long funcNo, /* Pci Function number of PMCQ1 */159 FUNCTION_PTR routine,/* interrupt routine */160 uintptr_t arg /* argument to pass to interrupt routine */161 );162 163 #endif /* __INCPMCQ1H */ -
deleted file c/src/lib/libbsp/powerpc/ep1a/include/bsp.h
diff --git a/c/src/lib/libbsp/powerpc/ep1a/include/bsp.h b/c/src/lib/libbsp/powerpc/ep1a/include/bsp.h deleted file mode 100644 index d989785..0000000
+ - 1 /*2 * COPYRIGHT (c) 1989-2008.3 * On-Line Applications Research Corporation (OAR).4 *5 * The license and distribution terms for this file may be6 * found in the file LICENSE in this distribution or at7 * http://www.rtems.org/license/LICENSE.8 */9 10 #ifndef LIBBSP_POWERPC_EP1A_BSP_H11 #define LIBBSP_POWERPC_EP1A_BSP_H12 13 #include <bspopts.h>14 #include <bsp/default-initial-extension.h>15 16 #include <rtems.h>17 #include <rtems/console.h>18 #include <libcpu/io.h>19 #include <rtems/clockdrv.h>20 #include <bsp/vectors.h>21 22 /* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */23 #define _IO_BASE CHRP_ISA_IO_BASE24 #define _ISA_MEM_BASE CHRP_ISA_MEM_BASE25 /* address of our ram on the PCI bus */26 #define PCI_DRAM_OFFSET CHRP_PCI_DRAM_OFFSET27 #define PCI_MEM_BASE 0x8000000028 #define PCI_MEM_BASE_ADJUSTMENT 029 /* address of our ram on the PCI bus */30 #define PCI_DRAM_OFFSET CHRP_PCI_DRAM_OFFSET31 32 /* offset of pci memory as seen from the CPU */33 #undef PCI_MEM_BASE34 #define PCI_MEM_BASE 0x0000000035 36 /* Override the default values for the following DEFAULT */37 #define PCI_CONFIG_ADDR 0xfec00000 /* 0xcf8 */38 #define PCI_CONFIG_DATA 0xfee00000 /* 0xcfc */39 40 /*41 * EP1A configuration Registers.42 * Note: All addresses assume flash boot.43 */44 45 #define EQUIPMENT_PRESENT_REGISTER1 ((volatile unsigned char *)0xffa00000)46 #define EQUIPMENT_PRESENT_REGISTER2 ((volatile unsigned char *)0xffa00008)47 #define BOARD_REVISION_REGISTER1 ((volatile unsigned char *)0xffa00010)48 #define BOARD_REVISION_REGISTER2 ((volatile unsigned char *)0xffa00018)49 #define GENERAL_REGISTER1 ((volatile unsigned char *)0xffa00020)50 #define GENERAL_REGISTER2 ((volatile unsigned char *)0xffa00028)51 #define WATCHDOG_TRIGGER ((volatile unsigned char *)0xffa00030)52 53 /* EQUIPMENT_PRESENT_REGISTER1 */54 #define BANK_MEMORY_SIZE_128MB 0x2055 #define BANK_MEMORY_SIZE_64MB 0x1056 #define ECC_ENABLED 0x0457 58 /* EQUIPMENT-PRESENT_REGISTER2 */59 #define PLL_CFG_MASK 0xf860 #define MHZ_33_66_200 0x70 /* PCI MEM CPU Frequency */61 #define MHZ_33_100_200 0x80 /* PCI MEM CPU Frequency */62 #define MHZ_33_66_266 0xb0 /* PCI MEM CPU Frequency */63 #define MHZ_33_66_333 0x50 /* PCI MEM CPU Frequency */64 #define MHZ_33_100_333 0x08 /* PCI MEM CPU Frequency */65 #define MHZ_33_100_350 0x78 /* PCI MEM CPU Frequency */66 67 #define PMC_SLOT1_PRESENT 0x0268 #define PMC_SLOT2_PRESENT 0x0169 70 /* BOARD_REVISION_REGISTER1 */71 #define ARTWORK_REVISION_MASK 0xf072 #define BUILD_REVISION_MASK 0x0f73 74 /* BOARD_REVISION_REGISTER2 */75 #define HARDWARE_ID_MASK 0xe076 #define HARDWARE_ID_PPC5_EP1A 0xe077 #define HARDWARE_ID_EP1B 0xc078 79 /* GENERAL_REGISTER1 */80 #define DISABLE_WATCHDOG 0x8081 #define DISABLE_RESET_SWITCH 0x4082 #define DISABLE_USER_FLASH 0x2083 #define DISABLE_BOOT_FLASH 0x1084 #define LED4_OFF 0x0885 #define LED3_OFF 0x0486 #define LED2_OFF 0x0287 #define LED1_OFF 0x0188 89 90 /* GENERAL_REGISTER2 */91 #define BSP_FLASH_VPP_ENABLE 0x0192 #define BSP_FLASH_PAGE_MASK 0x3893 #define BSP_FLASH_PAGE_SHIFT 0x0394 #define BSP_BIT_SLOWSTART 0x0495 #define BSP_OFFLINE 0x0296 #define BSP_SYSFAIL 0x0197 98 /* WATCHDOG_TRIGGER */99 #define BSP_FLASH_BASE 0xff000000100 #define BSP_VME_A16_BASE 0x9fff0000101 #define BSP_VME_A24_BASE 0x9f000000102 103 /*104 * address definitions for several devices105 *106 */107 #define UART_OFFSET_1_8245 (0x04500)108 #define UART_OFFSET_2_8245 (0x04600)109 #define UART_BASE_COM1 0xff800000110 #define UART_BASE_COM2 0xff800040111 112 #include <bsp/openpic.h>113 114 /* Note docs list 0x41000 but OpenPIC has a 0x1000 pad at the start115 * assume that open pic specifies this pad but not mentioned in116 * 8245 docs.117 * This is an offset from EUMBBAR118 */119 #define BSP_OPEN_PIC_BASE_OFFSET 0x40000120 121 /* BSP_PIC_DO_EOI is optionally used by the 'vmeUniverse' driver122 * to implement VME IRQ priorities in software.123 * Note that this requires support by the interrupt controller124 * driver (cf. libbsp/shared/powerpc/irq/openpic_i8259_irq.c)125 * and the BSP-specific universe initialization/configuration126 * (cf. libbsp/shared/powerpc/vme/VMEConfig.h vme_universe.c)127 *128 * ********* IMPORTANT NOTE ********129 * When deriving from this file (new BSPs)130 * DO NOT define "BSP_PIC_DO_EOI" if you don't know what131 * you are doing i.e., w/o implementing the required pieces132 * mentioned above.133 * ********* IMPORTANT NOTE ********134 */135 #define BSP_PIC_DO_EOI openpic_eoi(0)136 137 138 #ifndef ASM139 #define outport_byte(port,value) outb(value,port)140 #define outport_word(port,value) outw(value,port)141 #define outport_long(port,value) outl(value,port)142 143 #define inport_byte(port,value) (value = inb(port))144 #define inport_word(port,value) (value = inw(port))145 #define inport_long(port,value) (value = inl(port))146 147 /*148 * EUMMBAR149 */150 extern unsigned int EUMBBAR;151 152 /*153 * Total memory154 */155 extern unsigned int BSP_mem_size;156 157 /*158 * PCI Bus Frequency159 */160 extern unsigned int BSP_bus_frequency;161 162 /*163 * processor clock frequency164 */165 extern unsigned int BSP_processor_frequency;166 167 /*168 * Time base divisior (how many tick for 1 second).169 */170 extern unsigned int BSP_time_base_divisor;171 172 #define BSP_Convert_decrementer( _value ) \173 ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value)))174 175 #define Processor_Synchronize() \176 __asm__ (" eieio ")177 178 extern void BSP_panic(char *s);179 extern int BSP_disconnect_clock_handler (void);180 extern int BSP_connect_clock_handler (void);181 182 /*183 * FLASH184 */185 int BSP_FLASH_Enable_writes( uint32_t area );186 int BSP_FLASH_Disable_writes( uint32_t area );187 void BSP_FLASH_set_page( uint8_t page );188 189 #define BSP_FLASH_ENABLE_WRITES( _area) BSP_FLASH_Enable_writes( _area )190 #define BSP_FLASH_DISABLE_WRITES(_area) BSP_FLASH_Disable_writes( _area )191 #define BSP_FLASH_SET_PAGE(_page) BSP_FLASH_set_page( _page )192 193 /* clear hostbridge errors194 *195 * enableMCP: whether to enable MCP checkstop / machine check interrupts196 * on the hostbridge and in HID0.197 *198 * NOTE: HID0 and MEREN are left alone if this flag is 0199 *200 * quiet : be silent201 *202 * RETURNS : raven MERST register contents (lowermost 16 bits), 0 if203 * there were no errors204 */205 extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet);206 207 #endif208 209 #endif -
deleted file c/src/lib/libbsp/powerpc/ep1a/include/tm27.h
diff --git a/c/src/lib/libbsp/powerpc/ep1a/include/tm27.h b/c/src/lib/libbsp/powerpc/ep1a/include/tm27.h deleted file mode 100644 index 8f819a5..0000000
+ - 1 /*2 * @file3 * @ingroup powerpc_ep1a4 * @brief Implementations for interrupt mechanisms for Time Test 275 */6 7 /*8 * COPYRIGHT (c) 1989-2014.9 * On-Line Applications Research Corporation (OAR).10 *11 * The license and distribution terms for this file may be12 * found in the file LICENSE in this distribution or at13 * http://www.rtems.org/license/LICENSE.14 */15 16 #ifndef _RTEMS_TMTEST2717 #error "This is an RTEMS internal file you must not include directly."18 #endif19 20 #ifndef __tm27_h21 #define __tm27_h22 23 #include <bsp/irq.h>24 25 #define MUST_WAIT_FOR_INTERRUPT 126 27 void nullFunc() {}28 29 static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER,30 0,31 (rtems_irq_enable)nullFunc,32 (rtems_irq_disable)nullFunc,33 (rtems_irq_is_enabled) nullFunc};34 void Install_tm27_vector(void (*_handler)())35 {36 clockIrqData.hdl = _handler;37 if (!BSP_install_rtems_irq_handler (&clockIrqData)) {38 printk("Error installing clock interrupt handler!\n");39 rtems_fatal_error_occurred(1);40 }41 }42 43 #define Cause_tm27_intr() \44 do { \45 uint32_t _clicks = 8; \46 __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \47 } while (0)48 49 50 #define Clear_tm27_intr() \51 do { \52 uint32_t _clicks = 0xffffffff; \53 __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \54 } while (0)55 56 #define Lower_tm27_intr() \57 do { \58 uint32_t _msr = 0; \59 _ISR_Set_level( 0 ); \60 __asm__ volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \61 _msr |= 0x8002; \62 __asm__ volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \63 } while (0)64 #endif -
deleted file c/src/lib/libbsp/powerpc/ep1a/irq/irq_init.c
diff --git a/c/src/lib/libbsp/powerpc/ep1a/irq/irq_init.c b/c/src/lib/libbsp/powerpc/ep1a/irq/irq_init.c deleted file mode 100644 index cba05a4..0000000
+ - 1 /*2 * This file contains the implementation of rtems initialization3 * related to interrupt handling.4 */5 6 /*7 * CopyRight (C) 1999 valette@crf.canon.fr8 *9 * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com>10 * to make it valid for MVME2300 Motorola boards.11 *12 * Till Straumann <strauman@slac.stanford.edu>, 12/20/2001:13 * Use the new interface to openpic_init14 *15 * COPYRIGHT (c) 1989-2008.16 * On-Line Applications Research Corporation (OAR).17 *18 * The license and distribution terms for this file may be19 * found in the file LICENSE in this distribution or at20 * http://www.rtems.org/license/LICENSE.21 */22 23 #include <libcpu/io.h>24 #include <libcpu/spr.h>25 #include <bsp/pci.h>26 #include <bsp/residual.h>27 #include <bsp/openpic.h>28 #include <bsp/irq.h>29 #include <bsp.h>30 #include <bsp/vectors.h>31 #include <bsp/motorola.h>32 #include <rtems/bspIo.h>33 34 /*35 #define SHOW_ISA_PCI_BRIDGE_SETTINGS36 */37 #define TRACE_IRQ_INIT38 39 static void IRQ_Default_rtems_irq_hdl(40 rtems_irq_hdl_param ptr41 )42 {43 }44 45 static void IRQ_Default_rtems_irq_enable(46 const struct __rtems_irq_connect_data__ *ptr47 )48 {49 }50 51 static void IRQ_Default_rtems_irq_disable(52 const struct __rtems_irq_connect_data__ *ptr53 )54 {55 }56 57 static int IRQ_Default_rtems_irq_is_enabled(58 const struct __rtems_irq_connect_data__ *ptr)59 {60 return 1;61 }62 63 static rtems_irq_connect_data rtemsIrq[BSP_IRQ_NUMBER];64 static rtems_irq_global_settings initial_config;65 66 static rtems_irq_connect_data defaultIrq = {67 .name = 0,68 .hdl = IRQ_Default_rtems_irq_hdl,69 .handle = NULL,70 .on = IRQ_Default_rtems_irq_enable,71 .on = IRQ_Default_rtems_irq_disable,72 .isOn = IRQ_Default_rtems_irq_is_enabled73 };74 75 static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={76 /*77 * actual rpiorities for interrupt :78 * 0 means that only current interrupt is masked79 * 255 means all other interrupts are masked80 */81 /*82 * ISA interrupts.83 * The second entry has a priority of 255 because84 * it is the slave pic entry and is should always remain85 * unmasked.86 */87 0,0,88 255,89 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,90 /*91 * PCI Interrupts92 */93 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, /* for raven prio 0 means unactive... */94 /*95 * Processor exceptions handled as interrupts96 */97 098 };99 100 static unsigned char mcp750_openpic_initpolarities[] = {101 1, /* 0 8259 cascade */102 0, /* 1 all the rest of them */103 0, /* 2 all the rest of them */104 0, /* 3 all the rest of them */105 0, /* 4 all the rest of them */106 0, /* 5 all the rest of them */107 0, /* 6 all the rest of them */108 0, /* 7 all the rest of them */109 0, /* 8 all the rest of them */110 0, /* 9 all the rest of them */111 0, /* 10 all the rest of them */112 0, /* 11 all the rest of them */113 0, /* 12 all the rest of them */114 0, /* 13 all the rest of them */115 0, /* 14 all the rest of them */116 0, /* 15 all the rest of them */117 0, /* 16 all the rest of them */118 0, /* 17 all the rest of them */119 1, /* 18 all the rest of them */120 1, /* 19 all the rest of them */121 1, /* 20 all the rest of them */122 1, /* 21 all the rest of them */123 1, /* 22 all the rest of them */124 1, /* 23 all the rest of them */125 1, /* 24 all the rest of them */126 1, /* 25 all the rest of them */127 };128 129 static unsigned char mcp750_openpic_initsenses[] = {130 1, /* 0 MCP750_INT_PCB(8259) */131 0, /* 1 MCP750_INT_FALCON_ECC_ERR */132 1, /* 2 MCP750_INT_PCI_ETHERNET */133 1, /* 3 MCP750_INT_PCI_PMC */134 1, /* 4 MCP750_INT_PCI_WATCHDOG_TIMER1 */135 1, /* 5 MCP750_INT_PCI_PRST_SIGNAL */136 1, /* 6 MCP750_INT_PCI_FALL_SIGNAL */137 1, /* 7 MCP750_INT_PCI_DEG_SIGNAL */138 1, /* 8 MCP750_INT_PCI_BUS1_INTA */139 1, /* 9 MCP750_INT_PCI_BUS1_INTB */140 1, /*10 MCP750_INT_PCI_BUS1_INTC */141 1, /*11 MCP750_INT_PCI_BUS1_INTD */142 1, /*12 MCP750_INT_PCI_BUS2_INTA */143 1, /*13 MCP750_INT_PCI_BUS2_INTB */144 1, /*14 MCP750_INT_PCI_BUS2_INTC */145 1, /*15 MCP750_INT_PCI_BUS2_INTD */146 1,147 1,148 1,149 1,150 1,151 1,152 1,153 1,154 1,155 1156 };157 158 /*159 * This code assumes the exceptions management setup has already160 * been done. We just need to replace the exceptions that will161 * be handled like interrupt. On mcp750/mpc750 and many PPC processors162 * this means the decrementer exception and the external exception.163 */164 void BSP_rtems_irq_mng_init(unsigned cpuId)165 {166 int i;167 168 /*169 * First initialize the Interrupt management hardware170 */171 #ifdef TRACE_IRQ_INIT172 printk("Going to initialize openpic compliant device\n");173 #endif174 /* FIXME (t.s.): we should probably setup the EOI delay by175 * passing a non-zero 'epic_freq' argument (frequency of the176 * EPIC serial interface) but I don't know the value on this177 * board (8245 SDRAM freq, IIRC)...178 */179 openpic_init(1, mcp750_openpic_initpolarities, mcp750_openpic_initsenses, 0, 16, 0 /* epic_freq */);180 181 #ifdef TRACE_IRQ_INIT182 printk("Going to initialize the PCI/ISA bridge IRQ related setting (VIA 82C586)\n");183 #endif184 185 /*186 * Initialize Rtems management interrupt table187 */188 /*189 * re-init the rtemsIrq table190 */191 for (i = 0; i < BSP_IRQ_NUMBER; i++) {192 rtemsIrq[i] = defaultIrq;193 rtemsIrq[i].name = i;194 }195 /*196 * Init initial Interrupt management config197 */198 initial_config.irqNb = BSP_IRQ_NUMBER;199 initial_config.defaultEntry = defaultIrq;200 initial_config.irqHdlTbl = rtemsIrq;201 initial_config.irqBase = BSP_LOWEST_OFFSET;202 initial_config.irqPrioTbl = irqPrioTable;203 204 printk("Call BSP_rtems_irq_mngt_set\n");205 if (!BSP_rtems_irq_mngt_set(&initial_config)) {206 /*207 * put something here that will show the failure...208 */209 BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n");210 }211 212 #ifdef TRACE_IRQ_INIT213 printk("RTEMS IRQ management is now operationnal\n");214 #endif215 }216 -
deleted file c/src/lib/libbsp/powerpc/ep1a/irq/openpic_xxx_irq.c
diff --git a/c/src/lib/libbsp/powerpc/ep1a/irq/openpic_xxx_irq.c b/c/src/lib/libbsp/powerpc/ep1a/irq/openpic_xxx_irq.c deleted file mode 100644 index 23b1ce2..0000000
+ - 1 /*2 * This file contains the i8259/openpic-specific implementation of3 * the function described in irq.h4 *5 * Copyright (C) 1998, 1999 valette@crf.canon.fr6 *7 * The license and distribution terms for this file may be8 * found in the file LICENSE in this distribution or at9 * http://www.rtems.org/license/LICENSE.10 */11 12 #include <stdlib.h>13 14 #include <bsp.h>15 #include <bsp/irq.h>16 #include <bsp/irq_supp.h>17 #include <bsp/VMEConfig.h>18 #include <bsp/openpic.h>19 #include <libcpu/io.h>20 #include <bsp/vectors.h>21 #include <stdlib.h>22 23 #include <rtems/bspIo.h> /* for printk */24 #define RAVEN_INTR_ACK_REG 0xfeff003025 26 #ifdef BSP_PCI_ISA_BRIDGE_IRQ27 /*28 * pointer to the mask representing the additionnal irq vectors29 * that must be disabled when a particular entry is activated.30 * They will be dynamically computed from the priority table given31 * in BSP_rtems_irq_mngt_set();32 * CAUTION : this table is accessed directly by interrupt routine33 * prologue.34 */35 rtems_i8259_masks irq_mask_or_tbl[BSP_IRQ_NUMBER];36 #endif37 38 /*39 * default handler connected on each irq after bsp initialization40 */41 static rtems_irq_connect_data default_rtems_entry;42 43 static rtems_irq_connect_data* rtems_hdl_tbl;44 45 #ifdef BSP_PCI_ISA_BRIDGE_IRQ46 /*47 * Check if IRQ is an ISA IRQ48 */49 static inline int is_isa_irq(const rtems_irq_number irqLine)50 {51 return (((int) irqLine <= BSP_ISA_IRQ_MAX_OFFSET) &52 ((int) irqLine >= BSP_ISA_IRQ_LOWEST_OFFSET)53 );54 }55 #endif56 57 /*58 * Check if IRQ is an OPENPIC IRQ59 */60 static inline int is_pci_irq(const rtems_irq_number irqLine)61 {62 return (((int) irqLine <= BSP_PCI_IRQ_MAX_OFFSET) &63 ((int) irqLine >= BSP_PCI_IRQ_LOWEST_OFFSET)64 );65 }66 67 /*68 * ------------------------ RTEMS Irq helper functions ----------------69 */70 void71 BSP_enable_irq_at_pic(const rtems_irq_number name)72 {73 #ifdef BSP_PCI_ISA_BRIDGE_IRQ74 if (is_isa_irq(name)) {75 /*76 * Enable interrupt at PIC level77 */78 printk("ERROR BSP_irq_enable_at_i8259s Being Called for %d\n", (int)name);79 BSP_irq_enable_at_i8259s ((int) name);80 }81 #endif82 83 if (is_pci_irq(name)) {84 /*85 * Enable interrupt at OPENPIC level86 */87 printk(" openpic_enable_irq %d\n", (int)name );88 openpic_enable_irq ((int) name);89 }90 }91 92 int93 BSP_disable_irq_at_pic(const rtems_irq_number name)94 {95 #ifdef BSP_PCI_ISA_BRIDGE_IRQ96 if (is_isa_irq(name)) {97 /*98 * disable interrupt at PIC level99 */100 return BSP_irq_disable_at_i8259s ((int) name);101 }102 #endif103 if (is_pci_irq(name)) {104 /*105 * disable interrupt at OPENPIC level106 */107 return openpic_disable_irq ((int) name );108 }109 return -1;110 }111 112 /*113 * RTEMS Global Interrupt Handler Management Routines114 */115 int BSP_setup_the_pic(rtems_irq_global_settings* config)116 {117 int i;118 /*119 * Store various code accelerators120 */121 default_rtems_entry = config->defaultEntry;122 rtems_hdl_tbl = config->irqHdlTbl;123 124 /*125 * continue with PCI IRQ126 */127 for (i=BSP_PCI_IRQ_LOWEST_OFFSET; i < BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER ; i++) {128 /*129 * Note that openpic_set_priority() sets the TASK priority of the PIC130 */131 openpic_set_source_priority(i - BSP_PCI_IRQ_LOWEST_OFFSET,132 config->irqPrioTbl[i]);133 if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {134 openpic_enable_irq ((int) i );135 }136 else {137 openpic_disable_irq ((int) i );138 }139 }140 141 #ifdef BSP_PCI_ISA_BRIDGE_IRQ142 if ( BSP_ISA_IRQ_NUMBER > 0 ) {143 /*144 * Must enable PCI/ISA bridge IRQ145 */146 openpic_enable_irq (0);147 }148 #endif149 150 return 1;151 }152 153 int _BSP_vme_bridge_irq = -1;154 155 unsigned BSP_spuriousIntr = 0;156 157 /*158 * High level IRQ handler called from shared_raw_irq_code_entry159 */160 int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum)161 {162 register unsigned int irq;163 #ifdef BSP_PCI_ISA_BRIDGE_IRQ164 register unsigned isaIntr; /* boolean */165 register unsigned oldMask = 0; /* old isa pic masks */166 register unsigned newMask; /* new isa pic masks */167 #endif168 169 if (excNum == ASM_DEC_VECTOR) {170 /* printk("ASM_DEC_VECTOR\n"); */171 bsp_irq_dispatch_list(rtems_hdl_tbl, BSP_DECREMENTER, default_rtems_entry.hdl);172 173 return 0;174 175 }176 irq = openpic_irq(0);177 if (irq == OPENPIC_VEC_SPURIOUS) {178 /* printk("OPENPIC_VEC_SPURIOUS interrupt %d\n", OPENPIC_VEC_SPURIOUS ); */179 ++BSP_spuriousIntr;180 return 0;181 }182 183 /* some BSPs might want to use a different numbering... */184 irq = irq - OPENPIC_VEC_SOURCE + BSP_PCI_IRQ_LOWEST_OFFSET;185 /* printk("OpenPic Irq: %d\n", irq); */186 187 #ifdef BSP_PCI_ISA_BRIDGE_IRQ188 isaIntr = (irq == BSP_PCI_ISA_BRIDGE_IRQ);189 if (isaIntr) {190 /* printk("BSP_PCI_ISA_BRIDGE_IRQ\n"); */191 /*192 * Acknowledge and read 8259 vector193 */194 irq = (unsigned int) (*(unsigned char *) RAVEN_INTR_ACK_REG);195 /*196 * store current PIC mask197 */198 oldMask = i8259s_cache;199 newMask = oldMask | irq_mask_or_tbl [irq];200 i8259s_cache = newMask;201 outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff);202 outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));203 BSP_irq_ack_at_i8259s (irq);204 openpic_eoi(0);205 }206 #endif207 208 209 /* dispatch handlers */210 /* printk("dispatch\n"); */211 irq -=16;212 bsp_irq_dispatch_list(rtems_hdl_tbl, irq, default_rtems_entry.hdl);213 /* printk("Back from dispatch\n"); */214 215 #ifdef BSP_PCI_ISA_BRIDGE_IRQ216 if (isaIntr) {\217 i8259s_cache = oldMask;218 outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff);219 outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));220 }221 else222 #endif223 {224 #ifdef BSP_PCI_VME_DRIVER_DOES_EOI225 /* leave it to the VME bridge driver to do EOI, so226 * it can re-enable the openpic while handling227 * VME interrupts (-> VME priorities in software)228 */229 if (_BSP_vme_bridge_irq != irq)230 #endif231 openpic_eoi(0);232 }233 return 0;234 } -
deleted file c/src/lib/libbsp/powerpc/ep1a/make/custom/ep1a.cfg
diff --git a/c/src/lib/libbsp/powerpc/ep1a/make/custom/ep1a.cfg b/c/src/lib/libbsp/powerpc/ep1a/make/custom/ep1a.cfg deleted file mode 100644 index 2b2c2d2..0000000
+ - 1 #2 # Config file for the Radstone PowerPC 8245 ep1a3 #4 #5 6 include $(RTEMS_ROOT)/make/custom/default.cfg7 8 RTEMS_CPU=powerpc9 RTEMS_CPU_MODEL=mpc824510 11 # This contains the compiler options necessary to select the CPU model12 # and (hopefully) optimize for it.13 #14 CPU_CFLAGS = -mcpu=603e -Dppc603e -mmultiple -mstring -mstrict-align15 16 # optimize flag: typically -O217 CFLAGS_OPTIMIZE_V = -O2 -g -
deleted file c/src/lib/libbsp/powerpc/ep1a/pci/no_host_bridge.c
diff --git a/c/src/lib/libbsp/powerpc/ep1a/pci/no_host_bridge.c b/c/src/lib/libbsp/powerpc/ep1a/pci/no_host_bridge.c deleted file mode 100644 index 123f793..0000000
+ - 1 /*2 * COPYRIGHT (c) 1989-2008.3 * On-Line Applications Research Corporation (OAR).4 *5 * The license and distribution terms for this file may be6 * found in the file LICENSE in this distribution or at7 * http://www.rtems.org/license/LICENSE.8 */9 10 #include <libcpu/io.h>11 #include <libcpu/spr.h>12 13 #include <bsp.h>14 #include <bsp/pci.h>15 #include <bsp/consoleIo.h>16 #include <bsp/residual.h>17 #include <bsp/openpic.h>18 19 #include <rtems/bspIo.h>20 21 /*22 * For the 8240 and the 8245 there is no host bridge the23 * Open PIC device is built into the processor chip.24 */25 void detect_host_bridge(void)26 {27 OpenPIC=(volatile struct OpenPIC *) (EUMBBAR + BSP_OPEN_PIC_BASE_OFFSET );28 } -
deleted file c/src/lib/libbsp/powerpc/ep1a/preinstall.am
diff --git a/c/src/lib/libbsp/powerpc/ep1a/preinstall.am b/c/src/lib/libbsp/powerpc/ep1a/preinstall.am deleted file mode 100644 index 88a9e13..0000000
+ - 1 ## Automatically generated by ampolish3 - Do not edit2 3 if AMPOLISH34 $(srcdir)/preinstall.am: Makefile.am5 $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am6 endif7 8 PREINSTALL_DIRS =9 DISTCLEANFILES += $(PREINSTALL_DIRS)10 11 all-am: $(PREINSTALL_FILES)12 13 PREINSTALL_FILES =14 CLEANFILES = $(PREINSTALL_FILES)15 16 all-local: $(TMPINSTALL_FILES)17 18 TMPINSTALL_FILES =19 CLEANFILES += $(TMPINSTALL_FILES)20 21 $(PROJECT_LIB)/$(dirstamp):22 @$(MKDIR_P) $(PROJECT_LIB)23 @: > $(PROJECT_LIB)/$(dirstamp)24 PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp)25 26 $(PROJECT_INCLUDE)/$(dirstamp):27 @$(MKDIR_P) $(PROJECT_INCLUDE)28 @: > $(PROJECT_INCLUDE)/$(dirstamp)29 PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)30 31 $(PROJECT_INCLUDE)/bsp/$(dirstamp):32 @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp33 @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp)34 PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp)35 36 $(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp)37 $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs38 PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs39 40 $(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp)41 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h42 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h43 44 $(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)45 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h46 PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h47 48 $(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)49 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h50 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h51 52 $(PROJECT_INCLUDE)/bsp/bootcard.h: ../../shared/include/bootcard.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)53 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bootcard.h54 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bootcard.h55 56 $(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp)57 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h58 PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h59 60 $(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp)61 $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds62 PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds63 64 $(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)65 $(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT)66 TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT)67 68 $(PROJECT_LIB)/rtems_crti.$(OBJEXT): rtems_crti.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)69 $(INSTALL_DATA) $< $(PROJECT_LIB)/rtems_crti.$(OBJEXT)70 TMPINSTALL_FILES += $(PROJECT_LIB)/rtems_crti.$(OBJEXT)71 72 $(PROJECT_INCLUDE)/bsp/uart.h: ../../powerpc/shared/console/uart.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)73 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/uart.h74 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/uart.h75 76 $(PROJECT_INCLUDE)/bsp/motorola.h: ../../powerpc/shared/motorola/motorola.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)77 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/motorola.h78 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/motorola.h79 80 $(PROJECT_INCLUDE)/bsp/residual.h: ../../powerpc/shared/residual/residual.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)81 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/residual.h82 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/residual.h83 84 $(PROJECT_INCLUDE)/bsp/pnp.h: ../../powerpc/shared/residual/pnp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)85 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/pnp.h86 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/pnp.h87 88 $(PROJECT_INCLUDE)/bsp/consoleIo.h: ../../powerpc/shared/console/consoleIo.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)89 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/consoleIo.h90 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/consoleIo.h91 92 $(PROJECT_INCLUDE)/bsp/rsPMCQ1.h: console/rsPMCQ1.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)93 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/rsPMCQ1.h94 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/rsPMCQ1.h95 96 $(PROJECT_INCLUDE)/bsp/console_private.h: ../../shared/console_private.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)97 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/console_private.h98 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/console_private.h99 100 $(PROJECT_INCLUDE)/bsp/openpic.h: ../../powerpc/shared/openpic/openpic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)101 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/openpic.h102 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/openpic.h103 104 $(PROJECT_INCLUDE)/bsp/pci.h: ../../powerpc/shared/pci/pci.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)105 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/pci.h106 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/pci.h107 108 $(PROJECT_INCLUDE)/bsp/irq.h: ../../powerpc/shared/irq/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)109 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h110 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h111 112 $(PROJECT_INCLUDE)/bsp/irq_supp.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)113 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq_supp.h114 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq_supp.h115 116 $(PROJECT_INCLUDE)/bsp/vmeUniverse.h: ../../shared/vmeUniverse/vmeUniverse.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)117 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vmeUniverse.h118 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vmeUniverse.h119 120 $(PROJECT_INCLUDE)/bsp/VMEConfig.h: vme/VMEConfig.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)121 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/VMEConfig.h122 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/VMEConfig.h123 124 $(PROJECT_INCLUDE)/bsp/vme_am_defs.h: ../../shared/vmeUniverse/vme_am_defs.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)125 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vme_am_defs.h126 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vme_am_defs.h127 128 $(PROJECT_INCLUDE)/bsp/VME.h: ../../shared/vmeUniverse/VME.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)129 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/VME.h130 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/VME.h131 132 $(PROJECT_INCLUDE)/bsp/vmeUniverseDMA.h: ../../shared/vmeUniverse/vmeUniverseDMA.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)133 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vmeUniverseDMA.h134 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vmeUniverseDMA.h135 136 $(PROJECT_INCLUDE)/bsp/bspVmeDmaList.h: ../../shared/vmeUniverse/bspVmeDmaList.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)137 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bspVmeDmaList.h138 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bspVmeDmaList.h139 140 $(PROJECT_INCLUDE)/bsp/VMEDMA.h: ../../shared/vmeUniverse/VMEDMA.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)141 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/VMEDMA.h142 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/VMEDMA.h143 -
deleted file c/src/lib/libbsp/powerpc/ep1a/start/start.S
diff --git a/c/src/lib/libbsp/powerpc/ep1a/start/start.S b/c/src/lib/libbsp/powerpc/ep1a/start/start.S deleted file mode 100644 index 51596ac..0000000
+ - 1 /*2 * This is based on the mvme-crt0.S file from libgloss/rs6000.3 * crt0.S -- startup file for PowerPC systems.4 *5 * (c) 1998, Radstone Technology plc.6 *7 *8 * This is an unpublished work the copyright in which vests9 * in Radstone Technology plc. All rights reserved.10 *11 * The information contained herein is the property of Radstone12 * Technology plc. and is supplied without liability for13 * errors or omissions and no part may be reproduced, used or14 * disclosed except as authorized by contract or other written15 * permission. The copyright and the foregoing16 * restriction on reproduction, use and disclosure extend to17 * all the media in which this information may be18 * embodied.19 *20 * Copyright (c) 1995 Cygnus Support21 *22 * The authors hereby grant permission to use, copy, modify, distribute,23 * and license this software and its documentation for any purpose, provided24 * that existing copyright notices are retained in all copies and that this25 * notice is included verbatim in any distributions. No written agreement,26 * license, or royalty fee is required for any of the authorized uses.27 * Modifications to this software may be copyrighted by their authors28 * and need not follow the licensing terms described here, provided that29 * the new terms are clearly indicated on the first page of each file where30 * they apply.31 */32 /*33 #include <ppc-asm.h>34 #include <bsp.h>35 */36 37 #include <rtems/asm.h>38 #include <rtems/score/cpu.h>39 #include <libcpu/io.h>40 #include <ppc-asm.h>41 42 #define H0_60X_ICE 0x8000 /* HID0 I-Cache Enable */43 #define H0_60X_DCE 0x4000 /* HID0 D-Cache Enable */44 45 .file "start.s"46 47 .extern FUNC_NAME(atexit)48 .globl FUNC_NAME(__atexit)49 .section ".sdata","aw"50 .align 251 FUNC_NAME(__atexit): /* tell C's eabi-ctor's we have an atexit function */52 .long FUNC_NAME(atexit)@fixup /* and that it is to register __do_global_dtors */53 54 .section ".fixup","aw"55 .align 256 .long FUNC_NAME(__atexit)57 58 .text59 .globl __rtems_entry_point60 .type __rtems_entry_point,@function61 __rtems_entry_point:62 63 /* Set MSR */64 /*65 * Enable data and instruction address translation and floating point66 */67 li r3,MSR_IR | MSR_DR | MSR_FP68 mtmsr r369 70 /* XXX - ADD BACK IN CACHING INSTRUCTIONS */71 72 /* clear bss */73 lis r6,__bss_start@h74 ori r6,r6,__bss_start@l75 lis r7,__bss_end@h76 ori r7,r7,__bss_end@l77 78 cmplw 1,r6,r779 bc 4,4,.Lbss_done80 81 subf r8,r6,r7 /* number of bytes to zero */82 srwi r9,r8,2 /* number of words to zero */83 mtctr r984 li r0,0 /* zero to clear memory */85 addi r6,r6,-4 /* adjust so we can use stwu */86 .Lbss_loop:87 stwu r0,4(r6) /* zero bss */88 bdnz .Lbss_loop89 90 .Lbss_done:91 92 /* clear sbss */93 lis r6,__sbss_start@h94 ori r6,r6,__sbss_start@l95 lis r7,__sbss_end@h96 ori r7,r7,__sbss_end@l97 98 cmplw 1,r6,r799 bc 4,4,.Lsbss_done100 101 subf r8,r6,r7 /* number of bytes to zero */102 srwi r9,r8,2 /* number of words to zero */103 mtctr r9104 li r0,0 /* zero to clear memory */105 addi r6,r6,-4 /* adjust so we can use stwu */106 .Lsbss_loop:107 stwu r0,4(r6) /* zero sbss */108 bdnz .Lsbss_loop109 110 .Lsbss_done:111 112 lis sp,__stack@h113 ori sp,sp,__stack@l114 115 /* set up initial stack frame */116 addi sp,sp,-4 /* make sure we don't overwrite debug mem */117 lis r0,0118 stw r0,0(sp) /* clear back chain */119 stwu sp,-56(sp) /* push another stack frame */120 121 li r3, 0 /* command line */122 123 /* Let her rip */124 bl FUNC_NAME(boot_card)125 126 /*127 * This should never get reached128 */129 /*130 * Return MSR to its reset state131 */132 li r3,0133 mtmsr r3134 isync135 136 /*137 * Call reset entry point138 */139 lis r3,0xfff0140 ori r3,r3,0x100141 mtlr r3142 blr143 .Lstart:144 .size __rtems_entry_point,.Lstart-__rtems_entry_point145 146 .comm environ,4,4 -
deleted file c/src/lib/libbsp/powerpc/ep1a/startup/bspstart.c
diff --git a/c/src/lib/libbsp/powerpc/ep1a/startup/bspstart.c b/c/src/lib/libbsp/powerpc/ep1a/startup/bspstart.c deleted file mode 100644 index dc675e2..0000000
+ - 1 /*2 * This routine does the bulk of the system initialization.3 */4 5 /*6 * COPYRIGHT (c) 1989-2014.7 * On-Line Applications Research Corporation (OAR).8 *9 * The license and distribution terms for this file may be10 * found in the file LICENSE in this distribution or at11 * http://www.rtems.org/license/LICENSE.12 */13 14 #include <bsp/consoleIo.h>15 #include <bsp/bootcard.h>16 #include <libcpu/spr.h>17 #include <bsp/residual.h>18 #include <bsp/pci.h>19 #include <bsp/openpic.h>20 #include <bsp/irq.h>21 #include <bsp/VME.h>22 #include <bsp.h>23 #include <libcpu/bat.h>24 #include <libcpu/pte121.h>25 #include <libcpu/cpuIdent.h>26 #include <bsp/vectors.h>27 #include <rtems/powerpc/powerpc.h>28 #include <rtems/counter.h>29 30 extern unsigned long __bss_start[], __SBSS_START__[], __SBSS_END__[];31 extern unsigned long __SBSS2_START__[], __SBSS2_END__[];32 33 extern unsigned long __rtems_end[];34 extern void L1_caches_enables(void);35 extern unsigned get_L2CR(void);36 extern void set_L2CR(unsigned);37 extern Triv121PgTbl BSP_pgtbl_setup(void);38 extern void BSP_pgtbl_activate(Triv121PgTbl);39 extern void BSP_vme_config(void);40 extern void ShowBATS(void);41 unsigned int rsPMCQ1Init(void);42 43 uint32_t bsp_clicks_per_usec;44 45 SPR_RW(SPRG1)46 47 uint8_t LightIdx = 0;48 49 extern int RAM_END;50 unsigned int BSP_mem_size = (unsigned int)&RAM_END;51 52 static void BSP_Increment_Light(void)53 {54 uint8_t data;55 56 data = *GENERAL_REGISTER1;57 data &= 0xf0;58 data |= LightIdx++;59 *GENERAL_REGISTER1 = data;60 }61 62 /*63 * Vital Board data Start using DATA RESIDUAL64 */65 uint32_t VME_Slot1 = FALSE;66 67 /*68 * PCI Bus Frequency69 */70 unsigned int BSP_bus_frequency;71 72 /*73 * processor clock frequency74 */75 unsigned int BSP_processor_frequency;76 77 /*78 * Time base divisior (how many tick for 1 second).79 */80 unsigned int BSP_time_base_divisor = 1000; /* XXX - Just a guess */81 82 void BSP_panic(char *s)83 {84 printk("%s PANIC %s\n",_RTEMS_version, s);85 __asm__ __volatile ("sc");86 }87 88 void _BSP_Fatal_error(unsigned int v)89 {90 printk("%s PANIC ERROR %x\n",_RTEMS_version, v);91 __asm__ __volatile ("sc");92 }93 94 int BSP_FLASH_Disable_writes(95 uint32_t area96 )97 {98 unsigned char data;99 100 data = *GENERAL_REGISTER1;101 data |= DISABLE_USER_FLASH;102 *GENERAL_REGISTER1 = data;103 104 return RTEMS_SUCCESSFUL;105 }106 107 int BSP_FLASH_Enable_writes(108 uint32_t area /* IN */109 )110 {111 unsigned char data;112 113 data = *GENERAL_REGISTER1;114 data &= (~DISABLE_USER_FLASH);115 *GENERAL_REGISTER1 = data;116 117 return RTEMS_SUCCESSFUL;118 }119 120 void BSP_FLASH_set_page(121 uint8_t page122 )123 {124 unsigned char data;125 126 /* Set the flash page register. */127 data = *GENERAL_REGISTER2;128 data &= ~(BSP_FLASH_PAGE_MASK);129 data |= 0x80 | (page << BSP_FLASH_PAGE_SHIFT);130 *GENERAL_REGISTER2 = data;131 }132 133 /*134 * bsp_pretasking_hook135 *136 * BSP pretasking hook. Called just before drivers are initialized.137 */138 void bsp_pretasking_hook(void)139 {140 rsPMCQ1Init();141 }142 143 unsigned int EUMBBAR;144 145 static unsigned int get_eumbbar(void)146 {147 register int a, e;148 149 __asm__ volatile( "lis %0,0xfec0; ori %0,%0,0x0000": "=r" (a) );150 __asm__ volatile("sync");151 152 __asm__ volatile("lis %0,0x8000; ori %0,%0,0x0078": "=r"(e) );153 __asm__ volatile("stwbrx %0,0x0,%1": "=r"(e): "r"(a));154 __asm__ volatile("sync");155 156 __asm__ volatile("lis %0,0xfee0; ori %0,%0,0x0000": "=r" (a) );157 __asm__ volatile("sync");158 159 __asm__ volatile("lwbrx %0,0x0,%1": "=r" (e): "r" (a));160 __asm__ volatile("isync");161 return e;162 }163 164 static void Read_ep1a_config_registers( ppc_cpu_id_t myCpu ) {165 unsigned char value;166 167 /*168 * Print out the board and revision.169 */170 171 printk("Board: ");172 printk( get_ppc_cpu_type_name(myCpu) );173 174 value = *BOARD_REVISION_REGISTER2 & HARDWARE_ID_MASK;175 if ( value == HARDWARE_ID_PPC5_EP1A )176 printk(" EP1A ");177 else if ( value == HARDWARE_ID_EP1B )178 printk(" EP1B ");179 else180 printk(" Unknown ");181 182 value = *BOARD_REVISION_REGISTER2&0x1;183 printk("Board ID %08x", value);184 if(value == 0x0){185 VME_Slot1 = TRUE;186 printk("VME Slot 1\n");187 }188 else{189 VME_Slot1 = FALSE;190 printk("\n");191 }192 193 printk("Revision: ");194 value = *BOARD_REVISION_REGISTER1;195 printk("%d%c\n\n", value>>4, 'A'+(value&BUILD_REVISION_MASK) );196 197 /*198 * Get the CPU, XXX frequency199 */200 value = *EQUIPMENT_PRESENT_REGISTER2 & PLL_CFG_MASK;201 switch( value ) {202 case MHZ_33_66_200: /* PCI, MEM, & CPU Frequency */203 BSP_processor_frequency = 200000000;204 BSP_bus_frequency = 33000000;205 break;206 case MHZ_33_100_200: /* PCI, MEM, & CPU Frequency */207 BSP_processor_frequency = 200000000;208 BSP_bus_frequency = 33000000;209 break;210 case MHZ_33_66_266: /* PCI, MEM, & CPU Frequency */211 BSP_processor_frequency = 266000000;212 BSP_bus_frequency = 33000000;213 break;214 case MHZ_33_66_333: /* PCI, MEM, & CPU Frequency */215 BSP_processor_frequency = 333000000;216 BSP_bus_frequency = 33000000;217 break;218 case MHZ_33_100_333: /* PCI, MEM, & CPU Frequency */219 BSP_processor_frequency = 333000000;220 BSP_bus_frequency = 33000000;221 break;222 case MHZ_33_100_350: /* PCI, MEM, & CPU Frequency */223 BSP_processor_frequency = 350000000;224 BSP_bus_frequency = 33000000;225 break;226 default:227 printk("ERROR: Unknown Processor frequency 0x%02x please fill in bspstart.c\n",value);228 BSP_processor_frequency = 350000000;229 BSP_bus_frequency = 33000000;230 break;231 }232 }233 234 /*235 * bsp_start236 *237 * This routine does the bulk of the system initialization.238 */239 void bsp_start( void )240 {241 uintptr_t intrStackStart;242 uintptr_t intrStackSize;243 ppc_cpu_id_t myCpu;244 Triv121PgTbl pt=0; /* R = e; */245 246 /*247 * Get CPU identification dynamically. Note that the get_ppc_cpu_type()248 * function store the result in global variables so that it can be used249 * latter...250 */251 BSP_Increment_Light();252 myCpu = get_ppc_cpu_type();253 get_ppc_cpu_revision();254 255 EUMBBAR = get_eumbbar();256 printk("EUMBBAR 0x%08x\n", EUMBBAR );257 258 /*259 * Note this sets BSP_processor_frequency based upon register settings.260 * It must be done prior to setting up hooks.261 */262 Read_ep1a_config_registers( myCpu );263 264 bsp_clicks_per_usec = BSP_processor_frequency/(BSP_time_base_divisor * 1000);265 rtems_counter_initialize_converter(266 BSP_processor_frequency / (BSP_time_base_divisor / 1000)267 );268 269 ShowBATS();270 #if 0 /* XXX - Add back in cache enable when we get this up and running!! */271 /*272 * enables L1 Cache. Note that the L1_caches_enables() codes checks for273 * relevant CPU type so that the reason why there is no use of myCpu...274 */275 L1_caches_enables();276 #endif277 278 /*279 * Initialize the interrupt related settings.280 */281 intrStackStart = (uintptr_t) __rtems_end;282 intrStackSize = rtems_configuration_get_interrupt_stack_size();283 284 /*285 * Initialize default raw exception hanlders.286 */287 ppc_exc_initialize(intrStackStart, intrStackSize);288 289 /*290 * Init MMU block address translation to enable hardware291 * access292 */293 setdbat(1, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE);294 setdbat(3, 0x90000000, 0x90000000, 0x10000000, IO_PAGE);295 296 297 #ifdef SHOW_MORE_INIT_SETTINGS298 printk("Going to start PCI buses scanning and initialization\n");299 #endif300 pci_initialize();301 302 #ifdef SHOW_MORE_INIT_SETTINGS303 printk("Number of PCI buses found is : %d\n", pci_bus_count());304 #endif305 #ifdef TEST_RAW_EXCEPTION_CODE306 printk("Testing exception handling Part 1\n");307 308 /*309 * Cause a software exception310 */311 __asm__ __volatile ("sc");312 313 /*314 * Check we can still catch exceptions and returned coorectly.315 */316 printk("Testing exception handling Part 2\n");317 __asm__ __volatile ("sc");318 #endif319 320 /*321 * Initalize RTEMS IRQ system322 */323 BSP_rtems_irq_mng_init(0);324 325 /* Activate the page table mappings only after326 * initializing interrupts because the irq_mng_init()327 * routine needs to modify the text328 */329 if (pt) {330 #ifdef SHOW_MORE_INIT_SETTINGS331 printk("Page table setup finished; will activate it NOW...\n");332 #endif333 BSP_pgtbl_activate(pt);334 }335 336 /*337 * Initialize VME bridge - needs working PCI338 * and IRQ subsystems...339 */340 #ifdef SHOW_MORE_INIT_SETTINGS341 printk("Going to initialize VME bridge\n");342 #endif343 /* VME initialization is in a separate file so apps which don't use344 * VME or want a different configuration may link against a customized345 * routine.346 */347 BSP_vme_config();348 349 #ifdef SHOW_MORE_INIT_SETTINGS350 ShowBATS();351 printk("Exit from bspstart\n");352 #endif353 } -
deleted file c/src/lib/libbsp/powerpc/ep1a/startup/linkcmds
diff --git a/c/src/lib/libbsp/powerpc/ep1a/startup/linkcmds b/c/src/lib/libbsp/powerpc/ep1a/startup/linkcmds deleted file mode 100644 index 69644e3..0000000
+ - 1 OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc",2 "elf32-powerpc")3 4 OUTPUT_ARCH(powerpc)5 ENTRY(_start)6 7 /*8 * Number of Decrementer countdowns per millisecond9 *10 * Calculated by: (66.67 Mhz * 1000) / 4 cycles per click11 */12 13 SECTIONS14 {15 .vectors 0x00100 :16 {17 *(.vectors)18 }19 20 /* Read-only sections, merged into text segment: */21 /* SDS ROM worked at 0x30000 */22 . = 0x30000;23 .interp : { *(.interp) }24 .hash : { *(.hash) }25 .dynsym : { *(.dynsym) }26 .dynstr : { *(.dynstr) }27 .rela.text : { *(.rela.text) }28 .rela.data : { *(.rela.data) }29 .rela.rodata : { *(.rela.rodata) }30 .rela.got : { *(.rela.got) }31 .rela.got1 : { *(.rela.got1) }32 .rela.got2 : { *(.rela.got2) }33 .rela.ctors : { *(.rela.ctors) }34 .rela.dtors : { *(.rela.dtors) }35 .rela.init : { *(.rela.init) }36 .rela.fini : { *(.rela.fini) }37 .rela.bss : { *(.rela.bss) }38 .rela.plt : { *(.rela.plt) }39 .rela.sdata : { *(.rela.sdata2) }40 .rela.sbss : { *(.rela.sbss2) }41 .rela.sdata2 : { *(.rela.sdata2) }42 .rela.sbss2 : { *(.rela.sbss2) }43 .plt : { *(.plt) }44 .text :45 {46 _start = .;47 *(.text*)48 /*49 * Special FreeBSD sysctl sections.50 */51 . = ALIGN (16);52 __start_set_sysctl_set = .;53 *(set_sysctl_*);54 __stop_set_sysctl_set = ABSOLUTE(.);55 *(set_domain_*);56 *(set_pseudo_*);57 58 *(.gnu.linkonce.t.*)59 *(.descriptors)60 /* .gnu.warning sections are handled specially by elf32.em. */61 *(.gnu.warning)62 } =063 .init : { _init = .; *(.init) }64 .fini : { _fini = .; *(.fini) }65 .rodata : { *(.rodata*) KEEP (*(SORT(.rtemsroset.*))) *(.gnu.linkonce.r*) }66 .rodata1 : { *(.rodata1) }67 .tdata : {68 _TLS_Data_begin = .;69 *(.tdata .tdata.* .gnu.linkonce.td.*)70 _TLS_Data_end = .;71 }72 .tbss : {73 _TLS_BSS_begin = .;74 *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)75 _TLS_BSS_end = .;76 }77 _TLS_Data_size = _TLS_Data_end - _TLS_Data_begin;78 _TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin;79 _TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin;80 _TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin;81 _TLS_Size = _TLS_BSS_end - _TLS_Data_begin;82 _TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));83 .eh_frame : { *(.eh_frame) }84 _etext = .;85 PROVIDE (etext = .);86 PROVIDE (__SDATA2_START__ = .);87 .sdata2 : { *(.sdata2) *(.gnu.linkonce.s2.*) }88 .sbss2 : { *(.sbss2) *(.gnu.linkonce.sb2.*) }89 PROVIDE (__SBSS2_START__ = .);90 .sbss2 : { *(.sbss2) }91 PROVIDE (__SBSS2_END__ = .);92 /* Adjust the address for the data segment. We want to adjust up to93 the same address within the page on the next page up. It would94 be more correct to do this:95 . = ALIGN(0x40000) + (ALIGN(8) & (0x40000 - 1));96 The current expression does not correctly handle the case of a97 text segment ending precisely at the end of a page; it causes the98 data segment to skip a page. The above expression does not have99 this problem, but it will currently (2/95) cause BFD to allocate100 a single segment, combining both text and data, for this case.101 This will prevent the text segment from being shared among102 multiple executions of the program; I think that is more103 important than losing a page of the virtual address space (note104 that no actual memory is lost; the page which is skipped can not105 be referenced). */106 . = ALIGN(8) + 0x40000;107 PROVIDE (sdata = .);108 .data :109 {110 PROVIDE(__DATA_START__ = ABSOLUTE(.) );111 *(.data)112 KEEP (*(SORT(.rtemsrwset.*)))113 *(.gnu.linkonce.d.*)114 CONSTRUCTORS115 }116 PROVIDE (__EXCEPT_START__ = .);117 .gcc_except_table : { *(.gcc_except_table*) }118 PROVIDE (__EXCEPT_END__ = .);119 120 .data1 : { *(.data1) }121 .got1 : { *(.got1) }122 .dynamic : { *(.dynamic) }123 /* Put .ctors and .dtors next to the .got2 section, so that the pointers124 get relocated with -mrelocatable. Also put in the .fixup pointers.125 The current compiler no longer needs this, but keep it around for 2.7.2 */126 PROVIDE (_GOT2_START_ = .);127 .got2 : { *(.got2) }128 PROVIDE (__GOT2_END__ = .);129 PROVIDE (__CTOR_LIST__ = .);130 .ctors : { *(.ctors) }131 PROVIDE (__CTOR_END__ = .);132 PROVIDE (__DTOR_LIST__ = .);133 .dtors : { *(.dtors) }134 PROVIDE (__DTOR_END__ = .);135 PROVIDE (_FIXUP_START_ = .);136 .fixup : { *(.fixup) }137 PROVIDE (_FIXUP_END_ = .);138 PROVIDE (__FIXUP_END__ = .);139 PROVIDE (_GOT2_END_ = .);140 PROVIDE (_GOT_START_ = .);141 s.got = .;142 .got : { *(.got) }143 .got.plt : { *(.got.plt) }144 PROVIDE (_GOT_END_ = .);145 PROVIDE (__GOT_END__ = .);146 /* We want the small data sections together, so single-instruction offsets147 can access them all, and initialized data all before uninitialized, so148 we can shorten the on-disk segment size. */149 PROVIDE (__SDATA_START__ = .);150 .sdata : { *(.sdata*) *(.gnu.linkonce.s.*) }151 _edata = .;152 PROVIDE (edata = .);153 PROVIDE (RAM_END = ADDR(.text) + 10M);154 . = ALIGN(8) + 0x1000;155 PROVIDE (__SBSS_START__ = .);156 .sbss :157 {158 PROVIDE (__sbss_start = .);159 *(.sbss* .sbss.* .gnu.linkonce.sb.*)160 *(.scommon)161 PROVIDE (__sbss_end = .);162 }163 PROVIDE (__SBSS_END__ = .);164 .bss :165 {166 PROVIDE (__bss_start = .);167 *(.dynbss)168 *(.bss .bss* .gnu.linkonce.b*)169 *(COMMON)170 PROVIDE (__bss_end = .);171 }172 . = ALIGN(8) + 0x8000;173 PROVIDE (__stack = .);174 _end = . ;175 __rtems_end = . ;176 PROVIDE (end = .);177 178 /* These are needed for ELF backends which have not yet been179 converted to the new style linker. */180 .stab 0 : { *(.stab) }181 .stabstr 0 : { *(.stabstr) }182 /* DWARF debug sections.183 Symbols in the DWARF debugging sections are relative to the beginning184 of the section so we begin them at 0. */185 /* DWARF 1 */186 .debug 0 : { *(.debug) }187 .line 0 : { *(.line) }188 /* GNU DWARF 1 extensions */189 .debug_srcinfo 0 : { *(.debug_srcinfo) }190 .debug_sfnames 0 : { *(.debug_sfnames) }191 /* DWARF 1.1 and DWARF 2 */192 .debug_aranges 0 : { *(.debug_aranges) }193 .debug_pubnames 0 : { *(.debug_pubnames) }194 /* DWARF 2 */195 .debug_info 0 : { *(.debug_info) }196 .debug_abbrev 0 : { *(.debug_abbrev) }197 .debug_line 0 : { *(.debug_line) }198 .debug_frame 0 : { *(.debug_frame) }199 .debug_str 0 : { *(.debug_str) }200 .debug_loc 0 : { *(.debug_loc) }201 .debug_macinfo 0 : { *(.debug_macinfo) }202 /* SGI/MIPS DWARF 2 extensions */203 .debug_weaknames 0 : { *(.debug_weaknames) }204 .debug_funcnames 0 : { *(.debug_funcnames) }205 .debug_typenames 0 : { *(.debug_typenames) }206 .debug_varnames 0 : { *(.debug_varnames) }207 /* These must appear regardless of . */208 } -
deleted file c/src/lib/libbsp/powerpc/ep1a/vme/VMEConfig.h
diff --git a/c/src/lib/libbsp/powerpc/ep1a/vme/VMEConfig.h b/c/src/lib/libbsp/powerpc/ep1a/vme/VMEConfig.h deleted file mode 100644 index 1a57610..0000000
+ - 1 #ifndef RTEMS_BSP_VME_CONFIG_H2 #define RTEMS_BSP_VME_CONFIG_H3 4 /* BSP specific address space configuration parameters */5 6 /*7 * Authorship8 * ----------9 * This software was created by10 * Till Straumann <strauman@slac.stanford.edu>, 2002,11 * Stanford Linear Accelerator Center, Stanford University.12 *13 * Acknowledgement of sponsorship14 * ------------------------------15 * This software was produced by16 * the Stanford Linear Accelerator Center, Stanford University,17 * under Contract DE-AC03-76SFO0515 with the Department of Energy.18 *19 * Government disclaimer of liability20 * ----------------------------------21 * Neither the United States nor the United States Department of Energy,22 * nor any of their employees, makes any warranty, express or implied, or23 * assumes any legal liability or responsibility for the accuracy,24 * completeness, or usefulness of any data, apparatus, product, or process25 * disclosed, or represents that its use would not infringe privately owned26 * rights.27 *28 * Stanford disclaimer of liability29 * --------------------------------30 * Stanford University makes no representations or warranties, express or31 * implied, nor assumes any liability for the use of this software.32 *33 * Stanford disclaimer of copyright34 * --------------------------------35 * Stanford University, owner of the copyright, hereby disclaims its36 * copyright and all other rights in this software. Hence, anyone may37 * freely use it for any purpose without restriction.38 *39 * Maintenance of notices40 * ----------------------41 * In the interest of clarity regarding the origin and status of this42 * SLAC software, this and all the preceding Stanford University notices43 * are to remain affixed to any copy or derivative of this software made44 * or distributed by the recipient and are to be affixed to any copy of45 * software made or distributed by the recipient that contains a copy or46 * derivative of this software.47 *48 * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 0349 */50 /*51 * The BSP maps VME address ranges into52 * one BAT.53 * NOTE: the BSP (startup/bspstart.c) uses54 * hardcoded window lengths that match this55 * layout:56 *57 * BSP_VME_BAT_IDX defines58 * which BAT to use for mapping the VME bus.59 * If this is undefined, no extra BAT will be60 * configured and VME has to share the available61 * PCI address space with PCI devices.62 */63 #undef BSP_VME_BAT_IDX64 65 #define _VME_A32_WIN0_ON_PCI 0x9000000066 #define _VME_A24_ON_PCI 0x9f00000067 #define _VME_A16_ON_PCI 0x9fff000068 69 /* start of the A32 window on the VME bus70 * TODO: this should perhaps be a configuration option71 */72 #define _VME_A32_WIN0_ON_VME 0x2000000073 74 /* if _VME_DRAM_OFFSET is defined, the BSP75 * will map our RAM onto the VME bus, starting76 * at _VME_DRAM_OFFSET77 */78 #undef _VME_DRAM_OFFSET79 #define _VME_DRAM_OFFSET 0xc000000080 #define _VME_DRAM_32_OFFSET1 0x2000000081 #define _VME_DRAM_32_OFFSET2 0x20b0000082 #define _VME_DRAM_24_OFFSET1 0x0000000083 #define _VME_DRAM_24_OFFSET2 0x0010000084 #define _VME_DRAM_16_OFFSET1 0x0000000085 #define _VME_DRAM_16_OFFSET2 0x0000800086 87 #define _VME_A24_SIZE 0x0010000088 #define _VME_A16_SIZE 0x0000800089 90 #undef _VME_CSR_ON_PCI91 92 /* Tell the interrupt manager that the universe driver93 * already called openpic_eoi() and that this step hence94 * must be omitted.95 */96 97 #define BSP_PCI_VME_DRIVER_DOES_EOI98 99 /* don't reference vmeUniverse0PciIrqLine directly here - leave it up to100 * bspstart() to set BSP_vme_bridge_irq. That way, we can generate variants101 * of the BSP with / without the universe driver...102 */103 extern int _BSP_vme_bridge_irq;104 105 extern int BSP_VMEInit(void);106 extern int BSP_VMEIrqMgrInstall(void);107 108 #define BSP_VME_UNIVERSE_INSTALL_IRQ_MGR(err) \109 do { \110 err = vmeUniverseInstallIrqMgr(0,5,1,6); \111 } while (0)112 113 #endif
