Ticket #215: libcpu_powerpc_io.diff

File libcpu_powerpc_io.diff, 6.3 KB (added by strauman, on 12/03/06 at 13:31:12)

libcpu_powerpc_io.diff

Line 
1This patch (against rtems-ss-20020301) addresses the following
2issues (powerpc):
3
4 - _IO_BASE, _ISA_MEM_BASE and PCI_DRAM_OFFSET
5   are no longer defined by libcpu (powerpc/shared/include/io.h)
6   but by the BSP (who is the only one to know the values)
7
8 - the affected BSP (shared/motorola) headers have been fixed
9   in a separate "libbsp/powerpc/shared" patch.
10
11 - the DEC 21140 driver (libchip/network/dec21140.c)
12   has been fixed to use PCI_DRAM_OFFSET instead of PREP_PCI_DRAM_OFFSET.
13   and PCI_MEM_BASE instead of PREP_ISA_MEM_BASE. PCI_MEM_BASE
14   is to be defined by the BSP who is using this driver.
15
16 - the DEC driver also has been fixed to use the newer
17   rtems_bsp_delay_in_bus_cycles() instead of the obsolete
18   delay_in_bus_cycles().
19
20Author: Till Straumann <strauman@slac.stanford.edu>, 4/2002
21
22Index: c/src/lib/libcpu/powerpc/shared/include/io.h
23===================================================================
24RCS file: /afs/slac/g/spear/cvsrep/rtems/src/c/src/lib/libcpu/powerpc/shared/include/io.h,v
25retrieving revision 1.1.1.1
26retrieving revision 1.5
27diff -c -r1.1.1.1 -r1.5
28*** c/src/lib/libcpu/powerpc/shared/include/io.h        2001/12/14 22:53:00     1.1.1.1
29--- c/src/lib/libcpu/powerpc/shared/include/io.h        2002/04/18 01:52:21     1.5
30***************
31*** 23,34 ****
32  #define PREP_ISA_MEM_BASE     0xc0000000
33  #define PREP_PCI_DRAM_OFFSET  0x80000000
34 
35! #define _IO_BASE      PREP_ISA_IO_BASE
36! #define _ISA_MEM_BASE PREP_ISA_MEM_BASE
37! #define PCI_DRAM_OFFSET       PREP_PCI_DRAM_OFFSET
38 
39  #ifndef ASM
40 
41  #define inb(port)             in_8((unsigned char *)((port)+_IO_BASE))
42  #define outb(val, port)               out_8((unsigned char *)((port)+_IO_BASE), (val))
43  #define inw(port)             in_le16((unsigned short *)((port)+_IO_BASE))
44--- 23,44 ----
45  #define PREP_ISA_MEM_BASE     0xc0000000
46  #define PREP_PCI_DRAM_OFFSET  0x80000000
47 
48! #define CHRP_ISA_IO_BASE      0xfe000000
49! #define CHRP_ISA_MEM_BASE     0xfd000000
50! #define CHRP_PCI_DRAM_OFFSET  0x00000000
51 
52+ /* _IO_BASE, _ISA_MEM_BASE, PCI_DRAM_OFFSET are now defined by bsp.h */
53+
54  #ifndef ASM
55 
56+ #include <bsp.h>              /* for _IO_BASE & friends */
57+
58+ /* NOTE: The use of these macros is DISCOURAGED.
59+  *       you should consider e.g. using in_xxx / out_xxx
60+  *       with a device specific base address that is
61+  *       defined by the BSP. This makes drivers easier
62+  *       to port.
63+  */
64  #define inb(port)             in_8((unsigned char *)((port)+_IO_BASE))
65  #define outb(val, port)               out_8((unsigned char *)((port)+_IO_BASE), (val))
66  #define inw(port)             in_le16((unsigned short *)((port)+_IO_BASE))
67Index: c/src/libchip/network/dec21140.c
68===================================================================
69RCS file: /afs/slac/g/spear/cvsrep/rtems/src/c/src/libchip/network/dec21140.c,v
70retrieving revision 1.1.1.1
71retrieving revision 1.5
72diff -c -r1.1.1.1 -r1.5
73*** c/src/libchip/network/dec21140.c    2001/12/14 22:53:12     1.1.1.1
74--- c/src/libchip/network/dec21140.c    2002/04/21 05:12:31     1.5
75***************
76*** 187,200 ****
77  #define START_TRANSMIT_EVENT  RTEMS_EVENT_2
78 
79  #if defined(__PPC)
80! #define phys_to_bus(address) ((unsigned int)((address)) + PREP_PCI_DRAM_OFFSET)
81! #define bus_to_phys(address) ((unsigned int)((address)) - PREP_PCI_DRAM_OFFSET)
82  #define CPU_CACHE_ALIGNMENT_FOR_BUFFER PPC_CACHE_ALIGNMENT
83  #else
84  extern void Wait_X_ms( unsigned int timeToWait );
85  #define phys_to_bus(address) ((unsigned int) ((address)))
86  #define bus_to_phys(address) ((unsigned int) ((address)))
87! #define delay_in_bus_cycles(cycle) Wait_X_ms( cycle/100 )
88  #define CPU_CACHE_ALIGNMENT_FOR_BUFFER PG_SIZE
89 
90  inline void st_le32(volatile unsigned32 *addr, unsigned32 value)
91--- 187,200 ----
92  #define START_TRANSMIT_EVENT  RTEMS_EVENT_2
93 
94  #if defined(__PPC)
95! #define phys_to_bus(address) ((unsigned int)((address)) + PCI_DRAM_OFFSET)
96! #define bus_to_phys(address) ((unsigned int)((address)) - PCI_DRAM_OFFSET)
97  #define CPU_CACHE_ALIGNMENT_FOR_BUFFER PPC_CACHE_ALIGNMENT
98  #else
99  extern void Wait_X_ms( unsigned int timeToWait );
100  #define phys_to_bus(address) ((unsigned int) ((address)))
101  #define bus_to_phys(address) ((unsigned int) ((address)))
102! #define rtems_bsp_delay_in_bus_cycles(cycle) Wait_X_ms( cycle/100 )
103  #define CPU_CACHE_ALIGNMENT_FOR_BUFFER PG_SIZE
104 
105  inline void st_le32(volatile unsigned32 *addr, unsigned32 value)
106***************
107*** 333,352 ****
108        for (i = 10; i >= 0; i--) {
109                short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
110                st_le32(ioaddr, EE_ENB | dataval);
111!               delay_in_bus_cycles(200);
112                st_le32(ioaddr, EE_ENB | dataval | EE_SHIFT_CLK);
113!               delay_in_bus_cycles(200);
114                st_le32(ioaddr, EE_ENB | dataval); /* Finish EEPROM a clock tick. */
115!               delay_in_bus_cycles(200);
116        }
117        st_le32(ioaddr, EE_ENB);
118       
119        for (i = 16; i > 0; i--) {
120                st_le32(ioaddr, EE_ENB | EE_SHIFT_CLK);
121!               delay_in_bus_cycles(200);
122                retval = (retval << 1) | ((ld_le32(ioaddr) & EE_DATA_READ) ? 1 : 0);
123                st_le32(ioaddr, EE_ENB);
124!               delay_in_bus_cycles(200);
125        }
126 
127        /* Terminate the EEPROM access. */
128--- 333,352 ----
129        for (i = 10; i >= 0; i--) {
130                short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
131                st_le32(ioaddr, EE_ENB | dataval);
132!               rtems_bsp_delay_in_bus_cycles(200);
133                st_le32(ioaddr, EE_ENB | dataval | EE_SHIFT_CLK);
134!               rtems_bsp_delay_in_bus_cycles(200);
135                st_le32(ioaddr, EE_ENB | dataval); /* Finish EEPROM a clock tick. */
136!               rtems_bsp_delay_in_bus_cycles(200);
137        }
138        st_le32(ioaddr, EE_ENB);
139       
140        for (i = 16; i > 0; i--) {
141                st_le32(ioaddr, EE_ENB | EE_SHIFT_CLK);
142!               rtems_bsp_delay_in_bus_cycles(200);
143                retval = (retval << 1) | ((ld_le32(ioaddr) & EE_DATA_READ) ? 1 : 0);
144                st_le32(ioaddr, EE_ENB);
145!               rtems_bsp_delay_in_bus_cycles(200);
146        }
147 
148        /* Terminate the EEPROM access. */
149***************
150*** 375,381 ****
151     */
152    st_le32( (tbase+memCSR6), CSR6_INIT); 
153    st_le32( (tbase+memCSR0), RESET_CHIP); 
154!   delay_in_bus_cycles(200);
155 
156    /*
157     * Init CSR0
158--- 375,381 ----
159     */
160    st_le32( (tbase+memCSR6), CSR6_INIT); 
161    st_le32( (tbase+memCSR0), RESET_CHIP); 
162!   rtems_bsp_delay_in_bus_cycles(200);
163 
164    /*
165     * Init CSR0
166***************
167*** 895,901 ****
168 
169 
170        tmp = (unsigned int)(lvalue & (unsigned int)(~MEM_MASK))
171!         + (unsigned int)PREP_ISA_MEM_BASE;
172        sc->base = (unsigned int *)(tmp);
173 
174        (void)pci_read_config_byte(0,
175--- 895,901 ----
176 
177 
178        tmp = (unsigned int)(lvalue & (unsigned int)(~MEM_MASK))
179!         + (unsigned int)PCI_MEM_BASE;
180        sc->base = (unsigned int *)(tmp);
181 
182        (void)pci_read_config_byte(0,