Ticket #2020: 0001-Updates-for-ppc440.patch

File 0001-Updates-for-ppc440.patch, 29.4 KB (added by Ric Claus, on 02/17/12 at 21:58:27)

PPC 440 support modifications

  • c/src/lib/libbsp/powerpc/acinclude.m4 

    From 8018b975d9afd97d7ba81c0a43b42ba5539f197a Mon Sep 17 00:00:00 2001
From: Ric Claus <claus@SLAC.Stanford.edu>
Date: Fri, 17 Feb 2012 13:25:54 -0800
Subject: [PATCH 1/7] Updates for ppc440

---
 c/src/lib/libbsp/powerpc/acinclude.m4              |    4 +
 c/src/lib/libbsp/shared/bootcard.c                 |    4 +-
 c/src/lib/libcpu/powerpc/README                    |    3 +-
 c/src/lib/libcpu/powerpc/configure.ac              |    9 +-
 .../new-exceptions/bspsupport/ppc_exc_categories.c |   35 +++++++--
 .../new-exceptions/bspsupport/ppc_exc_initialize.c |   38 ++++++++-
 .../powerpc/new-exceptions/bspsupport/vectors.h    |   10 ++-
 c/src/lib/libcpu/powerpc/ppc403/clock/clock.c      |   86 +++++++++++++++++---
 c/src/lib/libcpu/powerpc/rtems/powerpc/debugmod.h  |    4 +-
 c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h   |   15 +++-
 c/src/lib/libcpu/powerpc/shared/include/cpuIdent.c |   12 ++-
 c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h |   18 ++++-
 cpukit/score/cpu/powerpc/rtems/asm.h               |   79 ++++++++++++++++++-
 13 files changed, 276 insertions(+), 41 deletions(-)

diff --git a/c/src/lib/libbsp/powerpc/acinclude.m4 b/c/src/lib/libbsp/powerpc/acinclude.m4
index 871d345..52e9c3f 100644
    a b AC_DEFUN([RTEMS_CHECK_BSPDIR], 
    3636    AC_CONFIG_SUBDIRS([tqm8xx]);;
    3737  virtex )
    3838    AC_CONFIG_SUBDIRS([virtex]);;
     39  virtex4 )
     40    AC_CONFIG_SUBDIRS([virtex4]);;
     41  virtex5 )
     42    AC_CONFIG_SUBDIRS([virtex5]);;
    3943  *)
    4044    AC_MSG_ERROR([Invalid BSP]);;
    4145  esac

  • c/src/lib/libbsp/shared/bootcard.c 

    diff --git a/c/src/lib/libbsp/shared/bootcard.c b/c/src/lib/libbsp/shared/bootcard.c
index 939a206..9b7a781 100644
    a b  
    4646 *  found in the file LICENSE in this distribution or at
    4747 *  http://www.rtems.com/license/LICENSE.
    4848 *
    49  *  $Id$
     49 *  $Id:$
    5050 */
    5151
    5252#include <rtems.h>
    … … int boot_card( 
    214214  );
    215215
    216216  /*
    217    *  All BSP to do any required initialization now that RTEMS
     217   *  Call BSP to do any required initialization now that RTEMS
    218218   *  data structures are initialized.  In older BSPs or those
    219219   *  which do not use the shared framework, this is the typical
    220220   *  time when the C Library is initialized so malloc()

  • c/src/lib/libcpu/powerpc/README 

    diff --git a/c/src/lib/libcpu/powerpc/README b/c/src/lib/libcpu/powerpc/README
index 57ac52a..8800ddf 100644
    a b  
    11#
    2 #  $Id$
     2#  $Id:$
    33#
    44
    55This hierarchy contains support routines for some of
    … … family members using the new exception processing model: 
    2222  + mpc860
    2323  + mpc8260
    2424  + ppc405
     25  + ppc440
    2526
    2627Note that because of similarities in various family members,
    2728the mpc823 should be able to use the mpc821 code and the

  • c/src/lib/libcpu/powerpc/configure.ac 

    diff --git a/c/src/lib/libcpu/powerpc/configure.ac b/c/src/lib/libcpu/powerpc/configure.ac
index d799bd2..a64d0b1 100644
    a b  
    11# Process this file with autoconf to produce a configure script.
    22#
    3 # $Id$
     3# $Id:$
    44
    55##
    66#
    … … AM_CONDITIONAL(shared, \ 
    4141|| test "$RTEMS_CPU_MODEL" = "ppc603e" \
    4242|| test "$RTEMS_CPU_MODEL" = "ppc403" \
    4343|| test "$RTEMS_CPU_MODEL" = "ppc405" \
     44|| test "$RTEMS_CPU_MODEL" = "ppc440" \
    4445|| test "$RTEMS_CPU_MODEL" = "mpc604" \
    4546|| test "$RTEMS_CPU_MODEL" = "mpc6xx" \
    4647|| test "$RTEMS_CPU_MODEL" = "mpc8xx" \
    … … AM_CONDITIONAL(mpc8xx, test "$RTEMS_CPU_MODEL" = "mpc8xx" \ 
    7273AM_CONDITIONAL(mpc8260, test "$RTEMS_CPU_MODEL" = "mpc8260")
    7374AM_CONDITIONAL(mpc83xx, test "$RTEMS_CPU_MODEL" = "mpc83xx")
    7475
    75 # the ppc405 shares files with the ppc403
    76 AM_CONDITIONAL(ppc403,[test "$RTEMS_CPU_MODEL" = "ppc403" \
    77 || test "$RTEMS_CPU_MODEL" = "ppc405"])
     76# the ppc405 and ppc440 share files with the ppc403
     77AM_CONDITIONAL(ppc403, test "$RTEMS_CPU_MODEL" = "ppc403")
    7878AM_CONDITIONAL(ppc405, test "$RTEMS_CPU_MODEL" = "ppc405")
     79AM_CONDITIONAL(ppc440, test "$RTEMS_CPU_MODEL" = "ppc440")
    7980
    8081AM_CONDITIONAL(e500, test "$RTEMS_CPU_MODEL" = "e500")
    8182

  • c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_categories.c 

    diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_categories.c b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_categories.c
index d71ba7b..5ebcb5e 100644
    a b  
    2525 * found in found in the file LICENSE in this distribution or at
    2626 * http://www.rtems.com/license/LICENSE.
    2727 *
    28  * $Id$
     28 * $Id:$
    2929 */
    3030
    3131#include <bsp/vectors.h>
    … … static const ppc_exc_categories ppc_405_category_table = { 
    5656  [ASM_PROG_VECTOR] = PPC_EXC_CLASSIC,
    5757  [ASM_FLOAT_VECTOR] = PPC_EXC_CLASSIC,
    5858
    59   [ASM_PPC405_APU_UNAVAIL_VECTOR] = PPC_EXC_CLASSIC,
    60 
    6159  [ASM_SYS_VECTOR] = PPC_EXC_CLASSIC,
    6260
     61  [ASM_PPC405_APU_UNAVAIL_VECTOR] = PPC_EXC_CLASSIC,
     62
    6363  [ASM_BOOKE_DEC_VECTOR] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
    6464  [ASM_BOOKE_FIT_VECTOR] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
    6565  [ASM_BOOKE_WDOG_VECTOR] = PPC_EXC_405_CRITICAL | PPC_EXC_ASYNC,
    … … static const ppc_exc_categories ppc_405_category_table = { 
    6868  [ASM_TRACE_VECTOR] = PPC_EXC_405_CRITICAL,
    6969};
    7070
     71static const ppc_exc_categories ppc_booke_category_table = {
     72  [ASM_BOOKE_CRIT_VECTOR] = PPC_EXC_BOOKE_CRITICAL | PPC_EXC_ASYNC,
     73  [ASM_MACH_VECTOR] = PPC_EXC_E500_MACHCHK,
     74  [ASM_PROT_VECTOR] = PPC_EXC_CLASSIC,
     75  [ASM_ISI_VECTOR] = PPC_EXC_CLASSIC,
     76  [ASM_EXT_VECTOR] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
     77  [ASM_ALIGN_VECTOR] = PPC_EXC_CLASSIC,
     78  [ASM_PROG_VECTOR] = PPC_EXC_CLASSIC,
     79  [ASM_FLOAT_VECTOR] = PPC_EXC_CLASSIC,
     80  [ASM_SYS_VECTOR] = PPC_EXC_CLASSIC,
     81  [ASM_BOOKE_APU_VECTOR] = PPC_EXC_CLASSIC,
     82  [ASM_BOOKE_DEC_VECTOR] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
     83  [ASM_BOOKE_FIT_VECTOR] = PPC_EXC_CLASSIC | PPC_EXC_ASYNC,
     84  [ASM_BOOKE_WDOG_VECTOR] = PPC_EXC_BOOKE_CRITICAL | PPC_EXC_ASYNC,
     85  [ASM_BOOKE_DTLBMISS_VECTOR] = PPC_EXC_CLASSIC,
     86  [ASM_BOOKE_ITLBMISS_VECTOR] = PPC_EXC_CLASSIC,
     87  [ASM_BOOKE_DEBUG_VECTOR] = PPC_EXC_BOOKE_CRITICAL,
     88};
     89
    7190static const ppc_exc_categories mpc_5xx_category_table = {
    7291  [ASM_RESET_VECTOR] = PPC_EXC_CLASSIC,
    7392  [ASM_MACH_VECTOR] = PPC_EXC_CLASSIC,
    … … static const ppc_exc_categories e200_category_table = { 
    166185  [ASM_BOOKE_DTLBMISS_VECTOR] = PPC_EXC_CLASSIC,
    167186
    168187  /* FIXME: Depending on HDI0 [DAPUEN] this is a critical or debug exception */
    169   [ASM_TRACE_VECTOR] = PPC_EXC_CLASSIC | PPC_EXC_BOOKE_CRITICAL,
     188  [ASM_BOOKE_DEBUG_VECTOR] = PPC_EXC_BOOKE_CRITICAL,
    170189
    171   [ASM_E200_SPE_UNAVAILABLE_VECTOR] = PPC_EXC_CLASSIC,
    172   [ASM_E200_SPE_DATA_VECTOR] = PPC_EXC_CLASSIC,
    173   [ASM_E200_SPE_ROUND_VECTOR] = PPC_EXC_CLASSIC,
     190  [ASM_E500_SPE_UNAVAILABLE_VECTOR] = PPC_EXC_CLASSIC,
     191  [ASM_E500_EMB_FP_DATA_VECTOR] = PPC_EXC_CLASSIC,
     192  [ASM_E500_EMB_FP_ROUND_VECTOR] = PPC_EXC_CLASSIC
    174193};
    175194
    176195static const ppc_exc_categories e300_category_table = {
    … … const ppc_exc_categories *ppc_exc_categories_for_cpu(ppc_cpu_id_t cpu) 
    287306    case PPC_405GP:
    288307    case PPC_405EX:
    289308      return &ppc_405_category_table;
     309    case PPC_440:
     310      return &ppc_booke_category_table;
    290311    default:
    291312      break;
    292313  }

  • c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c 

    diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_initialize.c
index 93f0fb5..7ddcb20 100644
    a b  
    2121 * found in found in the file LICENSE in this distribution or at
    2222 * http://www.rtems.com/license/LICENSE.
    2323 *
    24  * $Id$
     24 * $Id:$
    2525 */
    2626
    2727#include <rtems.h>
    … … uint32_t ppc_exc_cache_wb_check = 1; 
    3333#define MTIVPR(prefix) asm volatile ("mtivpr %0" : : "r" (prefix))
    3434#define MTIVOR(x, vec) asm volatile ("mtivor"#x" %0" : : "r" (vec))
    3535
     36static void ppc_exc_initialize_booke(void)
     37{
     38  /* Interrupt vector prefix register */
     39  MTIVPR(ppc_exc_vector_base);
     40
     41  /* Interrupt vector offset registers */
     42  MTIVOR(0,  ppc_exc_vector_address(ASM_BOOKE_CRIT_VECTOR));
     43  MTIVOR(1,  ppc_exc_vector_address(ASM_MACH_VECTOR));
     44  MTIVOR(2,  ppc_exc_vector_address(ASM_PROT_VECTOR));
     45  MTIVOR(3,  ppc_exc_vector_address(ASM_ISI_VECTOR));
     46  MTIVOR(4,  ppc_exc_vector_address(ASM_EXT_VECTOR));
     47  MTIVOR(5,  ppc_exc_vector_address(ASM_ALIGN_VECTOR));
     48  MTIVOR(6,  ppc_exc_vector_address(ASM_PROG_VECTOR));
     49  MTIVOR(7,  ppc_exc_vector_address(ASM_FLOAT_VECTOR));
     50  MTIVOR(8,  ppc_exc_vector_address(ASM_SYS_VECTOR));
     51  MTIVOR(9,  ppc_exc_vector_address(ASM_BOOKE_APU_VECTOR));
     52  MTIVOR(10, ppc_exc_vector_address(ASM_BOOKE_DEC_VECTOR));
     53  MTIVOR(11, ppc_exc_vector_address(ASM_BOOKE_FIT_VECTOR));
     54  MTIVOR(12, ppc_exc_vector_address(ASM_BOOKE_WDOG_VECTOR));
     55  MTIVOR(13, ppc_exc_vector_address(ASM_BOOKE_DTLBMISS_VECTOR));
     56  MTIVOR(14, ppc_exc_vector_address(ASM_BOOKE_ITLBMISS_VECTOR));
     57  MTIVOR(15, ppc_exc_vector_address(ASM_BOOKE_DEBUG_VECTOR));
     58  MTIVOR(32, ppc_exc_vector_address(ASM_E500_SPE_UNAVAILABLE_VECTOR));
     59  MTIVOR(33, ppc_exc_vector_address(ASM_E500_EMB_FP_DATA_VECTOR));
     60  MTIVOR(34, ppc_exc_vector_address(ASM_E500_EMB_FP_ROUND_VECTOR));
     61  MTIVOR(35, ppc_exc_vector_address(ASM_E500_PERFMON_VECTOR));
     62}
     63
    3664static void ppc_exc_initialize_e500(void)
    3765{
    3866  /* Interupt vector prefix register */
    … … rtems_status_code ppc_exc_initialize( 
    141169  /* Need vector unit enabled to save/restore altivec context */
    142170  ppc_exc_msr_bits |= MSR_VE;
    143171#endif
    144  
    145   if (ppc_cpu_is(PPC_e200z1) || 
     172
     173  if (ppc_cpu_is(PPC_e200z1) ||
    146174      ppc_cpu_is(PPC_e200z6)) {
    147175    ppc_exc_initialize_e200();
    148   } else if (ppc_cpu_is_bookE() == PPC_BOOKE_STD || ppc_cpu_is_bookE() == PPC_BOOKE_E500) {
     176  } else if (ppc_cpu_is_bookE() == PPC_BOOKE_STD) {
     177    ppc_exc_initialize_booke();
     178  } else if ( ppc_cpu_is_bookE() == PPC_BOOKE_E500) {
    149179    ppc_exc_initialize_e500();
    150180  }
    151181

  • c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h 

    diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors.h
index e34255e..ef0440a 100644
    a b  
    2929 * found in found in the file LICENSE in this distribution or at
    3030 * http://www.rtems.com/license/LICENSE.
    3131 *
    32  * $Id$
     32 * $Id:$
    3333 */
    3434
    3535/* DO NOT INTRODUCE #ifdef <cpu_flavor> in this file */
    … … extern "C" { 
    7474#define ASM_BOOKE_DTLBMISS_VECTOR            0x12
    7575#define ASM_BOOKE_FIT_VECTOR                 0x13
    7676#define ASM_BOOKE_WDOG_VECTOR                0x14
     77#define ASM_BOOKE_APU_VECTOR                 0x18
     78#define ASM_BOOKE_DEBUG_VECTOR               ASM_TRACE_VECTOR
    7779
    7880#define ASM_PPC405_APU_UNAVAIL_VECTOR        ASM_60X_VEC_ASSIST_VECTOR
    7981
    … … extern "C" { 
    121123#define ASM_E300_ADDR_VECTOR                 0x13
    122124#define ASM_E300_SYSMGMT_VECTOR              0x14
    123125
     126/* e500 */
     127#define ASM_E500_SPE_UNAVAILABLE_VECTOR      ASM_60X_VEC_VECTOR
     128#define ASM_E500_EMB_FP_DATA_VECTOR          0x19
     129#define ASM_E500_EMB_FP_ROUND_VECTOR         0x1A
     130#define ASM_E500_PERFMON_VECTOR              ASM_60X_PERFMON_VECTOR
     131
    124132/*
    125133 * If you change that number make sure to adjust the wrapper code in ppc_exc.S
    126134 * and that ppc_exc_handler_table will be correctly initialized.

  • c/src/lib/libcpu/powerpc/ppc403/clock/clock.c 

    diff --git a/c/src/lib/libcpu/powerpc/ppc403/clock/clock.c b/c/src/lib/libcpu/powerpc/ppc403/clock/clock.c
index 513049e..30f4d6d 100644
    a b  
    3434 *
    3535 *  Modifications for PPC405GP by Dennis Ehlin
    3636 *
    37  *  $Id$
     37 *  $Id:$
    3838 */
    3939
    4040#include <rtems.h>
    … … static inline uint32_t get_itimer(void) 
    7272{
    7373    register uint32_t   rc;
    7474
    75 #ifndef ppc405 /* this is a ppc403 */
     75#ifdef ppc403 /* this is a ppc403 */
    7676    asm volatile ("mfspr %0, 0x3dd" : "=r" ((rc))); /* TBLO */
    77 #else /* ppc405 */
    78     asm volatile ("mfspr %0, 0x10c" : "=r" ((rc))); /* 405GP TBL */
    79 #endif /* ppc405 */
     77#else /* ppc403 */
     78    asm volatile ("mfspr %0, 0x10c" : "=r" ((rc))); /* 405, 440 TBL */
     79#endif /* ppc403 */
    8080
    8181    return rc;
    8282}
    … … void Clock_isr(void* handle) 
    135135        /* XXX: count these! this should never happen :-) */
    136136      }
    137137
     138#ifndef ppc440
    138139      asm volatile ("mtspr 0x3db, %0" :: "r"
    139140                         (clicks_til_next_interrupt)); /* PIT */
     141#else /* Book E */
     142      asm volatile ("mtspr 0x016, %0" :: "r"
     143                         (clicks_til_next_interrupt)); /* Decrementer */
     144#endif
    140145  }
    141146
     147    /* Clear the Programmable / Decrementer (Book E), Interrupt Status */
     148#ifndef ppc440
    142149    asm volatile ( "mtspr 0x3d8, %0" :: "r" (0x08000000)); /* TSR */
     150#else /* Book E */
     151    asm volatile ( "mtspr 0x150, %0" :: "r" (0x08000000)); /* TSR */
     152#endif
    143153
    144154    Clock_driver_ticks++;
    145155
    … … int ClockIsOn(const rtems_irq_connect_data* unused) 
    160170{
    161171    register uint32_t   tcr;
    162172
     173#ifndef ppc440
    163174    asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
     175#else /* Book E */
     176    asm volatile ("mfspr %0, 0x154" : "=r" ((tcr))); /* TCR */
     177#endif
    164178
    165179    return (tcr & 0x04000000) != 0;
    166180}
    … … void ClockOff( 
    171185{
    172186    register uint32_t   tcr;
    173187
     188    /* RiC - Wed Feb  9 11:53:04 2011
     189     * This appears to be an unprotected read-modify-write.
     190     * Is that intentional and okay?
     191     */
     192
     193#ifndef ppc440
    174194    asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
     195#else /* Book E */
     196    asm volatile ("mfspr %0, 0x154" : "=r" ((tcr))); /* TCR */
     197#endif
    175198
    176199    tcr &= ~ 0x04400000;
    177200
     201#ifndef ppc440
    178202    asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
     203#else /* Book E */
     204    asm volatile ("mtspr 0x154, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
     205#endif
    179206}
    180207
    181208void ClockOn(
    … … void ClockOn( 
    190217
    191218    Clock_driver_ticks = 0;
    192219
    193 #ifndef ppc405 /* this is a ppc403 */
     220#ifdef ppc403 /* this is a ppc403 */
    194221    asm volatile ("mfdcr %0, 0xa0" : "=r" (iocr)); /* IOCR */
    195222    if (bsp_timer_internal_clock) {
    196223        iocr &= ~4; /* timer clocked from system clock */
    … … void ClockOn( 
    214241    else if ((pvr & 0xff00) == 0x0100) /* 403GB */
    215242      auto_restart = true;
    216243
    217 #else /* ppc405 */
     244#else /* ppc403 */
     245# ifdef ppc405 /* ppc405 */
    218246    asm volatile ("mfdcr %0, 0x0b2" : "=r" (iocr));  /*405GP CPC0_CR1 */
    219247    if (bsp_timer_internal_clock) {
    220         iocr &=~0x800000        ;/* timer clocked from system clock CETE*/
     248      iocr &=~0x800000;               /* timer clocked from system clock CETE*/
    221249    }
    222250    else {
    223251        iocr |= 0x800000; /* select external timer clock CETE*/
    224252    }
    225253    asm volatile ("mtdcr 0x0b2, %0" : "=r" (iocr) : "0" (iocr)); /* 405GP CPC0_CR1 */
    226254
     255#else /* ppc405 */
     256    asm volatile ("mfspr %0, 0x378" : "=r" (iocr));  /* 440 CCR1 */
     257    if (bsp_timer_internal_clock) {
     258      iocr &= ~0x00000100;           /* timer clocked from system clock CETE */
     259    }
     260    else {
     261      iocr |=  0x00000100;           /* select external timer clock CETE */
     262    }
     263    asm volatile ("mtspr 0x378, %0" : "=r" (iocr) : "0" (iocr)); /* 440 CCR1 */
     264#endif /* ppc405 */
     265
    227266     /*
    228267      * Enable auto restart
    229268      */
    230269
    231     auto_restart=true;
     270    auto_restart = true;
    232271
    233 #endif /* ppc405 */
     272#endif /* ppc403 */
    234273    pit_value = rtems_configuration_get_microseconds_per_tick() *
    235274      bsp_clicks_per_usec;
    236275
    … … void ClockOn( 
    238277      * Set PIT value
    239278      */
    240279
     280#ifndef ppc440
    241281    asm volatile ("mtspr 0x3db, %0" : : "r" (pit_value)); /* PIT */
     282#else /* Book E */
     283    asm volatile ("mtspr 0x016, %0" : : "r" (pit_value)); /* Decrementer */
     284#endif
    242285
    243286     /*
    244287      * Set timer to autoreload, bit TCR->ARE = 1  0x0400000
    … … void ClockOn( 
    246289      */
    247290    tick_time = get_itimer() + pit_value;
    248291
     292#ifndef ppc440
    249293    asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
    250294    tcr = (tcr & ~0x04400000) | (auto_restart ? 0x04400000 : 0x04000000);
    251 #if 1
    252295    asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
     296#else /* Book E */
     297    asm volatile ("mfspr %0, 0x154" : "=r" ((tcr)));               /* TCR */
     298    tcr = (tcr & ~0x04400000) | (auto_restart ? 0x04400000 : 0x04000000);
     299    asm volatile ("mtspr 0x154, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
    253300#endif
    254 
    255301}
    256302
    257303
    … … void Install_clock( 
    279325   clockIrqConnData.on   = ClockOn;
    280326   clockIrqConnData.off  = ClockOff;
    281327   clockIrqConnData.isOn = ClockIsOn;
     328#ifndef ppc440
    282329   clockIrqConnData.name = BSP_PIT;
     330#else
     331   clockIrqConnData.name = BSP_DECREMENTER;
     332#endif
    283333   clockIrqConnData.hdl  = clock_isr;
    284334   if (!BSP_install_rtems_irq_handler (&clockIrqConnData)) {
    285335     printk("Unable to connect Clock Irq handler\n");
    … … ReInstall_clock( 
    300350  rtems_interrupt_disable(isrlevel);
    301351
    302352
     353#ifndef ppc440
    303354  clockIrqConnData.name = BSP_PIT;
     355#else
     356  clockIrqConnData.name = BSP_DECREMENTER;
     357#endif
    304358  if (!BSP_get_current_rtems_irq_handler(&clockIrqConnData)) {
    305359    printk("Unable to stop system clock\n");
    306360    rtems_fatal_error_occurred(1);
    … … ReInstall_clock( 
    311365  clockIrqConnData.on   = ClockOn;
    312366  clockIrqConnData.off  = ClockOff;
    313367  clockIrqConnData.isOn = ClockIsOn;
     368#ifndef ppc440
    314369  clockIrqConnData.name = BSP_PIT;
     370#else
     371  clockIrqConnData.name = BSP_DECREMENTER;
     372#endif
    315373  clockIrqConnData.hdl  = new_clock_isr;
    316374
    317375  if (!BSP_install_rtems_irq_handler (&clockIrqConnData)) {
    … … void Clock_exit(void) 
    335393{
    336394  rtems_irq_connect_data clockIrqConnData;
    337395
     396#ifndef ppc440
    338397  clockIrqConnData.name = BSP_PIT;
     398#else
     399  clockIrqConnData.name = BSP_DECREMENTER;
     400#endif
    339401  if (!BSP_get_current_rtems_irq_handler(&clockIrqConnData)) {
    340402    printk("Unable to stop system clock\n");
    341403    rtems_fatal_error_occurred(1);

  • c/src/lib/libcpu/powerpc/rtems/powerpc/debugmod.h 

    diff --git a/c/src/lib/libcpu/powerpc/rtems/powerpc/debugmod.h b/c/src/lib/libcpu/powerpc/rtems/powerpc/debugmod.h
index 692a564..b145ebe 100644
    a b  
    3535 * Note:
    3636 *      This file is included by both C and assembler code ( -DASM )
    3737 *
    38  *  $Id$
     38 *  $Id:$
    3939 */
    4040
    4141/*
    … … extern "C" { 
    7878#define PPC_DEBUG_MODEL_SINGLE_STEP_ONLY 2
    7979#define PPC_DEBUG_MODEL_IBM4xx           3
    8080
    81 #elif defined(ppc403) || defined(ppc405)
     81#elif defined(ppc403) || defined(ppc405) || defined(ppc440)
    8282
    8383#define PPC_DEBUG_MODEL          PPC_DEBUG_MODEL_IBM4xx
    8484

  • c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h 

    diff --git a/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h b/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h
index 9609fd1..79cf03a 100644
    a b  
    3838 * Note:
    3939 *      This file is included by both C and assembler code ( -DASM )
    4040 *
    41  *  $Id$
     41 *  $Id:$
    4242 */
    4343
    4444
    … … extern "C" { 
    137137#define PPC_HAS_EXCEPTION_PREFIX 0
    138138#define PPC_HAS_EVPR             1
    139139
     140#elif defined (ppc440)
     141
     142#define PPC_CACHE_ALIGNMENT         32
     143#define PPC_HAS_RI                   0
     144#define PPC_HAS_RFCI                 1
     145#define PPC_USE_MULTIPLE             1
     146#define PPC_I_CACHE              32768
     147#define PPC_D_CACHE              32768
     148#define PPC_HAS_EXCEPTION_PREFIX     0
     149#define PPC_HAS_EVPR                 1
     150
    140151#elif defined(mpc555)
    141152
    142153/* Copied from mpc505 */
    … … extern "C" { 
    380391
    381392#define PPC_IRQ_FIRST           PPC_IRQ_SYSTEM_RESET
    382393
    383 #if defined(ppc403) || defined(ppc405)
     394#if defined(ppc403) || defined(ppc405) || defined(ppc440)
    384395
    385396#define PPC_IRQ_CRIT     PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */
    386397#define PPC_IRQ_PIT      (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/

  • c/src/lib/libcpu/powerpc/shared/include/cpuIdent.c 

    diff --git a/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.c b/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.c
index 2bc7bfb..39ea5cf 100644
    a b  
    1010 *  found in found in the file LICENSE in this distribution or at
    1111 *  http://www.rtems.com/license/LICENSE.
    1212 *
    13  * $Id$
     13 * $Id:$
    1414 *
    1515 */
    1616
    … … ppc_feature_t current_ppc_features = { 
    3636  .has_epic = 0,
    3737  .has_shadowed_gprs = 0,
    3838  .has_ivpr = 0,
    39   .has_ivor = 0
     39  .has_ivor          = 0,
     40  .has_hwivor        = 0
    4041};
    4142
    4243char *get_ppc_cpu_type_name(ppc_cpu_id_t cpu)
    … … char *get_ppc_cpu_type_name(ppc_cpu_id_t cpu) 
    4546    case PPC_405:               return "PPC405";
    4647        case PPC_405GP:         return "PPC405GP";
    4748        case PPC_405EX:         return "PPC405EX";
     49    case PPC_440:               return "PPC440";
    4850    case PPC_601:               return "MPC601";
    4951    case PPC_5XX:               return "MPC5XX";
    5052    case PPC_603:               return "MPC603";
    … … ppc_cpu_id_t get_ppc_cpu_type(void) 
    110112    case PPC_405:
    111113    case PPC_405GP:
    112114    case PPC_405EX:
     115    case PPC_440:
    113116    case PPC_601:
    114117    case PPC_5XX:
    115118    case PPC_603:
    … … ppc_cpu_id_t get_ppc_cpu_type(void) 
    153156    case PPC_7400:
    154157        /* NOTE: PSIM PVR doesn't tell us anything (its
    155158     *       contents are not set based on what model
    156          *       the uses chooses but has to be programmed via
     159       *       the user chooses but has to be programmed via
    157160         *       the device file with the special value 0xfffe
    158161         *       telling us that we have a 'psim cpu').
    159162         *
    … … ppc_cpu_id_t get_ppc_cpu_type(void) 
    185188        case PPC_405EX:
    186189                current_ppc_features.is_bookE                   = PPC_BOOKE_405;
    187190        break;
     191    case PPC_440:
     192      current_ppc_features.is_bookE          = PPC_BOOKE_STD;
    188193        case PPC_8540:
    189194        case PPC_e200z0:
    190195        case PPC_e200z1:
    … … ppc_cpu_id_t get_ppc_cpu_type(void) 
    221226                        current_ppc_features.has_hwivor = 1;
    222227                        break;
    223228                case PPC_e200z6:
     229    case PPC_440:
    224230                        current_ppc_features.has_ivpr = 1;
    225231                        current_ppc_features.has_ivor = 1;
    226232                        break;

  • c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h 

    diff --git a/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h b/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h
index 0e64af8..37427b9 100644
    a b  
    1010 *  found in found in the file LICENSE in this distribution or at
    1111 *  http://www.rtems.com/license/LICENSE.
    1212 *
    13  *  $Id$
     13 *  $Id:$
    1414 */
    1515
    1616#ifndef _LIBCPU_CPUIDENT_H
    … … typedef enum 
    3535  PPC_604e = 0x9,
    3636  PPC_604r = 0xA,
    3737  PPC_7400 = 0xC,
    38   PPC_405  = 0x2001,
     38  PPC_405  = 0x2001,  /* Xilinx Virtex-II Pro or -4 */
    3939  PPC_405EX = 0x1291,   /* + 405EXr */
    4040  PPC_405GP = 0x4011,   /* + 405CR */
    4141  PPC_405GPr = 0x5091,
    4242  PPC_405EZ = 0x4151,
    4343  PPC_405EP = 0x5121,
     44  PPC_440 = 0x7ff2,  /* Xilinx Virtex-5*/
    4445  PPC_7455 = 0x8001, /* Kate Feng */
    4546  PPC_7457 = 0x8002,
    4647  PPC_620 = 0x16,
    … … static inline ppc_cpu_id_t ppc_cpu_current(void) 
    129130        return current_ppc_cpu;
    130131}
    131132
     133static inline bool ppc_cpu_is_e200()
     134{
     135        return ppc_cpu_current() == PPC_e200z0
     136                || ppc_cpu_current() == PPC_e200z1
     137                || ppc_cpu_current() == PPC_e200z6;
     138}
     139
    132140static inline bool ppc_cpu_is_e300()
    133141{
    134142        if (ppc_cpu_current() == PPC_UNKNOWN) {
    … … static inline bool ppc_cpu_is_e300() 
    139147                || ppc_cpu_current() == PPC_e300c3;
    140148}
    141149
     150static inline bool ppc_cpu_is_e500()
     151{
     152        return ppc_cpu_current() == PPC_8540;
     153                /* || ppc_cpu_current() == PPC_e500v2; */
     154}
     155
    142156static inline bool ppc_cpu_is(ppc_cpu_id_t cpu)
    143157{
    144158        return ppc_cpu_current() == cpu;

  • cpukit/score/cpu/powerpc/rtems/asm.h 

    diff --git a/cpukit/score/cpu/powerpc/rtems/asm.h b/cpukit/score/cpu/powerpc/rtems/asm.h
index d54c060..e6b90ec 100644
    a b  
    2525 *  COPYRIGHT (c) 1994.
    2626 *  On-Line Applications Research Corporation (OAR).
    2727 *
    28  *  $Id$
     28 *  $Id:$
    2929 */
    3030
    3131#ifndef _RTEMS_ASM_H
    … …  
    204204#define br5     0x085   /* DCR: memory bank register 5             */
    205205#define br6     0x086   /* DCR: memory bank register 6             */
    206206#define br7     0x087   /* DCR: memory bank register 7             */
     207
     208#elif defined(ppc440)
     209#define xer     0x001   /* SPR: Integer Exception Register                */
     210#define lr      0x008   /* SPR: Link Register                             */
     211#define ctr     0x009   /* SPR: Count Register                            */
     212#define pid     0x030   /* SPR: Process ID                                */
     213#define decar   0x036   /* SPR: Decrementer Auto-Reload                   */
     214#define dear    0x03d   /* SPR: Data Exception Address Register           */
     215#define esr     0x03e   /* SPR: Exception Syndrome Register               */
     216#define ivpr    0x03f   /* SPR: Interrupt Vector Prefix Register          */
     217#define sprg4_w 0x104   /* SPR: Special Purpose Register General 4 (WO)   */
     218#define sprg5_w 0x105   /* SPR: Special Purpose Register General 5 (WO)   */
     219#define sprg6_w 0x107   /* SPR: Special Purpose Register General 6 (WO)   */
     220#define sprg7_w 0x108   /* SPR: Special Purpose Register General 7 (WO)   */
     221#define tbl     0x10c   /* SPR: Time Base Lower                           */
     222#define tbu     0x10d   /* SPR: Time Base Upper                           */
     223#define pir     0x11e   /* SPR: Processor ID Register                     */
     224#define pvr     0x11f   /* SPR: Processor Version Register                */
     225#define dbsr    0x130   /* SPR: Debug Status Register                     */
     226#define dbcr0   0x134   /* SPR: Debug Control Register 0                  */
     227#define dbcr1   0x135   /* SPR: Debug Control Register 1                  */
     228#define dbcr2   0x136   /* SPR: Debug Control Register 2                  */
     229#define iac1    0x138   /* SPR: Instruction Address Compare 1             */
     230#define iac2    0x139   /* SPR: Instruction Address Compare 2             */
     231#define iac3    0x13a   /* SPR: Instruction Address Compare 3             */
     232#define iac4    0x13b   /* SPR: Instruction Address Compare 4             */
     233#define dac1    0x13c   /* SPR: Data Address Compare 1                    */
     234#define dac2    0x13d   /* SPR: Data Address Compare 2                    */
     235#define dvc1    0x13e   /* SPR: Data Value Compare 1                      */
     236#define dvc2    0x13f   /* SPR: Data Value Compare 2                      */
     237#define tsr     0x150   /* SPR: Timer Status Register                     */
     238#define tcr     0x154   /* SPR: Timer Control Register                    */
     239#define ivor0   0x190   /* SPR: Interrupt Vector Offset Register 0        */
     240#define ivor1   0x191   /* SPR: Interrupt Vector Offset Register 1        */
     241#define ivor2   0x192   /* SPR: Interrupt Vector Offset Register 2        */
     242#define ivor3   0x193   /* SPR: Interrupt Vector Offset Register 3        */
     243#define ivor4   0x194   /* SPR: Interrupt Vector Offset Register 4        */
     244#define ivor5   0x195   /* SPR: Interrupt Vector Offset Register 5        */
     245#define ivor6   0x196   /* SPR: Interrupt Vector Offset Register 6        */
     246#define ivor7   0x197   /* SPR: Interrupt Vector Offset Register 7        */
     247#define ivor8   0x198   /* SPR: Interrupt Vector Offset Register 8        */
     248#define ivor9   0x199   /* SPR: Interrupt Vector Offset Register 9        */
     249#define ivor10  0x19a   /* SPR: Interrupt Vector Offset Register 10       */
     250#define ivor11  0x19b   /* SPR: Interrupt Vector Offset Register 11       */
     251#define ivor12  0x19c   /* SPR: Interrupt Vector Offset Register 12       */
     252#define ivor13  0x19d   /* SPR: Interrupt Vector Offset Register 13       */
     253#define ivor14  0x19e   /* SPR: Interrupt Vector Offset Register 14       */
     254#define ivor15  0x19f   /* SPR: Interrupt Vector Offset Register 15       */
     255#define mcsr    0x23c   /* SPR: Machine Check Status Register             */
     256#define inv0    0x370   /* SPR: Instruction Cache Normal Victim 0         */
     257#define inv1    0x371   /* SPR: Instruction Cache Normal Victim 1         */
     258#define inv2    0x372   /* SPR: Instruction Cache Normal Victim 2         */
     259#define inv3    0x373   /* SPR: Instruction Cache Normal Victim 3         */
     260#define itv0    0x374   /* SPR: Instruction Cache Transient Victim 0      */
     261#define itv1    0x375   /* SPR: Instruction Cache Transient Victim 1      */
     262#define itv2    0x376   /* SPR: Instruction Cache Transient Victim 2      */
     263#define itv3    0x377   /* SPR: Instruction Cache Transient Victim 3      */
     264#define ccr1    0x378   /* SPR: Core Configuration Register 1             */
     265#define dnv0    0x390   /* SPR: Data Cache Normal Victim 0                */
     266#define dnv1    0x391   /* SPR: Data Cache Normal Victim 1                */
     267#define dnv2    0x392   /* SPR: Data Cache Normal Victim 2                */
     268#define dnv3    0x393   /* SPR: Data Cache Normal Victim 3                */
     269#define dtv0    0x394   /* SPR: Data Cache Transient Victim 0             */
     270#define dtv1    0x395   /* SPR: Data Cache Transient Victim 1             */
     271#define dtv2    0x396   /* SPR: Data Cache Transient Victim 2             */
     272#define dtv3    0x397   /* SPR: Data Cache Transient Victim 3             */
     273#define dvlim   0x398   /* SPR: Data Cache Victim Limit                   */
     274#define ivlim   0x399   /* SPR: Instruction Cache Victim Limit            */
     275#define rstcfg  0x39b   /* SPR: Reset Configuration                       */
     276#define dcdbtrl 0x39c   /* SPR: Data Cache Debug Tag Register Low         */
     277#define dcdbtrh 0x39d   /* SPR: Data Cache Debug Tag Register High        */
     278#define icdbtrl 0x39e   /* SPR: Instruction Cache Debug Tag Register Low  */
     279#define icdbtrh 0x39f   /* SPR: Instruction Cache Debug Tag Register High */
     280#define mmucr   0x3b2   /* SPR: Memory Management Unit Control Register   */
     281#define ccr0    0x3b3   /* SPR: Core Configuration Register 0             */
     282#define icdbdr  0x3d3   /* SPR: Instruction Cache Debug Data Register     */
     283#define dbdr    0x3f3   /* SPR: Debug Data Register                       */
    207284/* end of IBM400 series register definitions */
    208285
    209286#elif defined(mpc555)