RCS file: /usr1/CVS/rtems/cpukit/score/cpu/sparc64/rtems/score/sparc64.h,v
retrieving revision 1.3
diff -u -r1.3 sparc64.h
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287 | 287 | * |
288 | 288 | * sun4u and sun4v: softint_clr asr = 21, with mnemonic clear_softint |
289 | 289 | */ |
290 | | #define sparc64_clear_interrupt_bits( _bit_mask ) \ |
| 290 | #define sparc64_clear_interrupt_bits_reg( _bit_mask ) \ |
| 291 | do { \ |
| 292 | __asm__ volatile( "wr %%g0, %0, %%clear_softint" \ |
| 293 | : "=r" (_bit_mask) \ |
| 294 | :"0" (_bit_mask) ); \ |
| 295 | } while ( 0 ) |
| 296 | |
| 297 | #define sparc64_clear_interrupt_bits_const( _bit_mask ) \ |
291 | 298 | do { \ |
292 | | __asm__ volatile( "wr %%g0, %0, %%clear_softint" : "=r" (_bit_mask) \ |
293 | | : "0" (_bit_mask)); \ |
| 299 | __asm__ volatile( "wr %%g0, %0, %%clear_softint" : : "n" (_bit_mask) ); \ |
294 | 300 | } while ( 0 ) |
295 | 301 | |
296 | 302 | /************* DEPRECATED ****************/ |