| 1 | /*===============================================================*\
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| 2 | | Project: RTEMS generic MPC5200 BSP |
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| 3 | +-----------------------------------------------------------------+
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| 4 | | Partially based on the code references which are named below. |
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| 5 | | Adaptions, modifications, enhancements and any recent parts of |
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| 6 | | the code are: |
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| 7 | | Copyright (c) 2005 |
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| 8 | | Embedded Brains GmbH |
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| 9 | | Obere Lagerstr. 30 |
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| 10 | | D-82178 Puchheim |
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| 11 | | Germany |
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| 12 | | rtems@embedded-brains.de |
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| 13 | +-----------------------------------------------------------------+
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| 14 | | The license and distribution terms for this file may be |
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| 15 | | found in the file LICENSE in this distribution or at |
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| 16 | | |
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| 17 | | http://www.rtems.com/license/LICENSE. |
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| 18 | | |
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| 19 | +-----------------------------------------------------------------+
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| 20 | | this file contains the code to initialize the cpu |
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| 21 | \*===============================================================*/
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| 22 | /***********************************************************************/
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| 23 | /* */
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| 24 | /* Module: cpuinit.c */
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| 25 | /* Date: 07/17/2003 */
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| 26 | /* Purpose: RTEMS MPC5x00 C level startup code */
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| 27 | /* */
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| 28 | /*---------------------------------------------------------------------*/
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| 29 | /* */
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| 30 | /* Description: This file contains additional functions for */
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| 31 | /* initializing the MPC5x00 CPU */
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| 32 | /* */
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| 33 | /*---------------------------------------------------------------------*/
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| 34 | /* */
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| 35 | /* Code */
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| 36 | /* References: MPC8260ads additional CPU initialization */
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| 37 | /* Module: cpuinit.c */
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| 38 | /* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */
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| 39 | /* Version 1.1 */
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| 40 | /* Date: 10/22/2002 */
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| 41 | /* */
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| 42 | /* Author(s) / Copyright(s): */
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| 43 | /* */
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| 44 | /* Written by Jay Monkman (jmonkman@frasca.com) */
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| 45 | /* */
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| 46 | /*---------------------------------------------------------------------*/
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| 47 | /* */
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| 48 | /* Partially based on the code references which are named above. */
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| 49 | /* Adaptions, modifications, enhancements and any recent parts of */
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| 50 | /* the code are under the right of */
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| 51 | /* */
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| 52 | /* IPR Engineering, Dachauer Straße 38, D-80335 München */
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| 53 | /* Copyright(C) 2003 */
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| 54 | /* */
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| 55 | /*---------------------------------------------------------------------*/
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| 56 | /* */
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| 57 | /* IPR Engineering makes no representation or warranties with */
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| 58 | /* respect to the performance of this computer program, and */
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| 59 | /* specifically disclaims any responsibility for any damages, */
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| 60 | /* special or consequential, connected with the use of this program. */
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| 61 | /* */
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| 62 | /*---------------------------------------------------------------------*/
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| 63 | /* */
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| 64 | /* Version history: 1.0 */
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| 65 | /* */
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| 66 | /***********************************************************************/
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| 67 |
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| 68 | #include <stdbool.h>
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| 69 | #include <string.h>
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| 70 |
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| 71 | #include <libcpu/powerpc-utility.h>
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| 72 | #include <libcpu/mmu.h>
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| 73 |
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| 74 | #include <bsp.h>
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| 75 | #include <bsp/mpc5200.h>
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| 76 |
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| 77 | #define SET_DBAT( n, uv, lv) \
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| 78 | do { \
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| 79 | PPC_SET_SPECIAL_PURPOSE_REGISTER( DBAT##n##L, lv); \
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| 80 | PPC_SET_SPECIAL_PURPOSE_REGISTER( DBAT##n##U, uv); \
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| 81 | } while (0)
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| 82 |
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| 83 | #define SET_IBAT( n, uv, lv) \
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| 84 | do { \
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| 85 | PPC_SET_SPECIAL_PURPOSE_REGISTER( IBAT##n##L, lv); \
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| 86 | PPC_SET_SPECIAL_PURPOSE_REGISTER( IBAT##n##U, uv); \
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| 87 | } while (0)
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| 88 |
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| 89 | static void calc_dbat_regvals(
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| 90 | BAT *bat_ptr,
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| 91 | uint32_t base_addr,
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| 92 | uint32_t size,
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| 93 | bool flg_w,
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| 94 | bool flg_i,
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| 95 | bool flg_m,
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| 96 | bool flg_g,
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| 97 | uint32_t flg_bpp
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| 98 | )
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| 99 | {
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| 100 | uint32_t block_mask = 0xffffffff;
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| 101 | uint32_t end_addr = base_addr + size - 1;
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| 102 |
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| 103 | /* Determine block mask, that overlaps the whole block */
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| 104 | while ((end_addr & block_mask) != (base_addr & block_mask)) {
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| 105 | block_mask <<= 1;
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| 106 | }
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| 107 |
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| 108 | bat_ptr->batu.bepi = base_addr >> (32 - 15);
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| 109 | bat_ptr->batu.bl = ~(block_mask >> (28 - 11));
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| 110 | bat_ptr->batu.vs = 1;
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| 111 | bat_ptr->batu.vp = 1;
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| 112 |
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| 113 | bat_ptr->batl.brpn = base_addr >> (32 - 15);
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| 114 | bat_ptr->batl.w = flg_w;
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| 115 | bat_ptr->batl.i = flg_i;
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| 116 | bat_ptr->batl.m = flg_m;
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| 117 | bat_ptr->batl.g = flg_g;
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| 118 | bat_ptr->batl.pp = flg_bpp;
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| 119 | }
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| 120 |
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| 121 | static void calc_ibat_regvals(
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| 122 | BAT *bat_ptr,
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| 123 | uint32_t base_addr,
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| 124 | uint32_t size,
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| 125 | bool flg_w,
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| 126 | bool flg_i,
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| 127 | bool flg_m,
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| 128 | bool flg_g,
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| 129 | uint32_t flg_bpp
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| 130 | )
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| 131 | {
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| 132 | uint32_t block_mask = 0xffffffff;
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| 133 | uint32_t end_addr = base_addr + size - 1;
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| 134 |
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| 135 | /* Determine block mask, that overlaps the whole block */
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| 136 | while ((end_addr & block_mask) != (base_addr & block_mask)) {
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| 137 | block_mask <<= 1;
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| 138 | }
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| 139 |
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| 140 | bat_ptr->batu.bepi = base_addr >> (32 - 15);
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| 141 | bat_ptr->batu.bl = ~(block_mask >> (28 - 11));
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| 142 | bat_ptr->batu.vs = 1;
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| 143 | bat_ptr->batu.vp = 1;
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| 144 |
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| 145 | bat_ptr->batl.brpn = base_addr >> (32 - 15);
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| 146 | bat_ptr->batl.w = flg_w;
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| 147 | bat_ptr->batl.i = flg_i;
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| 148 | bat_ptr->batl.m = flg_m;
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| 149 | bat_ptr->batl.g = flg_g;
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| 150 | bat_ptr->batl.pp = flg_bpp;
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| 151 | }
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| 152 |
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| 153 | #if defined (BRS5L)
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| 154 | void cpu_init_bsp(void)
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| 155 | {
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| 156 | BAT dbat;
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| 157 |
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| 158 | calc_dbat_regvals(
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| 159 | &dbat,
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| 160 | (uint32_t) bsp_ram_start,
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| 161 | (uint32_t) bsp_ram_size,
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| 162 | true,
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| 163 | false,
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| 164 | false,
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| 165 | false,
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| 166 | BPP_RW
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| 167 | );
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| 168 | SET_DBAT(0,dbat.batu,dbat.batl);
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| 169 |
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| 170 | calc_dbat_regvals(
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| 171 | &dbat,
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| 172 | (uint32_t) bsp_rom_start,
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| 173 | (uint32_t) bsp_rom_size,
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| 174 | true,
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| 175 | false,
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| 176 | false,
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| 177 | false,
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| 178 | BPP_RX
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| 179 | );
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| 180 | SET_DBAT(1,dbat.batu,dbat.batl);
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| 181 |
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| 182 | calc_dbat_regvals(
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| 183 | &dbat,
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| 184 | (uint32_t) MBAR,
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| 185 | 128 * 1024,
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| 186 | false,
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| 187 | true,
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| 188 | false,
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| 189 | true,
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| 190 | BPP_RW
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| 191 | );
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| 192 | SET_DBAT(2,dbat.batu,dbat.batl);
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| 193 |
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| 194 | calc_dbat_regvals(
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| 195 | &dbat,
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| 196 | (uint32_t) bsp_dpram_start,
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| 197 | 128 * 1024,
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| 198 | false,
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| 199 | true,
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| 200 | false,
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| 201 | true,
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| 202 | BPP_RW
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| 203 | );
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| 204 | SET_DBAT(3,dbat.batu,dbat.batl);
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| 205 | }
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| 206 | #elif defined (HAS_UBOOT)
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| 207 | void cpu_init_bsp(void)
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| 208 | {
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| 209 | BAT dbat;
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| 210 | uint32_t start = 0;
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| 211 |
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| 212 | /*
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| 213 | * Program BAT0 for RAM
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| 214 | */
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| 215 | calc_dbat_regvals(
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| 216 | &dbat,
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| 217 | bsp_uboot_board_info.bi_memstart,
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| 218 | bsp_uboot_board_info.bi_memsize,
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| 219 | true,
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| 220 | false,
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| 221 | false,
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| 222 | false,
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| 223 | BPP_RW
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| 224 | );
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| 225 | SET_DBAT(0,dbat.batu,dbat.batl);
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| 226 |
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| 227 | /*
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| 228 | * Program BAT1 for Flash
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| 229 | *
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| 230 | * WARNING!! Some Freescale LITE5200B boards ship with a version of
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| 231 | * U-Boot that lies about the starting address of Flash. This check
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| 232 | * corrects that.
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| 233 | */
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| 234 | if ((bsp_uboot_board_info.bi_flashstart + bsp_uboot_board_info.bi_flashsize)
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| 235 | < bsp_uboot_board_info.bi_flashstart) {
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| 236 | start = 0 - bsp_uboot_board_info.bi_flashsize;
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| 237 | } else {
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| 238 | start = bsp_uboot_board_info.bi_flashstart;
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| 239 | }
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| 240 | calc_dbat_regvals(
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| 241 | &dbat,
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| 242 | start,
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| 243 | bsp_uboot_board_info.bi_flashsize,
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| 244 | true,
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| 245 | false,
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| 246 | false,
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| 247 | false,
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| 248 | BPP_RX
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| 249 | );
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| 250 | SET_DBAT(1,dbat.batu,dbat.batl);
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| 251 |
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| 252 | /*
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| 253 | * Program BAT2 for the MBAR
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| 254 | */
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| 255 | calc_dbat_regvals(
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| 256 | &dbat,
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| 257 | (uint32_t) MBAR,
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| 258 | 128 * 1024,
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| 259 | false,
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| 260 | true,
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| 261 | false,
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| 262 | true,
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| 263 | BPP_RW
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| 264 | );
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| 265 | SET_DBAT(2,dbat.batu,dbat.batl);
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| 266 |
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| 267 | /*
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| 268 | * If there is SRAM, program BAT3 for that memory
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| 269 | */
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| 270 | if (bsp_uboot_board_info.bi_sramsize != 0) {
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| 271 | calc_dbat_regvals(
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| 272 | &dbat,
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| 273 | bsp_uboot_board_info.bi_sramstart,
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| 274 | bsp_uboot_board_info.bi_sramsize,
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| 275 | false,
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| 276 | true,
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| 277 | true,
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| 278 | true,
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| 279 | BPP_RW
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| 280 | );
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| 281 | SET_DBAT(3,dbat.batu,dbat.batl);
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| 282 | }
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| 283 | }
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| 284 | #elif defined (PCM032)
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| 285 | void cpu_init_bsp(void)
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| 286 | {
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| 287 | BAT dbat;
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| 288 | BAT ibat;
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| 289 |
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| 290 | calc_dbat_regvals(
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| 291 | &dbat,
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| 292 | (uint32_t) bsp_ram_start,
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| 293 | (uint32_t) bsp_ram_size,
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| 294 | false,
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| 295 | false,
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| 296 | false,
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| 297 | false,
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| 298 | BPP_RW
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| 299 | );
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| 300 | SET_DBAT(0,dbat.batu,dbat.batl);
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| 301 |
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| 302 | calc_ibat_regvals(
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| 303 | &ibat,
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| 304 | (uint32_t) bsp_ram_start,
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| 305 | (uint32_t) bsp_ram_size,
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| 306 | false,
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| 307 | false,
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| 308 | false,
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| 309 | false,
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| 310 | BPP_RW
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| 311 | );
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| 312 | SET_IBAT(0,ibat.batu,ibat.batl);
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| 313 |
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| 314 | calc_dbat_regvals(
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| 315 | &dbat,
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| 316 | (uint32_t) bsp_rom_start,
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| 317 | (uint32_t) bsp_rom_size,
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| 318 | false,
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| 319 | true,
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| 320 | false,
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| 321 | false,
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| 322 | BPP_RX
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| 323 | );
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| 324 | SET_DBAT(1,dbat.batu,dbat.batl);
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| 325 |
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| 326 | calc_ibat_regvals(
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| 327 | &ibat,
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| 328 | (uint32_t) bsp_rom_start,
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| 329 | (uint32_t) bsp_rom_size,
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| 330 | false,
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| 331 | false,
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| 332 | false,
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| 333 | false,
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| 334 | BPP_RX
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| 335 | );
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| 336 | SET_IBAT(1,ibat.batu,ibat.batl);
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| 337 |
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| 338 | calc_dbat_regvals(
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| 339 | &dbat,
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| 340 | (uint32_t) MBAR,
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| 341 | 128 * 1024,
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| 342 | false,
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| 343 | true,
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| 344 | false,
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| 345 | false,
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| 346 | BPP_RW
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| 347 | );
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| 348 | SET_DBAT(2,dbat.batu,dbat.batl);
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| 349 |
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| 350 | calc_ibat_regvals(
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| 351 | &ibat,
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| 352 | (uint32_t) MBAR,
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| 353 | 128 * 1024,
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| 354 | false,
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| 355 | true,
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| 356 | false,
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| 357 | false,
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| 358 | BPP_RW
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| 359 | );
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| 360 | SET_IBAT(2,ibat.batu,ibat.batl);
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| 361 |
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| 362 | calc_dbat_regvals(
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| 363 | &dbat,
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| 364 | (uint32_t) bsp_dpram_start,
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| 365 | 128 * 1024,
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| 366 | false,
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| 367 | true,
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| 368 | false,
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| 369 | false,
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| 370 | BPP_RW
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| 371 | );
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| 372 | SET_DBAT(3,dbat.batu,dbat.batl);
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| 373 |
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| 374 | calc_ibat_regvals(
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| 375 | &ibat,
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| 376 | (uint32_t) bsp_dpram_start,
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| 377 | 128 * 1024,
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| 378 | false,
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| 379 | false,
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| 380 | false,
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| 381 | false,
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| 382 | BPP_RW
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| 383 | );
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| 384 | SET_IBAT(3,ibat.batu,ibat.batl);
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| 385 |
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| 386 | }
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| 387 | #else
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| 388 | #warning "Using BAT register values set by environment"
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| 389 | #endif
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| 390 |
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| 391 | void cpu_init(void)
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| 392 | {
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| 393 | uint32_t msr;
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| 394 |
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| 395 | /* Set up DBAT registers in MMU */
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| 396 | cpu_init_bsp();
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| 397 |
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| 398 | /* Read MSR */
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| 399 | msr = ppc_machine_state_register();
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| 400 |
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| 401 | /* Enable instruction MMU in MSR */
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| 402 | msr |= MSR_IR;
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| 403 |
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| 404 | /* Update MSR */
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| 405 | ppc_set_machine_state_register(msr);
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| 406 |
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| 407 | PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_ICE | HID0_ICFI);
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| 408 | PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS(HID0, HID0_ICFI);
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| 409 |
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| 410 | #if defined(SHOW_MORE_INIT_SETTINGS)
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| 411 | { extern void ShowBATS(void);
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| 412 | ShowBATS();
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| 413 | }
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| 414 | #endif
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| 415 |
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| 416 | /* Read MSR */
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| 417 | msr = ppc_machine_state_register();
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| 418 |
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| 419 | /* Enable data MMU in MSR */
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| 420 | msr |= MSR_DR;
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| 421 |
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| 422 | /* Update MSR */
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| 423 | ppc_set_machine_state_register( msr);
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| 424 |
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| 425 | /*
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| 426 | * Enable data cache.
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| 427 | *
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| 428 | * NOTE: TRACE32 now supports data cache for MGT5x00.
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| 429 | */
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| 430 | PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_DCE);
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| 431 | } |
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