Ticket #1933: irq_asm1.patch
File irq_asm1.patch, 2.7 KB (added by Daniel Hellstrom, on 10/07/11 at 11:49:42) |
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c/src/lib/libbsp/sparc/shared/irq_asm.S
RCS file: /home/cvspserver/SMP_Repository/rtems-smp/c/src/lib/libbsp/sparc/shared/irq_asm.S,v retrieving revision 1.2 diff -u -r1.2 irq_asm.S
267 267 add %l5, %l7, %l5 268 268 #endif 269 269 ld [%l5], %l5 /* l5 = pointer to per CPU */ 270 nop271 nop272 270 273 271 /* 274 272 * On multi-core system, we need to use SMP safe versions … … 277 275 * _ISR_SMP_Enter returns the interrupt nest level. If we are 278 276 * outermost interrupt, then we need to switch stacks. 279 277 */ 280 mov %sp, %fp281 278 call SYM(_ISR_SMP_Enter), 0 282 nop! delay slot279 mov %sp, %fp ! delay slot 283 280 cmp %o0, 0 284 281 #else 285 282 /* … … 321 318 /* 322 319 * Do we need to switch to the interrupt stack? 323 320 */ 324 b nzdont_switch_stacks ! No, then do not switch stacks325 ld[%l5 + PER_CPU_INTERRUPT_STACK_HIGH], %sp321 beq,a dont_switch_stacks ! No, then do not switch stacks 322 ld [%l5 + PER_CPU_INTERRUPT_STACK_HIGH], %sp 326 323 327 324 dont_switch_stacks: 328 325 /* … … 358 355 nop ! delay slot 359 356 cmp %o0, 0 360 357 bz simple_return 358 nop 361 359 #else 362 360 !sethi %hi(SYM(_Thread_Dispatch_disable_level)), %l4 363 361 !ld [%l5 + PER_CPU_ISR_NEST_LEVEL], %l7 … … 405 403 ld [%l6 + %lo(SYM(_CPU_ISR_Dispatch_disable))], %l7 406 404 orcc %l7, %g0, %g0 ! Is this thread already doing an ISR? 407 405 bnz simple_return ! Yes, then do a "simple" exit 408 nop406 nop 409 407 410 408 /* 411 409 * If a context switch is necessary, then do fudge stack to … … 413 411 */ 414 412 415 413 ldub [%l5 + PER_CPU_DISPATCH_NEEDED], %l5 416 nop417 nop418 419 414 orcc %l5, %g0, %g0 ! Is thread switch necessary? 420 415 bz simple_return ! No, then return 416 nop 421 417 #endif 422 418 /* 423 419 * Invoke interrupt dispatcher. … … 479 475 nop 480 476 #endif 481 477 ld [%l5], %l5 /* l5 = pointer to per CPU */ 482 nop483 nop484 478 #else 485 479 sethi %hi(_Per_CPU_Information), %l5 486 480 add %l5, %lo(_Per_CPU_Information), %l5 487 481 #endif 488 482 ldub [%l5 + PER_CPU_DISPATCH_NEEDED], %l5 489 nop490 nop491 492 483 orcc %l5, %g0, %g0 ! Is thread switch necessary? 493 484 bz allow_nest_again 494 485 nop