commit e0d4d55f693886b991c1b35b53091d005cea8cf5
Author: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Sat Jul 30 17:13:51 2011 +0200
new LM32 interrupt handler (based on NIOS)
diff --git a/cpukit/score/cpu/lm32/irq.c b/cpukit/score/cpu/lm32/irq.c
index 0bf648d..d07d7cf 100644
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1 | 1 | /* |
2 | | * lm32 interrupt handler |
| 2 | * lm32 exception and interrupt handler |
3 | 3 | * |
4 | 4 | * Derived from c4x/irq.c and nios2/irq.c |
5 | 5 | * |
6 | | * COPYRIGHT (c) 1989-2009. |
| 6 | * COPYRIGHT (c) 1989-2007. |
7 | 7 | * On-Line Applications Research Corporation (OAR). |
8 | 8 | * |
9 | 9 | * The license and distribution terms for this file may be |
10 | 10 | * found in the file LICENSE in this distribution or at |
11 | 11 | * http://www.rtems.com/license/LICENSE. |
12 | 12 | * |
13 | | * $Id: irq.c,v 1.8 2011/04/21 19:05:14 jennifer Exp $ |
| 13 | * $Id: irq.c,v 1.9 2011/04/21 19:05:14 jennifer Exp $ |
14 | 14 | */ |
15 | 15 | |
16 | 16 | #ifdef HAVE_CONFIG_H |
… |
… |
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19 | 19 | |
20 | 20 | #include <rtems/system.h> |
21 | 21 | #include <rtems/score/cpu.h> |
22 | | #include <rtems/score/thread.h> |
23 | 22 | #include <rtems/score/isr.h> |
24 | | #include <rtems/score/percpu.h> |
| 23 | #include <rtems/score/thread.h> |
25 | 24 | |
26 | 25 | /* |
27 | 26 | * This routine provides the RTEMS interrupt management. |
… |
… |
|
29 | 28 | * Upon entry, interrupts are disabled |
30 | 29 | */ |
31 | 30 | |
32 | | #if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) |
33 | | unsigned long *_old_stack_ptr; |
34 | | #endif |
| 31 | unsigned long *_old_stack_ptr; |
35 | 32 | |
36 | 33 | void *_exception_stack_frame; |
37 | 34 | |
… |
… |
void __ISR_Handler(uint32_t vector, CPU_Interrupt_frame *ifr) |
44 | 41 | |
45 | 42 | /* Interrupts are disabled upon entry to this Handler */ |
46 | 43 | |
47 | | _Thread_Dispatch_increment_disable_level(); |
48 | | |
49 | | #if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) |
50 | 44 | if ( _ISR_Nest_level == 0 ) { |
51 | 45 | /* Install irq stack */ |
52 | 46 | _old_stack_ptr = stack_ptr; |
53 | 47 | stack_ptr = _CPU_Interrupt_stack_high - 4; |
54 | 48 | } |
55 | | #endif |
56 | 49 | |
57 | 50 | _ISR_Nest_level++; |
58 | 51 | |
| 52 | _Thread_Dispatch_increment_disable_level(); |
| 53 | |
59 | 54 | if ( _ISR_Vector_table[ vector] ) |
60 | 55 | { |
61 | 56 | (*_ISR_Vector_table[ vector ])(vector, ifr); |
… |
… |
void __ISR_Handler(uint32_t vector, CPU_Interrupt_frame *ifr) |
64 | 59 | /* Make sure that interrupts are disabled again */ |
65 | 60 | _CPU_ISR_Disable( level ); |
66 | 61 | |
| 62 | _Thread_Dispatch_decrement_disable_level(); |
| 63 | |
67 | 64 | _ISR_Nest_level--; |
68 | 65 | |
69 | | #if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) |
70 | | if( _ISR_Nest_level == 0) |
| 66 | if( _ISR_Nest_level == 0) { |
71 | 67 | stack_ptr = _old_stack_ptr; |
72 | | #endif |
73 | 68 | |
74 | | _Thread_Dispatch_decrement_disable_level(); |
| 69 | if( !_Thread_Dispatch_in_critical_section() ) |
| 70 | { |
| 71 | if ( _Thread_Dispatch_necessary ) { |
| 72 | _CPU_ISR_Enable( level ); |
| 73 | /* save off our stack frame so the context switcher can get to it */ |
| 74 | _exception_stack_frame = ifr; |
| 75 | _Thread_Dispatch(); |
| 76 | /* and make sure its clear in case we didn't dispatch. if we did, its |
| 77 | * already cleared */ |
| 78 | _exception_stack_frame = NULL; |
| 79 | /* may have switched to another task and not return here immed. */ |
| 80 | _CPU_ISR_Disable( level ); /* Keep _pairs_ of Enable/Disable */ |
| 81 | } |
| 82 | } |
| 83 | } |
75 | 84 | |
76 | 85 | _CPU_ISR_Enable( level ); |
77 | | |
78 | | if ( _ISR_Nest_level ) |
79 | | return; |
80 | | |
81 | | if ( _Thread_Dispatch_necessary ) { |
82 | | |
83 | | /* save off our stack frame so the context switcher can get to it */ |
84 | | _exception_stack_frame = ifr; |
85 | | |
86 | | _Thread_Dispatch(); |
87 | | |
88 | | /* and make sure its clear in case we didn't dispatch. if we did, its |
89 | | * already cleared */ |
90 | | _exception_stack_frame = NULL; |
91 | | } |
92 | 86 | } |
93 | | |