Ticket #1781: patch_v1.1

File patch_v1.1, 131.0 KB (added by Rohan, on Apr 20, 2011 at 3:10:01 PM)

Blackfin 52X patch v 1.1 added change log

Line 
1diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libbsp/bfin/bf537Stamp/ChangeLog rtems/c/src/lib/libbsp/bfin/bf537Stamp/ChangeLog
2*** rtems-4.10.0/c/src/lib/libbsp/bfin/bf537Stamp/ChangeLog     2011-02-02 10:14:13.000000000 -0500
3--- rtems/c/src/lib/libbsp/bfin/bf537Stamp/ChangeLog    2011-04-20 11:40:42.000000000 -0400
4***************
5*** 1,3 ****
6--- 1,10 ----
7+ 2011-04-20  Rohan Kangralkar <rkangral@ece.neu.edu>
8+ ------------------------------------------------------------------------
9+ r36 | rkangral | 2011-03-15 16:59:39 -0400 (Tue, 15 Mar 2011) | 1 line
10+   * console/console-io.c: The UART RX and TX are different ISR now. So the
11+       array containing the registeration changes. The change is due to change
12+       in the libcup uart function.
13+   
14  2011-02-02    Ralf Corsépius <ralf.corsepius@rtems.org>
15 
16        * configure.ac: Require autoconf-2.68, automake-1.11.1.
17diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libbsp/bfin/bf537Stamp/console/console.c rtems/c/src/lib/libbsp/bfin/bf537Stamp/console/console.c
18*** rtems-4.10.0/c/src/lib/libbsp/bfin/bf537Stamp/console/console.c     2009-12-10 23:10:27.000000000 -0500
19--- rtems/c/src/lib/libbsp/bfin/bf537Stamp/console/console.c    2011-03-15 16:59:39.000000000 -0400
20***************
21*** 7,13 ****
22   *  found in the file LICENSE in this distribution or at
23   *  http://www.rtems.com/license/LICENSE.
24   *
25!  *  $Id: console.c,v 1.5 2009/12/11 04:10:27 ralf Exp $
26   */
27 
28 
29--- 7,13 ----
30   *  found in the file LICENSE in this distribution or at
31   *  http://www.rtems.com/license/LICENSE.
32   *
33!  *  $Id: console.c 36 2011-03-15 20:59:39Z rkangral $
34   */
35 
36 
37***************
38*** 26,41 ****
39  */
40 
41  static bfin_uart_channel_t channels[] = {
42!   {"/dev/console",
43!    (char *) UART0_BASE_ADDRESS,
44!    CONSOLE_USE_INTERRUPTS,
45! #ifdef CONSOLE_FORCE_BAUD
46!    CONSOLE_FORCE_BAUD,
47! #else
48!    0,
49! #endif
50!    NULL,
51!    0}
52 
53  #if (!BFIN_ON_SKYEYE)
54  ,
55--- 26,46 ----
56  */
57 
58  static bfin_uart_channel_t channels[] = {
59!     {"/dev/console",
60!      UART0_BASE_ADDRESS,
61!      0,
62!      0,
63!      CONSOLE_USE_INTERRUPTS,
64!      0,
65!   #ifdef CONSOLE_FORCE_BAUD
66!      CONSOLE_FORCE_BAUD,
67!   #else
68!      0,
69!   #endif
70!      NULL,
71!      0,
72!      0}
73!   };
74 
75  #if (!BFIN_ON_SKYEYE)
76  ,
77***************
78*** 56,65 ****
79 
80  #if CONSOLE_USE_INTERRUPTS
81  static bfin_isr_t bfinUARTISRs[] = {
82!   {SIC_DMA8_UART0_RX_VECTOR, bfin_uart_isr, 0, 0, NULL},
83!   {SIC_DMA10_UART1_RX_VECTOR, bfin_uart_isr, 0, 0, NULL},
84!   {SIC_DMA9_UART0_TX_VECTOR, bfin_uart_isr, 0, 0, NULL},
85!   {SIC_DMA11_UART1_TX_VECTOR, bfin_uart_isr, 0, 0, NULL}
86  };
87  #endif
88 
89--- 61,70 ----
90 
91  #if CONSOLE_USE_INTERRUPTS
92  static bfin_isr_t bfinUARTISRs[] = {
93!   {SIC_DMA8_UART0_RX_VECTOR, bfinUart_rxIsr, 0, 0, NULL},
94!   {SIC_DMA10_UART1_RX_VECTOR, bfinUart_rxIsr, 0, 0, NULL},
95!   {SIC_DMA9_UART0_TX_VECTOR, bfinUart_txIsr, 0, 0, NULL},
96!   {SIC_DMA11_UART1_TX_VECTOR, bfinUart_txIsr, 0, 0, NULL}
97  };
98  #endif
99 
100diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libbsp/bfin/eZKit533/ChangeLog rtems/c/src/lib/libbsp/bfin/eZKit533/ChangeLog
101*** rtems-4.10.0/c/src/lib/libbsp/bfin/eZKit533/ChangeLog       2011-02-02 10:14:16.000000000 -0500
102--- rtems/c/src/lib/libbsp/bfin/eZKit533/ChangeLog      2011-04-20 11:40:42.000000000 -0400
103***************
104*** 1,3 ****
105--- 1,12 ----
106+ 2011-04-20  Rohan Kangralkar <rkangral@ece.neu.edu>
107+ ------------------------------------------------------------------------
108+ r36 | rkangral | 2011-03-15 16:59:39 -0400 (Tue, 15 Mar 2011) | 1 line
109+   * console/console-io.c: The UART RX and TX are different ISR now. So the
110+       array containing the registeration changes. The change is due to change
111+       in the libcup uart function.
112+   
113+     
114+   
115  2011-02-02    Ralf Corsépius <ralf.corsepius@rtems.org>
116 
117        * configure.ac: Require autoconf-2.68, automake-1.11.1.
118diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libbsp/bfin/eZKit533/console/console-io.c rtems/c/src/lib/libbsp/bfin/eZKit533/console/console-io.c
119*** rtems-4.10.0/c/src/lib/libbsp/bfin/eZKit533/console/console-io.c    2009-12-10 23:09:43.000000000 -0500
120--- rtems/c/src/lib/libbsp/bfin/eZKit533/console/console-io.c   2011-03-15 16:59:39.000000000 -0400
121***************
122*** 11,17 ****
123   *  found in the file LICENSE in this distribution or at
124   *  http://www.rtems.com/license/LICENSE.
125   *
126!  *  $Id: console-io.c,v 1.5 2009/12/11 04:09:43 ralf Exp $
127   */
128 
129 
130--- 11,17 ----
131   *  found in the file LICENSE in this distribution or at
132   *  http://www.rtems.com/license/LICENSE.
133   *
134!  *  $Id: console-io.c 36 2011-03-15 20:59:39Z rkangral $
135   */
136 
137 
138***************
139*** 26,39 ****
140 
141  static bfin_uart_channel_t channels[] = {
142    {"/dev/console",
143!    (char *) UART0_BASE_ADDRESS,
144     CONSOLE_USE_INTERRUPTS,
145  #ifdef CONSOLE_FORCE_BAUD
146     CONSOLE_FORCE_BAUD,
147  #else
148     0,
149  #endif
150     NULL,
151     0}
152  };
153 
154--- 26,43 ----
155 
156  static bfin_uart_channel_t channels[] = {
157    {"/dev/console",
158!    UART0_BASE_ADDRESS,
159!    0,
160!    0,
161     CONSOLE_USE_INTERRUPTS,
162+    0,
163  #ifdef CONSOLE_FORCE_BAUD
164     CONSOLE_FORCE_BAUD,
165  #else
166     0,
167  #endif
168     NULL,
169+    0,
170     0}
171  };
172 
173***************
174*** 45,52 ****
175 
176  #if CONSOLE_USE_INTERRUPTS
177  static bfin_isr_t bfinUARTISRs[] = {
178!   {SIC_DMA6_UART0_RX_VECTOR, bfin_uart_isr, 0, 0, NULL},
179!   {SIC_DMA7_UART0_TX_VECTOR, bfin_uart_isr, 0, 0, NULL},
180  };
181  #endif
182 
183--- 49,56 ----
184 
185  #if CONSOLE_USE_INTERRUPTS
186  static bfin_isr_t bfinUARTISRs[] = {
187!   {SIC_DMA6_UART0_RX_VECTOR, bfinUart_rxIsr, 0, 0, NULL},
188!   {SIC_DMA7_UART0_TX_VECTOR, bfinUart_txIsr, 0, 0, NULL},
189  };
190  #endif
191 
192diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/bsp_specs rtems/c/src/lib/libbsp/bfin/TLL6527M/bsp_specs
193*** rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/bsp_specs       1969-12-31 19:00:00.000000000 -0500
194--- rtems/c/src/lib/libbsp/bfin/TLL6527M/bsp_specs      2011-02-25 15:53:20.000000000 -0500
195***************
196*** 0 ****
197--- 1,10 ----
198+ %rename endfile old_endfile
199+ %rename startfile old_startfile
200+ %rename link old_link
201+
202+ *startfile:
203+ %{!qrtems: %(old_startfile)} \
204+ %{!nostdlib: %{qrtems: start.o%s -e __start}}
205+
206+ *link:
207+ %{!qrtems: %(old_link)} %{qrtems: -dc -dp -N}
208diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/ChangeLog rtems/c/src/lib/libbsp/bfin/TLL6527M/ChangeLog
209*** rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/ChangeLog       1969-12-31 19:00:00.000000000 -0500
210--- rtems/c/src/lib/libbsp/bfin/TLL6527M/ChangeLog      2011-04-20 11:40:42.000000000 -0400
211***************
212*** 0 ****
213--- 1,6 ----
214+ 2011-04-20  Rohan Kangralkar <rkangral@ece.neu.edu>
215+ Initial port of the BF52X for TLL6527M
216+     * all files : Initial port for the TLL6527Mboard that contains blackfin
217+      52X range of processors. Used eZKit533 as a reference for building the
218+      port.
219+ ------------------------------------------------------------------------
220\ No newline at end of file
221diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/configure.ac rtems/c/src/lib/libbsp/bfin/TLL6527M/configure.ac
222*** rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/configure.ac    1969-12-31 19:00:00.000000000 -0500
223--- rtems/c/src/lib/libbsp/bfin/TLL6527M/configure.ac   2011-03-15 16:59:39.000000000 -0400
224***************
225*** 0 ****
226--- 1,47 ----
227+ ## Process this file with autoconf to produce a configure script.
228+ ##
229+ ## $Id: configure.ac 36 2011-03-15 20:59:39Z rkangral $
230+
231+ AC_PREREQ(2.68)
232+ AC_INIT([rtems-c-src-lib-libbsp-bfin-TLL6527M],[_RTEMS_VERSION],[http://www.rtems.org/bugzilla])
233+ AC_CONFIG_SRCDIR([bsp_specs])
234+ RTEMS_TOP(../../../../../..)
235+
236+ RTEMS_CANONICAL_TARGET_CPU
237+ AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.11.1])
238+ RTEMS_BSP_CONFIGURE
239+
240+ RTEMS_PROG_CC_FOR_TARGET
241+ RTEMS_CANONICALIZE_TOOLS
242+ RTEMS_PROG_CCAS
243+
244+ ## bsp-specific options
245+ RTEMS_BSPOPTS_SET([CONSOLE_USE_INTERRUPTS],[*],[1])
246+ RTEMS_BSPOPTS_HELP([CONSOLE_USE_INTERRUPTS],
247+ [The console driver can operate in either polled or interrupt mode.])
248+
249+ RTEMS_BSPOPTS_SET([UART_USE_DMA],[*],[1])
250+ RTEMS_BSPOPTS_HELP([UART_USE_DMA],
251+ [The uart driver can operate in dma mode with interrupts.
252+ Set to 1 if DMA operation is required ])
253+
254+ RTEMS_BSPOPTS_SET([CONSOLE_BAUDRATE],[*],[9600])
255+ RTEMS_BSPOPTS_HELP([CONSOLE_BAUDRATE],
256+ [The baudrate of the console uart.])
257+
258+ RTEMS_BSPOPTS_SET([INTERRUPT_USE_TABLE],[*],[1])
259+ RTEMS_BSPOPTS_HELP([INTERRUPT_USE_TABLE],
260+ [Select if INTERRUPT use table or link list])
261+
262+
263+
264+ RTEMS_BSPOPTS_SET([BFIN_ON_SKYEYE],[*],[0])
265+ RTEMS_BSPOPTS_HELP([BFIN_ON_SKYEYE],
266+ [(BSP--Skyeye)
267+  If defined, disable features which are not supported on Skyeye.])
268+
269+ RTEMS_BSP_CLEANUP_OPTIONS(0, 0)
270+
271+ # Explicitly list all Makefiles here
272+ AC_CONFIG_FILES([Makefile])
273+ AC_OUTPUT
274diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/console/console.c rtems/c/src/lib/libbsp/bfin/TLL6527M/console/console.c
275*** rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/console/console.c       1969-12-31 19:00:00.000000000 -0500
276--- rtems/c/src/lib/libbsp/bfin/TLL6527M/console/console.c      2011-04-19 11:00:07.000000000 -0400
277***************
278*** 0 ****
279--- 1,182 ----
280+ /**
281+  *@file console.c
282+  *
283+  *@brief
284+  *  - This file implements uart console for TLL6527M. TLL6527M has BF527 with
285+  *  second uart (uart-1) connected to the console.
286+  *
287+  * Target:   TLL6527v1-0
288+  * Compiler:
289+  *
290+  * COPYRIGHT (c) 2010 by ECE Northeastern University.
291+  *
292+  * The license and distribution terms for this file may be
293+  * found in the file LICENSE in this distribution or at
294+  * http://www.rtems.com/license
295+  *
296+  * @author Rohan Kangralkar, ECE, Northeastern University
297+  *         (kangralkar.r@husky.neu.edu)
298+  *
299+  * LastChange:
300+  * $Id: console.c 48 2011-04-19 15:00:07Z rkangral $
301+  *
302+  */
303+
304+ #include <rtems.h>
305+ #include <rtems/libio.h>
306+ #include <bsp.h>
307+ #include <rtems/bspIo.h>
308+
309+ #include <bsp/interrupt.h>
310+ #include <libcpu/uart.h>
311+
312+ /***************************************************
313+ LOCAL DEFINES
314+  ***************************************************/
315+
316+
317+ /***************************************************
318+ STATIC GLOBALS
319+  ***************************************************/
320+ /**
321+  * Declaration of UART
322+  */
323+ static bfin_uart_channel_t channels[] = {
324+   {"/dev/console",
325+     UART1_BASE_ADDRESS,
326+     DMA10_BASE_ADDRESS,
327+     DMA11_BASE_ADDRESS,
328+     CONSOLE_USE_INTERRUPTS,
329+     UART_USE_DMA,
330+     CONSOLE_BAUDRATE,
331+     NULL,
332+     0,
333+     0}
334+ };
335+
336+ /**
337+  * Over all configuration
338+  */
339+ static bfin_uart_config_t config = {
340+     SCLK,
341+     sizeof(channels) / sizeof(channels[0]),
342+     channels
343+ };
344+
345+
346+ #if CONSOLE_USE_INTERRUPTS
347+ /**
348+  * The Rx and Tx isr will get the same argument
349+  * The isr will have to find if it was the rx that caused the interrupt or
350+  * the tx
351+  */
352+ static bfin_isr_t bfinUARTISRs[] = {
353+ #if UART_USE_DMA
354+     /* For First uart */
355+     {IRQ_DMA10_UART1_RX, bfinUart_rxDmaIsr, (void *)&channels[0], 0},
356+     {IRQ_DMA11_UART1_TX, bfinUart_txDmaIsr, (void *)&channels[0], 0},
357+     /* For second uart */
358+ #else
359+     /* For First uart */
360+     {IRQ_DMA10_UART1_RX, bfinUart_rxIsr, &channels[0], 0},
361+     {IRQ_DMA11_UART1_TX, bfinUart_txIsr, &channels[0], 0},
362+     /* For second uart */
363+ #endif
364+ };
365+ #endif
366+
367+
368+ static void TLL6527_BSP_output_char(char c) {
369+
370+   bfin_uart_poll_write(0, c);
371+ }
372+
373+ static int TLL6527_BSP_poll_char(void) {
374+
375+   return bfin_uart_poll_read(0);
376+ }
377+
378+ BSP_output_char_function_type     BSP_output_char = TLL6527_BSP_output_char;
379+ BSP_polling_getchar_function_type BSP_poll_char   = TLL6527_BSP_poll_char;
380+
381+
382+
383+ rtems_device_driver console_close(rtems_device_major_number major,
384+     rtems_device_minor_number minor,
385+     void *arg) {
386+
387+   return rtems_termios_close(arg);
388+ }
389+
390+ rtems_device_driver console_read(rtems_device_major_number major,
391+     rtems_device_minor_number minor,
392+     void *arg) {
393+
394+   return rtems_termios_read(arg);
395+ }
396+
397+ rtems_device_driver console_write(rtems_device_major_number major,
398+     rtems_device_minor_number minor,
399+     void *arg) {
400+
401+   return rtems_termios_write(arg);
402+ }
403+
404+ rtems_device_driver console_control(rtems_device_major_number major,
405+     rtems_device_minor_number minor,
406+     void *arg) {
407+
408+   return rtems_termios_ioctl(arg);
409+ }
410+
411+
412+
413+ /*
414+  *  Open entry point
415+  */
416+ rtems_device_driver console_open(rtems_device_major_number major,
417+     rtems_device_minor_number minor,
418+     void *arg) {
419+
420+   return bfin_uart_open(major, minor, arg);
421+ }
422+
423+
424+
425+ /**
426+  *
427+  * This routine initializes the console IO driver.
428+  *
429+  * Parameters
430+  * @param major major number
431+  * @param minor minor number
432+  *
433+  * Output parameters:  NONE
434+  *
435+  * @return void
436+  */
437+ rtems_device_driver console_initialize(rtems_device_major_number major,
438+     rtems_device_minor_number minor,
439+     void *arg) {
440+   rtems_status_code status = RTEMS_NOT_DEFINED;
441+ #if CONSOLE_USE_INTERRUPTS
442+   int               i      = 0;
443+ #endif
444+
445+   status = bfin_uart_initialize(major, &config);
446+   if (status != RTEMS_SUCCESSFUL) {
447+     rtems_fatal_error_occurred(status);
448+   }
449+
450+ #if CONSOLE_USE_INTERRUPTS
451+   for (i = 0; i < sizeof(bfinUARTISRs) / sizeof(bfinUARTISRs[0]); i++) {
452+     bfin_interrupt_register(&bfinUARTISRs[i]);
453+ #if INTERRUPT_USE_TABLE
454+ #else
455+     bfin_interrupt_enable(&bfinUARTISRs[i], 1);
456+ #endif
457+   }
458+ #endif
459+
460+   return RTEMS_SUCCESSFUL;
461+ }
462diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/include/bsp.h rtems/c/src/lib/libbsp/bfin/TLL6527M/include/bsp.h
463*** rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/include/bsp.h   1969-12-31 19:00:00.000000000 -0500
464--- rtems/c/src/lib/libbsp/bfin/TLL6527M/include/bsp.h  2011-04-19 11:00:07.000000000 -0400
465***************
466*** 0 ****
467--- 1,79 ----
468+ /**
469+  *@file bsp.h
470+  * 
471+  *  This include file contains all board IO definitions for TLL6527M.
472+  *
473+  * COPYRIGHT (c) 2010 by ECE Northeastern University.
474+  *
475+  * The license and distribution terms for this file may be
476+  * found in the file LICENSE in this distribution or at
477+  * http://www.rtems.com/license
478+  *
479+  *  $Id: bsp.h 48 2011-04-19 15:00:07Z rkangral $
480+  */
481
482+
483+ #ifndef _BSP_H
484+ #define _BSP_H
485+
486+
487+ #ifdef __cplusplus
488+ extern "C" {
489+ #endif
490+
491+ #include <bspopts.h>
492+
493+ #include <rtems.h>
494+ #include <rtems/console.h>
495+ #include <rtems/clockdrv.h>
496+ #include <rtems/score/bfin.h>
497+ #include <rtems/bfin/bf52x.h>
498+ #include <bf52x.h>
499+
500+
501+ /*
502+  * PLL and clock setup values:
503+  */
504+
505+ /*
506+  *  PLL configuration for TLL6527M
507+  *
508+  *  XTL   =  27 MHz
509+  *  CLKIN =  13 MHz
510+  *  VCO   = 391 MHz
511+  *  CCLK  = 391 MHz
512+  *  SCLK  = 130 MHz
513+  */
514+
515+ #define PLL_CSEL    0x0000      /* CCLK = VCO      */
516+ #define PLL_SSEL    0x0003      /* SCLK = CCLK/3   */
517+ #define PLL_MSEL    0x3A00      /* VCO = 29xCLKIN  */
518+ #define PLL_DF      0x0001      /* CLKIN = XTL/2   */
519+
520+ #define CLKIN             (25000000)  /* Input clock to the PLL */
521+ #define CCLK        (600000000)   /* CORE CLOCK     */
522+ #define SCLK        (100000000)   /* SYSTEM CLOCK   */
523+
524+ /*
525+  * UART setup values
526+  */
527+ #define BAUDRATE    57600       /* Console Baudrate   */
528+ #define WORD_5BITS  0x00        /* 5 bits word        */
529+ #define WORD_6BITS  0x01        /* 6 bits word        */
530+ #define WORD_7BITS  0x02        /* 7 bits word        */
531+ #define WORD_8BITS  0x03        /* 8 bits word        */
532+ #define EVEN_PARITY 0x18        /* Enable EVEN parity */
533+ #define ODD_PARITY  0x08        /* Enable ODD parity  */
534+ #define TWO_STP_BIT 0x04        /* 2 stop bits        */
535+
536+ rtems_isr_entry set_vector(                     /* returns old vector */
537+   rtems_isr_entry     handler,                  /* isr routine        */
538+   rtems_vector_number vector,                   /* vector number      */
539+   int                 type                      /* RTEMS or RAW intr  */
540+ );
541+
542+ #ifdef __cplusplus
543+ }
544+ #endif
545+
546+ #endif
547diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/include/cplb.h rtems/c/src/lib/libbsp/bfin/TLL6527M/include/cplb.h
548*** rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/include/cplb.h  1969-12-31 19:00:00.000000000 -0500
549--- rtems/c/src/lib/libbsp/bfin/TLL6527M/include/cplb.h 2011-02-25 15:46:42.000000000 -0500
550***************
551*** 0 ****
552--- 1,34 ----
553+ /*  cplb.h
554+  * 
555+  *  Copyright (c) 2006 by Atos Automacao Industrial Ltda.
556+  *             written by Alain Schaefer <alain.schaefer@easc.ch>
557+  *
558+  *  The license and distribution terms for this file may be
559+  *  found in the file LICENSE in this distribution or at
560+  *  http://www.rtems.com/license/LICENSE.
561+  *
562+  *  $Id: cplb.h 27 2011-02-25 20:46:42Z rkangral $
563+  */
564+ #ifndef _CPLB_H
565+ #define _CPLB_H
566+
567+ /* CPLB configurations */
568+ #define CPLB_DEF_CACHE_WT     CPLB_L1_CHBL | CPLB_WT
569+ #define CPLB_DEF_CACHE_WB     CPLB_L1_CHBL
570+ #define CPLB_CACHE_ENABLED    CPLB_L1_CHBL | CPLB_DIRTY
571+
572+ #define CPLB_DEF_CACHE                CPLB_L1_CHBL | CPLB_WT
573+ #define CPLB_ALL_ACCESS       CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
574+
575+ #define CPLB_I_PAGE_MGMT      CPLB_LOCK | CPLB_VALID
576+ #define CPLB_D_PAGE_MGMT      CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
577+
578+ #define CPLB_DNOCACHE         CPLB_ALL_ACCESS | CPLB_VALID
579+ #define CPLB_DDOCACHE         CPLB_DNOCACHE | CPLB_DEF_CACHE
580+ #define CPLB_INOCACHE         CPLB_USER_RD | CPLB_VALID
581+ #define CPLB_IDOCACHE         CPLB_INOCACHE | CPLB_L1_CHBL
582+
583+ #define CPLB_DDOCACHE_WT      CPLB_DNOCACHE | CPLB_DEF_CACHE_WT
584+ #define CPLB_DDOCACHE_WB      CPLB_DNOCACHE | CPLB_DEF_CACHE_WB
585+
586+ #endif /* _CPLB_H */
587diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/include/tm27.h rtems/c/src/lib/libbsp/bfin/TLL6527M/include/tm27.h
588*** rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/include/tm27.h  1969-12-31 19:00:00.000000000 -0500
589--- rtems/c/src/lib/libbsp/bfin/TLL6527M/include/tm27.h 2011-04-19 11:00:07.000000000 -0400
590***************
591*** 0 ****
592--- 1,37 ----
593+ /*
594+  *  tm27.h
595+  *
596+  * COPYRIGHT (c) 2010 by ECE Northeastern University.
597+  *
598+  * The license and distribution terms for this file may be
599+  * found in the file LICENSE in this distribution or at
600+  * http://www.rtems.com/license
601+  *
602+  *  $Id: tm27.h 48 2011-04-19 15:00:07Z rkangral $
603+  */
604+
605+ #ifndef _RTEMS_TMTEST27
606+ #error "This is an RTEMS internal file you must not include directly."
607+ #endif
608+
609+ #ifndef __tm27_h
610+ #define __tm27_h
611+
612+ /*
613+  *  Define the interrupt mechanism for Time Test 27
614+  */
615+
616+ #define MUST_WAIT_FOR_INTERRUPT 0
617+
618+ #define Install_tm27_vector(handler) \
619+ { \
620+   set_vector( handler, 0x06, 1 ); \
621+ }
622+
623+ #define Cause_tm27_intr() asm volatile("raise 0x06;" : :);
624+
625+ #define Clear_tm27_intr() /* empty */
626+
627+ #define Lower_tm27_intr() /* empty */
628+
629+ #endif
630diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/make/custom/TLL6527M.cfg rtems/c/src/lib/libbsp/bfin/TLL6527M/make/custom/TLL6527M.cfg
631*** rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/make/custom/TLL6527M.cfg        1969-12-31 19:00:00.000000000 -0500
632--- rtems/c/src/lib/libbsp/bfin/TLL6527M/make/custom/TLL6527M.cfg       2011-02-25 15:55:50.000000000 -0500
633***************
634*** 0 ****
635--- 1,19 ----
636+ #
637+ #  Config file for Blackfin TLL6527M
638+ #
639+ #  $Id: TLL6527M.cfg 29 2011-02-25 20:55:50Z rkangral $
640+ #
641+
642+ include $(RTEMS_ROOT)/make/custom/default.cfg
643+
644+ RTEMS_CPU=bfin
645+ RTEMS_CPU_MODEL=bf52x
646+
647+ #  This contains the compiler options necessary to select the CPU model
648+ #  and (hopefully) optimize for it.
649+ #
650+ CPU_CFLAGS =-mcpu=bf527
651+
652+ # optimize flag: typically -O2
653+ # gcc-4.2.0 segfaults on -OX > -O0
654+ CFLAGS_OPTIMIZE_V = -O2 -g
655diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/Makefile.am rtems/c/src/lib/libbsp/bfin/TLL6527M/Makefile.am
656*** rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/Makefile.am     1969-12-31 19:00:00.000000000 -0500
657--- rtems/c/src/lib/libbsp/bfin/TLL6527M/Makefile.am    2011-04-19 11:00:07.000000000 -0400
658***************
659*** 0 ****
660--- 1,52 ----
661+ ##
662+ ## $Id: Makefile.am 48 2011-04-19 15:00:07Z rkangral $
663+ ##
664+
665+ ACLOCAL_AMFLAGS = -I ../../../../aclocal
666+
667+ include $(top_srcdir)/../../../../automake/compile.am
668+
669+ include_bspdir = $(includedir)/bsp
670+
671+ dist_project_lib_DATA = bsp_specs
672+
673+ include_HEADERS = include/bsp.h
674+ include_HEADERS += include/tm27.h
675+ include_HEADERS += include/cplb.h
676+
677+ nodist_include_HEADERS = include/bspopts.h
678+ nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
679+ DISTCLEANFILES = include/bspopts.h
680+
681+ noinst_PROGRAMS =
682+
683+ include_HEADERS += ../../shared/include/coverhd.h
684+
685+ noinst_LIBRARIES = libbspstart.a
686+ libbspstart_a_SOURCES = ../shared/start/start.S
687+ project_lib_DATA = start.$(OBJEXT)
688+
689+ dist_project_lib_DATA += startup/linkcmds
690+
691+ noinst_LIBRARIES += libbsp.a
692+
693+ libbsp_a_SOURCES = ../../shared/bsplibc.c ../../shared/bsppost.c \
694+   ../../shared/bsppredriverhook.c startup/bspstart.c \
695+   ../../shared/bspclean.c ../../shared/sbrk.c ../../shared/setvec.c \
696+   ../../shared/bootcard.c ../../shared/gnatinstallhandler.c \
697+   ../../shared/bspgetworkarea.c
698+
699+ libbsp_a_SOURCES += console/console.c
700+
701+ libbsp_a_LIBADD  = ../../../libcpu/@RTEMS_CPU@/mmu.rel
702+ libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/interrupt.rel
703+ libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/cache.rel
704+ libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/uart.rel
705+ libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/clock.rel
706+ libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/rtc.rel
707+ libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/timer.rel
708+
709+ EXTRA_DIST = times
710+
711+ include $(srcdir)/preinstall.am
712+ include $(top_srcdir)/../../../../automake/local.am
713diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/preinstall.am rtems/c/src/lib/libbsp/bfin/TLL6527M/preinstall.am
714*** rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/preinstall.am   1969-12-31 19:00:00.000000000 -0500
715--- rtems/c/src/lib/libbsp/bfin/TLL6527M/preinstall.am  2011-02-25 15:53:20.000000000 -0500
716***************
717*** 0 ****
718--- 1,71 ----
719+ ## Automatically generated by ampolish3 - Do not edit
720+
721+ if AMPOLISH3
722+ $(srcdir)/preinstall.am: Makefile.am
723+       $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
724+ endif
725+
726+ PREINSTALL_DIRS =
727+ DISTCLEANFILES += $(PREINSTALL_DIRS)
728+
729+ all-local: $(TMPINSTALL_FILES)
730+
731+ TMPINSTALL_FILES =
732+ CLEANFILES = $(TMPINSTALL_FILES)
733+
734+ all-am: $(PREINSTALL_FILES)
735+
736+ PREINSTALL_FILES =
737+ CLEANFILES += $(PREINSTALL_FILES)
738+
739+ $(PROJECT_LIB)/$(dirstamp):
740+       @$(MKDIR_P) $(PROJECT_LIB)
741+       @: > $(PROJECT_LIB)/$(dirstamp)
742+ PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp)
743+
744+ $(PROJECT_INCLUDE)/$(dirstamp):
745+       @$(MKDIR_P) $(PROJECT_INCLUDE)
746+       @: > $(PROJECT_INCLUDE)/$(dirstamp)
747+ PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
748+
749+ $(PROJECT_INCLUDE)/bsp/$(dirstamp):
750+       @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp
751+       @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp)
752+ PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp)
753+
754+ $(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp)
755+       $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs
756+ PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs
757+
758+ $(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp)
759+       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h
760+ PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h
761+
762+ $(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
763+       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
764+ PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
765+
766+ $(PROJECT_INCLUDE)/cplb.h: include/cplb.h $(PROJECT_INCLUDE)/$(dirstamp)
767+       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/cplb.h
768+ PREINSTALL_FILES += $(PROJECT_INCLUDE)/cplb.h
769+
770+ $(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
771+       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
772+ PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h
773+
774+ $(PROJECT_INCLUDE)/bsp/bootcard.h: ../../shared/include/bootcard.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
775+       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bootcard.h
776+ PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bootcard.h
777+
778+ $(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp)
779+       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h
780+ PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h
781+
782+ $(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
783+       $(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT)
784+ TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT)
785+
786+ $(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp)
787+       $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds
788+ PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds
789+
790diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/README rtems/c/src/lib/libbsp/bfin/TLL6527M/README
791*** rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/README  1969-12-31 19:00:00.000000000 -0500
792--- rtems/c/src/lib/libbsp/bfin/TLL6527M/README 2011-03-15 16:59:39.000000000 -0400
793***************
794*** 0 ****
795--- 1,96 ----
796+ #
797+ #  $Id: README 36 2011-03-15 20:59:39Z rkangral $
798+ #
799+
800+ BSP NAME:           TLL6527M
801+ BOARD:              TLL6527M
802+ CPU FAMILY:         Blackfin
803+ CPU:                Blackfin 527
804+ MODE:               32 bit mode
805+
806+ DEBUG MONITOR:     
807+ SIMULATOR:         
808+
809+ PERIPHERALS
810+ ===========
811+ TIMERS:             internal
812+   RESOLUTION:         1 milisecond
813+ SERIAL PORTS:       2 internal UART (polled/interrupt/dma)
814+ REAL-TIME CLOCK:    internal
815+ DMA:                internal
816+ VIDEO:              none
817+ SCSI:               none
818+ NETWORKING:         none
819+
820+
821+ DRIVER INFORMATION
822+ ==================
823+ CLOCK DRIVER:       internal
824+ TIMER DRIVER:       internal
825+ I2C:
826+ SPI:
827+ PPI:
828+ SPORT:
829+
830+
831+ STDIO
832+ =====
833+ PORT:               Console port 1
834+ ELECTRICAL:         RS-232
835+ BAUD:               9600
836+ BITS PER CHARACTER: 8
837+ PARITY:             None
838+ STOP BITS:          1
839+
840+ NOTES
841+ =====
842+ The TLL56527M board contains analog devices blackfin 527 processor. In addition
843+ to the peripherals provided by bf527 the board has a temprature sensor,
844+ accelerometer and power module connected via I2C. It also has LCD interface,
845+ Card reader interface.
846+
847+ The analog device bf52X family of processors are different from the bf53x range
848+ of processors. This port supports the additional features that are not
849+ supported by the blackfin 53X family of processors.
850+   
851+ The TLL6527M does not use the interrupt module used by the bfin 53x since it has
852+ an additional system interrupt controller isr registers for additional lines.
853+ On the 53X these line are multiplexed.
854+ The centralized interrupt handler is implemented to use lookup tables for
855+ jumping to the user ISR. For more details look at files implemented under
856+ libcpu/bfin/bf52x/interrupt/*
857+
858+ This port supports only the uart peripheral. The uart is supported via
859+ polling, DMA, interrupt. The uart file is generic and is common between the
860+ ports. Under bsp configure.ac files
861+ * change the CONSOLE_BAUDRATE or to choose among different baudrate.
862+ * Set UART_USE_DMA for UART to use DMA based transfers. In DMA based transfer
863+   chunk of buffer is transmitted at once and then an interrupt is generated.
864+ * Set CONSOLE_USE_INTERRUPTS to use interrupt based transfers. After every
865+   character is transmitted an interrupt is generated.
866+ * If CONSOLE_USE_INTERRUPTS, UART_USE_DMA are both not set then the port uses
867+   polling to transmit data over uart. This call is blocking.
868+
869+ TLL6527 specific file are mentioned below.
870+ =====================================
871+ c/src/lib/libcpu/bfin/bf52x/*
872+ c/src/lib/libbsp/bfin/TLL6527M/*
873+
874+
875+ The port was compiled using
876+ ===========================
877+ 1. bfin-rtems4.11-gcc (GCC) 4.5.2 20101216
878+               (RTEMS gcc-4.5.2-3.el5/newlib-1.19.0-1.el5)
879+ 2. automake (GNU automake) 1.11.1
880+ 3. autoconf (GNU Autoconf) 2.68
881+
882+
883+ The port was configured using the flags
884+ ==========================================
885+ --target=bfin-rtems4.11 --enable-rtemsbsp=TLL6527M --enable-tests=samples
886+ --disable-posix --disable-itron
887+       
888+
889+ ISSUES:
890+ Could not place code in l1code (SRAM) because it was not being loaded by the
891+ gnu loaded.
892\ No newline at end of file
893diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/startup/bspstart.c rtems/c/src/lib/libbsp/bfin/TLL6527M/startup/bspstart.c
894*** rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/startup/bspstart.c      1969-12-31 19:00:00.000000000 -0500
895--- rtems/c/src/lib/libbsp/bfin/TLL6527M/startup/bspstart.c     2011-04-19 11:00:07.000000000 -0400
896***************
897*** 0 ****
898--- 1,207 ----
899+ /*  bspstart.c for TLL6527M
900+  *
901+  *  This routine starts the application.  It includes application,
902+  *  board, and monitor specific initialization and configuration.
903+  *  The generic CPU dependent initialization has been performed
904+  *  before this routine is invoked.
905+  * 
906+  * COPYRIGHT (c) 2010 by ECE Northeastern University.
907+  *
908+  * The license and distribution terms for this file may be
909+  * found in the file LICENSE in this distribution or at
910+  * http://www.rtems.com/license
911+  *
912+  *  $Id: bspstart.c 48 2011-04-19 15:00:07Z rkangral $
913+  */
914+
915+
916+ #include <bsp.h>
917+ #include <cplb.h>
918+ #include <bsp/interrupt.h>
919+ #include <libcpu/ebiuRegs.h>
920+
921+ const unsigned int dcplbs_table[16][2] = { 
922+   { 0xFFA00000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },
923+   { 0xFF900000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },/* L1 Data B */
924+   { 0xFF800000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },/* L1 Data A */
925+   { 0xFFB00000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },
926+
927+   { 0x20300000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },/* Async Memory Bank 3 */
928+   { 0x20200000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },/* Async Memory Bank 2  */
929+   { 0x20100000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },/* Async Memory Bank 1 */
930+   { 0x20000000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) }, /* Async Memory Bank 0 */
931+
932+   { 0x02400000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
933+   { 0x02000000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
934+   { 0x00C00000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
935+   { 0x00800000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
936+   { 0x00400000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
937+   { 0x00000000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
938+
939+   { 0xffffffff, 0xffffffff }/* end of section - termination */
940+ };
941+
942+
943+ const unsigned int _icplbs_table[16][2] = {
944+   { 0xFFA00000, (PAGE_SIZE_1MB | CPLB_I_PAGE_MGMT | CPLB_I_PAGE_MGMT | 0x4) },
945+   /* L1 Code */
946+   { 0xEF000000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, /* AREA DE BOOT */
947+   { 0xFFB00000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },
948+
949+   { 0x20300000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Memory Bank 3 */
950+   { 0x20200000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Bank 2 (Secnd) */
951+   { 0x20100000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Bank 1 (Prim B) */
952+   { 0x20000000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Bank 0 (Prim A) */
953+
954+   { 0x02400000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
955+   { 0x02000000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
956+   { 0x00C00000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
957+   { 0x00800000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
958+   { 0x00400000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
959+   { 0x00000000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
960+
961+   { 0xffffffff, 0xffffffff }/* end of section - termination */
962+ };
963+
964+ /*
965+  *  Use the shared implementations of the following routines
966+  */
967+
968+ void bsp_libc_init( void *, uint32_t, int );
969+ void Init_PLL (void);
970+ void Init_EBIU (void);
971+ void Init_Flags(void);
972+ void Init_RTC (void);
973+ void initCPLB(void);
974+
975+
976+ void null_isr(void);
977+
978+ /*
979+  *  Function:   bsp_pretasking_hook
980+  *  Created:    95/03/10
981+  *
982+  *  Description:
983+  *      BSP pretasking hook.  Called just before drivers are initialized.
984+  *      Used to setup libc and install any BSP extensions.
985+  *
986+  *  NOTES:
987+  *      Must not use libc (to do io) from here, since drivers are
988+  *      not yet initialized.
989+  *
990+  */
991+
992+ void bsp_pretasking_hook(void)
993+ {
994+   bfin_interrupt_init();
995+ }
996+
997+ /*
998+  *  bsp_start
999+  *
1000+  *  This routine does the bulk of the system initialization.
1001+  */
1002+
1003+ void bsp_start( void )
1004+ {
1005+   /* BSP Hardware Initialization*/
1006+   Init_RTC();   /* Blackfin Real Time Clock initialization */ 
1007+   Init_PLL();   /* PLL initialization */
1008+   Init_EBIU();  /* EBIU initialization */
1009+   Init_Flags(); /* GPIO initialization */
1010+
1011+   /*
1012+    *  Allocate the memory for the RTEMS Work Space.  This can come from
1013+    *  a variety of places: hard coded address, malloc'ed from outside
1014+    *  RTEMS world (e.g. simulator or primitive memory manager), or (as
1015+    *  typically done by stock BSPs) by subtracting the required amount
1016+    *  of work space from the last physical address on the CPU board.
1017+    */
1018+   int i=0;
1019+   for (i=5;i<16;i++) {
1020+     set_vector((rtems_isr_entry)null_isr, i, 1);
1021+   }
1022+   
1023+ }
1024+
1025+  /*
1026+   * Init_PLL
1027+   *
1028+   * Routine to initialize the PLL. The TLL6527M uses a 25 Mhz XTAL.
1029+   */
1030+ void Init_PLL (void)
1031+ {
1032+   unsigned short msel = 0;
1033+   unsigned short ssel = 0;
1034+
1035+   msel = (unsigned short)( (float)CCLK/(float)CLKIN );
1036+   ssel = (unsigned short)( (float)(CLKIN*msel)/(float)SCLK);
1037+   
1038+   asm("cli r0;");
1039+
1040+   *((uint32_t*)SIC_IWR) = 0x1;
1041+
1042+   /* Configure PLL registers */
1043+   *((uint16_t*)PLL_DIV) = ssel;;
1044+   msel = msel<<9;
1045+   *((uint16_t*)PLL_CTL) = msel;
1046+
1047+   /* Commands to set PLL values */
1048+   asm("idle;");
1049+   asm("sti r0;");
1050+ }
1051+
1052+  /*
1053+   * Init_EBIU
1054+   *
1055+   * Configure extern memory
1056+   */
1057+
1058+ void Init_EBIU (void)
1059+ {
1060+   /* Check if SDRAM is already enabled */
1061+   if ( 0 != (*(uint16_t *)EBIU_SDSTAT & EBIU_SDSTAT_SDRS) ){
1062+     asm("ssync;");
1063+     /* RDIV = (100MHz*64ms)/8192-(6+3)=0x406 cycles */
1064+     *(uint16_t *)EBIU_SDRRC  = 0x3F6; /* SHould have been 0x306*/
1065+     *(uint16_t *)EBIU_SDBCTL = EBIU_SDBCTL_EBCAW_10 | EBIU_SDBCTL_EBSZ_64M |
1066+         EBIU_SDBCTL_EBE;
1067+     *(uint32_t *)EBIU_SDGCTL = 0x8491998d;
1068+     asm("ssync;");
1069+   } else {
1070+     /* SDRAm is already programmed */
1071+   }
1072+ }
1073+
1074+  /*
1075+   * Init_Flags
1076+   *
1077+   * Enable LEDs port
1078+   */
1079+ void Init_Flags(void)
1080+ {
1081+   *((uint16_t*)PORTH_FER)    = 0x0;
1082+   *((uint16_t*)PORTH_MUX)    = 0x0;
1083+   *((uint16_t*)PORTHIO_DIR)  = 0x1<<15;
1084+   *((uint16_t*)PORTHIO_SET)  = 0x1<<15;
1085+ }
1086+
1087+
1088+
1089+ void initCPLB(void) {
1090+
1091+        int i = 0;
1092+        unsigned int *addr;
1093+        unsigned int *data;
1094+         
1095+        addr = (unsigned int *)0xffe00100;
1096+        data = (unsigned int *)0xffe00200;
1097+
1098+        while ( dcplbs_table[i][0] != 0xffffffff ) {
1099+                *addr = dcplbs_table[i][0];
1100+                *data = dcplbs_table[i][1];
1101+
1102+                addr++;
1103+                data++;
1104+        }
1105+ }
1106diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/startup/linkcmds rtems/c/src/lib/libbsp/bfin/TLL6527M/startup/linkcmds
1107*** rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/startup/linkcmds        1969-12-31 19:00:00.000000000 -0500
1108--- rtems/c/src/lib/libbsp/bfin/TLL6527M/startup/linkcmds       2011-04-12 18:05:09.000000000 -0400
1109***************
1110*** 0 ****
1111--- 1,154 ----
1112+ OUTPUT_FORMAT("elf32-bfin", "elf32-bfin",
1113+             "elf32-bfin")
1114+
1115+ OUTPUT_ARCH(bfin)
1116+ ENTRY(__start)
1117+
1118+ /*
1119+  * Declare some sizes.
1120+  */
1121+ _RamBase    = DEFINED(_RamBase)   ? _RamBase : 0x0;
1122+ _RamSize    = DEFINED(_RamSize)   ? _RamSize : 0x04000000;
1123+ _HeapSize   = DEFINED(_HeapSize)  ? _HeapSize : 0x10000;
1124+ _StackSize  = DEFINED(_StackSize) ? _StackSize : 0x10000;
1125+
1126+ MEMORY
1127+ {
1128+       sdram(rwx)      : ORIGIN = 0x00000100, LENGTH = 0x04000000
1129+       
1130+       l1dataA(rwx)    : ORIGIN = 0xff800000, LENGTH = 0x00004000
1131+       l1dataAC(rwx)   : ORIGIN = 0xff804000, LENGTH = 0x00004000
1132+       l1dataB(rwx)    : ORIGIN = 0xff900000, LENGTH = 0x00004000
1133+       l1dataBC(rwx)   : ORIGIN = 0xff904000, LENGTH = 0x00004000
1134+       
1135+       l1code(rwx)     : ORIGIN = 0xffa00000, LENGTH = 0x0000C000
1136+       l1codeC(rwx)    : ORIGIN = 0xffa10000, LENGTH = 0x00004000
1137+       scratchpad(rwx) : ORIGIN = 0xffb00000, LENGTH = 0x00001000
1138+ }
1139+
1140+ SECTIONS
1141+ {
1142+
1143+     .init          :
1144+     {
1145+       *(.l1code)
1146+         KEEP (*(.init))
1147+     } > sdram   /*=0*/
1148+
1149+     .text :
1150+     {
1151+          CREATE_OBJECT_SYMBOLS
1152+         *(.text)
1153+         *(.rodata*)
1154+         *(.gnu.linkonce.r*)
1155+         
1156+         /*
1157+          * Special FreeBSD sysctl sections.
1158+          */
1159+         . = ALIGN (16);
1160+         ___start_set_sysctl_set = .;
1161+         *(set_sysctl_*);
1162+         ___stop_set_sysctl_set = ABSOLUTE(.);
1163+         *(set_domain_*);
1164+         *(set_pseudo_*);
1165+
1166+          _etext = .;
1167+
1168+         ___CTOR_LIST__ = .;
1169+         LONG((___CTOR_END__ - ___CTOR_LIST__) / 4 - 2)
1170+         *(.ctors)
1171+         LONG(0)
1172+         ___CTOR_END__ = .;
1173+         ___DTOR_LIST__ = .;
1174+         LONG((___DTOR_END__ - ___DTOR_LIST__) / 4 - 2)
1175+         *(.dtors)
1176+         LONG(0)
1177+         ___DTOR_END__ = .;         
1178+     } > sdram
1179+     
1180+     .fini :
1181+     {
1182+         KEEP (*(.fini))
1183+     } > sdram  /*=0*/
1184+     
1185+     .data :
1186+     {
1187+         *(.data)
1188+         *(.jcr)
1189+         *(.gnu.linkonce.d*)
1190+         CONSTRUCTORS
1191+          _edata = .;
1192+     } > sdram
1193+
1194+     .eh_frame : { *(.eh_frame) } > sdram
1195+     .data1   : { *(.data1) } > sdram
1196+     .eh_frame : { *(.eh_frame) } > sdram
1197+     .gcc_except_table : { *(.gcc_except_table*) } > sdram
1198+
1199+     .rodata :
1200+     {
1201+         *(.rodata)
1202+         *(.rodata.*)
1203+         *(.gnu.linkonce.r*)
1204+     } > sdram
1205+
1206+     
1207+     .bss :
1208+     {
1209+          _bss_start = .;
1210+         _clear_start = .;
1211+         *(.bss)
1212+         *(.gnu.linkonce.b.*)
1213+         *(COMMON)
1214+         . = ALIGN (64);
1215+         _stack_init = .;
1216+         . += _StackSize;
1217+         _clear_end = .;
1218+         _WorkAreaBase = .;
1219+          _end = .;
1220+          __end = .;
1221+     } > sdram
1222+     
1223+ /* Debugging stuff follows */
1224+
1225+   /* Stabs debugging sections.  */
1226+   .stab 0 : { *(.stab) }
1227+   .stabstr 0 : { *(.stabstr) }
1228+   .stab.excl 0 : { *(.stab.excl) }
1229+   .stab.exclstr 0 : { *(.stab.exclstr) }
1230+   .stab.index 0 : { *(.stab.index) }
1231+   .stab.indexstr 0 : { *(.stab.indexstr) }
1232+   .comment 0 : { *(.comment) }
1233+   /* DWARF debug sections.
1234+      Symbols in the DWARF debugging sections are relative to the beginning
1235+      of the section so we begin them at 0.  */
1236+   /* DWARF 1 */
1237+   .debug          0 : { *(.debug) }
1238+   .line           0 : { *(.line) }
1239+   /* GNU DWARF 1 extensions */
1240+   .debug_srcinfo  0 : { *(.debug_srcinfo) }
1241+   .debug_sfnames  0 : { *(.debug_sfnames) }
1242+   /* DWARF 1.1 and DWARF 2 */
1243+   .debug_aranges  0 : { *(.debug_aranges) }
1244+   .debug_pubnames 0 : { *(.debug_pubnames) }
1245+   /* DWARF 2 */
1246+   .debug_info     0 : { *(.debug_info) }
1247+   .debug_abbrev   0 : { *(.debug_abbrev) }
1248+   .debug_line     0 : { *(.debug_line) }
1249+   .debug_frame    0 : { *(.debug_frame) }
1250+   .debug_str      0 : { *(.debug_str) }
1251+   .debug_loc      0 : { *(.debug_loc) }
1252+   .debug_macinfo  0 : { *(.debug_macinfo) }
1253+   /* SGI/MIPS DWARF 2 extensions */
1254+   .debug_weaknames 0 : { *(.debug_weaknames) }
1255+   .debug_funcnames 0 : { *(.debug_funcnames) }
1256+   .debug_typenames 0 : { *(.debug_typenames) }
1257+   .debug_varnames  0 : { *(.debug_varnames) }
1258+   /*.stack 0x80000 : { _stack = .; *(.stack) }*/
1259+   /* These must appear regardless of  .  */   
1260+ }
1261+
1262+ __HeapSize = _HeapSize;
1263+ __edata = _edata;
1264+ __etext = _etext;
1265+
1266diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/times rtems/c/src/lib/libbsp/bfin/TLL6527M/times
1267*** rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/times   1969-12-31 19:00:00.000000000 -0500
1268--- rtems/c/src/lib/libbsp/bfin/TLL6527M/times  2011-04-12 18:05:09.000000000 -0400
1269***************
1270*** 0 ****
1271--- 1,179 ----
1272+ #
1273+ #  Timing Test Suite Results for TLL6527M
1274+ #
1275+ #
1276+ #  $Id: times 46 2011-04-12 22:05:09Z rkangral $
1277+ #
1278+
1279+ Board: TLL6527M
1280+ CPU: Blackfin 527
1281+ Clock Speed: 600 MHz
1282+ Memory Configuration: SDRAM 100 MHz
1283+
1284+
1285+ *** TIME TEST 1 ***
1286+ rtems_semaphore_create 8
1287+ rtems_semaphore_delete 4
1288+ rtems_semaphore_obtain: available 0
1289+ rtems_semaphore_obtain: not available -- NO_WAIT 0
1290+ rtems_semaphore_release: no waiting tasks 1
1291+ *** END OF TEST 1 ***
1292+
1293+
1294+ *** TIME TEST 2 ***
1295+ rtems_semaphore_obtain: not available -- caller blocks 8
1296+ *** END OF TEST 2 ***
1297+
1298+
1299+ *** TIME TEST 3 ***
1300+
1301+ *** TIME TEST 4 ***
1302+
1303+ *** TIME TEST 5 ***
1304+
1305+ *** TIME TEST 6 ***
1306+ rtems_task_restart: calling task 3
1307+ rtems_task_suspend: returns to caller 1
1308+ rtems_task_resume: task readied -- returns to caller 1
1309+ rtems_task_delete: ready task 15
1310+ *** END OF TEST 6 ***
1311+
1312+ *** TIME TEST 7 ***
1313+
1314+
1315+ *** TIME TEST 8 ***
1316+ rtems_task_set_priority: obtain current priorityrtems_task_mode: reschedule -- preempts caller 0   
1317+ rtems_task_set_priority: returns to caller  2
1318+ rtems_task_mode: obtain current mode101 0
1319+ rtems_task_mode: no reschedule 0
1320+ rtems_task_mode: reschedule -- returns to caller
1321+  2
1322+ rtems_task_set_note 1
1323+ rtems_task_get_note 0
1324+ rtems_clock_set 2
1325+ rtems_clock_get_tod 12
1326+ *** END OF TEST 8 ***
1327+
1328+
1329+ *** TIME TEST 9 ***
1330+ rtems_message_queue_create 43
1331+ rtems_message_queue_send: no waiting tasks 2
1332+ rtems_message_queue_urgent: no waiting tasks 2
1333+ rtems_message_queue_receive: available 2
1334+ rtems_message_queue_flush: no messages flushed 0
1335+ rtems_message_queue_flush: messages flushed 1
1336+ rtems_message_queue_delete 8
1337+ *** END OF TEST 9 ***
1338+
1339+ *** TIME TEST 10 ***
1340+ rtems_message_queue_receive: not available -- NO_WAITrtems_message_queue_receive: not available -- caller blocks 1
1341+  8
1342+ *** END OF TEST 10 ***
1343+
1344+ *** TIME TEST 11 ***
1345+
1346+ *** TIME TEST 12 ***
1347+
1348+ *** TIME TEST 13 ***
1349+
1350+ *** TIME TEST 14 ***
1351+
1352+ *** TIME TEST 15 ***
1353+ rtems_event_receive: obtain current eventsrtems_event_receive: not available -- caller blocks  07 
1354+
1355+ rtems_event_receive: not available -- NO_WAITrtems_event_send: n
1356+
1357+
1358+
1359+ *** TIME TEST 16 ***
1360+
1361+ *** TIME TEST 17 ***
1362+     
1363+     
1364+ *** TIME TEST 18 ***
1365+ rtems_task_delete: calling task 22
1366+ *** END OF TEST 18 ***
1367+
1368+
1369+ *** TIME TEST 19 ***
1370+ rtems_signal_catch 1
1371+ rtems_signal_send: returns to caller 2
1372+ rtems_signal_send: signal to self 8
1373+ exi
1374+
1375+
1376+
1377+ *** TIME TEST 20 ***                                                                               
1378+ rtems_partition_create 12                                                                         
1379+ rtems_region_creatertems_region_get_segment: not available -- caller blocks 15
1380+ rtems_partition_get_buffer: available 3
1381+ rtems_partition_get_buffer: not available15 1
1382+ rtems_partition_return_buffer 2
1383+
1384+ rtems_partition_delete 2
1385+ rtems_region_get_segment: available 5rtems_region_return_segment: task readied -- returns to caller
1386+  rtems_region_get_segment: not available -- NO_WAIT 5
1387+ rtems_region_return_segment: no waiting tasks3 4
1388+
1389+ Ack! Something bad happened to the Blackfin!
1390+
1391+ SEQUENCER STATUS:
1392+  SEQSTAT: 0000c021  IPEND: 8068  SYSCFG: 0006
1393+   HWERRCAUSE: 0x3: external memory addressing error
1394+   EXCAUSE   : 0x21: undef inst
1395+   physical IVG6 asserted : <0x00009542> /* unknown address */
1396+   physical IVG15 asserted : <0x00009690> /* unknown address */
1397+  RETE: <0x00000100> /* unknown address */
1398+  RETN: <0x92a330ab> { ___smulsi3_highpart + 0x8ead486f }
1399+  RETX: <0x12001940> { ___smulsi3_highpart + 0xe0a3104 }
1400+  RETS: <0x000095fa> /* unknown address */
1401+  RETI: <0x0d48338c> { ___smulsi3_highpart + 0x9524b50 }
1402+ DCPLB_FAULT_ADDR: <0x000318f0> /* unknown address */
1403+ ICPLB_FAULT_ADDR: <0x12001940> { ___smulsi3_highpart + 0xe0a3104 }
1404
1405
1406+
1407+ *** TIME TEST 21 ***                                                                               
1408+
1409+ rtems_region_create FAILED -- expected (successful completion) got (address specified is invalid)
1410+
1411+ *** TIME TEST 22 ***
1412+
1413+ *** TIME TEST 23 ***
1414+
1415+
1416+ *** TIME TEST 24 ***
1417+     
1418+     
1419+ *** TIME TEST 25 ***
1420+ rtems_clock_tick 5
1421+ *** END OF TEST 25 ***
1422+
1423+
1424+ *** TIME TEST 26 ***
1425+
1426+ *** TIME TEST 27 ***
1427+ interrupt entry overhead: returns to interrupted taskinterrupt entry overhead: returns to preempting task  22
1428+
1429+ interrupt exit overhead: returns to interrupted task
1430+
1431+
1432+ *** TIME TEST 28 ***
1433+ rtems_port_create 1
1434+ rtems_port_external_to_internal 0
1435+ rtems_port_internal_to_external 0
1436+ rtems_port_delete 1
1437+ *** END OF TEST 28 ***
1438+
1439+
1440+ *** TIME TEST 29 ***
1441+ rtems_rate_monotonic_create 6
1442+ rtems_rate_monotonic_period: initiate period -- returns to caller 10
1443+ rtems_rate_monotonic_period: obtain status 2
1444+ rtems_rate_monotonic_cancel 3
1445+ rtems_rate_monotonic_delete: inactive 6
1446+ rtems_rate_monotonic_delete: active 3
1447+ rtems_rate_monotonic_period: conclude periods -- caller blocks 9
1448+ *** END OF TEST 29 ***
1449+
1450+         
1451\ No newline at end of file
1452diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libcpu/bfin/bf52x/include/bf52x.h rtems/c/src/lib/libcpu/bfin/bf52x/include/bf52x.h
1453*** rtems-4.10.0/c/src/lib/libcpu/bfin/bf52x/include/bf52x.h    1969-12-31 19:00:00.000000000 -0500
1454--- rtems/c/src/lib/libcpu/bfin/bf52x/include/bf52x.h   2011-04-19 11:00:07.000000000 -0400
1455***************
1456*** 0 ****
1457--- 1,133 ----
1458+ /**
1459+  *@file bf52x.h
1460+  *
1461+  *@brief
1462+  *  - This file provides the register address for the 52X model. The file is
1463+  *  based on the 533 implementation with some addition to support 52X range of
1464+  *  processors.
1465+  *
1466+  * Target:   TLL6527v1-0
1467+  * Compiler:
1468+  *
1469+  * COPYRIGHT (c) 2010 by ECE Northeastern University.
1470+  *
1471+  * The license and distribution terms for this file may be
1472+  * found in the file LICENSE in this distribution or at
1473+  * http://www.rtems.com/license
1474+  *
1475+  * @author Rohan Kangralkar, ECE, Northeastern University
1476+  *         (kangralkar.r@husky.neu.edu)
1477+  *
1478+  * LastChange:
1479+  * $Id: bf52x.h 48 2011-04-19 15:00:07Z rkangral $
1480+  *
1481+  */
1482+
1483+ #ifndef _BF52X_H_
1484+ #define _BF52X_H_
1485+
1486+ /* register (or register block) addresses */
1487+
1488+ #define SIC_BASE_ADDRESS                          0xffc00100
1489+ #define WDOG_BASE_ADDRESS                         0xffc00200
1490+ #define RTC_BASE_ADDRESS                          0xffc00300
1491+ #define UART0_BASE_ADDRESS                        0xffc00400
1492+ #define UART1_BASE_ADDRESS                        0xffc02000
1493+ #define SPI_BASE_ADDRESS                          0xffc00500
1494+ #define TIMER_BASE_ADDRESS                        0xffc00600
1495+ #define TIMER_CHANNELS                                     3
1496+ #define TIMER_PITCH                                     0x10
1497+ #define TIMER0_BASE_ADDRESS                       0xffc00600
1498+ #define TIMER1_BASE_ADDRESS                       0xffc00610
1499+ #define TIMER2_BASE_ADDRESS                       0xffc00620
1500+ #define TIMER_ENABLE                              0xffc00640
1501+ #define TIMER_DISABLE                             0xffc00644
1502+ #define TIMER_STATUS                              0xffc00648
1503+ #define PORTFIO_BASE_ADDRESS                      0xffc00700
1504+ #define SPORT0_BASE_ADDRESS                       0xffc00800
1505+ #define SPORT1_BASE_ADDRESS                       0xffc00900
1506+ #define EBIU_BASE_ADDRESS                         0xffc00a00
1507+ #define DMA_TC_PER                                0xffc00b0c
1508+ #define DMA_TC_CNT                                0xffc00b10
1509+ #define DMA_BASE_ADDRESS                          0xffc00c00
1510+ #define DMA_CHANNELS                                       8
1511+ #define DMA_PITCH                                       0x40
1512+ #define DMA0_BASE_ADDRESS                         0xffc00c00
1513+ #define DMA1_BASE_ADDRESS                         0xffc00c40
1514+ #define DMA2_BASE_ADDRESS                         0xffc00c80
1515+ #define DMA3_BASE_ADDRESS                         0xffc00cc0
1516+ #define DMA4_BASE_ADDRESS                         0xffc00d00
1517+ #define DMA5_BASE_ADDRESS                         0xffc00d40
1518+ #define DMA6_BASE_ADDRESS                         0xffc00d80
1519+ #define DMA7_BASE_ADDRESS                         0xffc00dc0
1520+ #define DMA8_BASE_ADDRESS                         0xffc00e00
1521+ #define DMA9_BASE_ADDRESS                         0xffc00e40
1522+ #define DMA10_BASE_ADDRESS                        0xffc00e80
1523+ #define DMA11_BASE_ADDRESS                        0xffc00ec0
1524+ #define MDMA_BASE_ADDRESS                         0xffc00e00
1525+ #define MDMA_CHANNELS                                      2
1526+ #define MDMA_D_S                                        0x40
1527+ #define MDMA_PITCH                                      0x80
1528+ #define MDMA0D_BASE_ADDRESS                       0xffc00e00
1529+ #define MDMA0S_BASE_ADDRESS                       0xffc00e40
1530+ #define MDMA1D_BASE_ADDRESS                       0xffc00e80
1531+ #define MDMA1S_BASE_ADDRESS                       0xffc00ec0
1532+ #define PPI_BASE_ADDRESS                          0xffc01000
1533+
1534+
1535+ /* register fields */
1536+
1537+ #define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_MASK       0xf800
1538+ #define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_SHIFT          11
1539+ #define DMA_TC_PER_DAB_TRAFFIC_PERIOD_MASK            0x0700
1540+ #define DMA_TC_PER_DAB_TRAFFIC_PERIOD_SHIFT                8
1541+ #define DMA_TC_PER_DEB_TRAFFIC_PERIOD_MASK            0x00f0
1542+ #define DMA_TC_PER_DEB_TRAFFIC_PERIOD_SHIFT                4
1543+ #define DMA_TC_PER_DCB_TRAFFIC_PERIOD_MASK            0x000f
1544+ #define DMA_TC_PER_DCB_TRAFFIC_PERIOD_SHIFT                0
1545+
1546+ #define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_MASK        0xf800
1547+ #define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_SHIFT           11
1548+ #define DMA_TC_CNT_DAB_TRAFFIC_COUNT_MASK             0x0700
1549+ #define DMA_TC_CNT_DAB_TRAFFIC_COUNT_SHIFT                 8
1550+ #define DMA_TC_CNT_DEB_TRAFFIC_COUNT_MASK             0x00f0
1551+ #define DMA_TC_CNT_DEB_TRAFFIC_COUNT_SHIFT                 4
1552+ #define DMA_TC_CNT_DCB_TRAFFIC_COUNT_MASK             0x000f
1553+ #define DMA_TC_CNT_DCB_TRAFFIC_COUNT_SHIFT                 0
1554+
1555+ #define TIMER_ENABLE_TIMEN2                           0x0004
1556+ #define TIMER_ENABLE_TIMEN1                           0x0002
1557+ #define TIMER_ENABLE_TIMEN0                           0x0001
1558+
1559+ #define TIMER_DISABLE_TIMDIS2                         0x0004
1560+ #define TIMER_DISABLE_TIMDIS1                         0x0002
1561+ #define TIMER_DISABLE_TIMDIS0                         0x0001
1562+
1563+ #define TIMER_STATUS_TRUN2                        0x00004000
1564+ #define TIMER_STATUS_TRUN1                        0x00002000
1565+ #define TIMER_STATUS_TRUN0                        0x00001000
1566+ #define TIMER_STATUS_TOVF_ERR2                    0x00000040
1567+ #define TIMER_STATUS_TOVF_ERR1                    0x00000020
1568+ #define TIMER_STATUS_TOVF_ERR0                    0x00000010
1569+ #define TIMER_STATUS_TIMIL2                       0x00000004
1570+ #define TIMER_STATUS_TIMIL1                       0x00000002
1571+ #define TIMER_STATUS_TIMIL0                       0x00000001
1572+
1573+ /* Core Event Controller vectors */
1574+
1575+ #define CEC_EMULATION_VECTOR                               0
1576+ #define CEC_RESET_VECTOR                                   1
1577+ #define CEC_NMI_VECTOR                                     2
1578+ #define CEC_EXCEPTIONS_VECTOR                              3
1579+ #define CEC_HARDWARE_ERROR_VECTOR                          5
1580+ #define CEC_CORE_TIMER_VECTOR                              6
1581+ #define CEC_INTERRUPT_BASE_VECTOR                          7
1582+ #define CEC_INTERRUPT_COUNT                                9
1583+
1584+
1585+ /* System Interrupt Controller vectors */
1586+
1587+ #define SIC_IAR_COUNT                                      8
1588+
1589+ #endif /* _BF52X_H_ */
1590+
1591diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libcpu/bfin/bf52x/interrupt/interrupt.c rtems/c/src/lib/libcpu/bfin/bf52x/interrupt/interrupt.c
1592*** rtems-4.10.0/c/src/lib/libcpu/bfin/bf52x/interrupt/interrupt.c      1969-12-31 19:00:00.000000000 -0500
1593--- rtems/c/src/lib/libcpu/bfin/bf52x/interrupt/interrupt.c     2011-04-19 11:38:37.000000000 -0400
1594***************
1595*** 0 ****
1596--- 1,643 ----
1597+ /**
1598+  *@file interrupt.c
1599+  *
1600+  *@brief
1601+  * - This file implements interrupt dispatcher. Most of the code is taken from
1602+  *  the 533 implementation for blackfin. Since 52X supports 56 line and 2 ISR
1603+  *  registers some portion is written twice.
1604+  *
1605+  * Target:   TLL6527v1-0
1606+  * Compiler:
1607+  *
1608+  * COPYRIGHT (c) 2010 by ECE Northeastern University.
1609+  *
1610+  * The license and distribution terms for this file may be
1611+  * found in the file LICENSE in this distribution or at
1612+  * http://www.rtems.com/license
1613+  *
1614+  * @author Rohan Kangralkar, ECE, Northeastern University
1615+  *         (kangralkar.r@husky.neu.edu)
1616+  *
1617+  * LastChange:
1618+  * $Id: interrupt.c 49 2011-04-19 15:38:37Z rkangral $
1619+  *
1620+  */
1621+
1622+ #include <rtems.h>
1623+ #include <rtems/libio.h>
1624+
1625+ #include <bsp.h>
1626+ #include <libcpu/cecRegs.h>
1627+ #include <libcpu/sicRegs.h>
1628+ #include "interrupt.h"
1629+
1630+ #define SIC_IAR_COUNT_SET0              4
1631+ #define SIC_IAR_BASE_ADDRESS_0  0xFFC00150
1632+
1633+ /**
1634+  * There are two implementations for the interrupt handler.
1635+  * 1. INTERRUPT_USE_TABLE: uses tables for finding the right ISR.
1636+  * 2. Uses link list to find the user ISR.
1637+  *
1638+  *
1639+  * 1. INTERRUPT_USE_TABLE
1640+  * Space requirement:
1641+  *  - Array to hold CEC masks size: CEC_INTERRUPT_COUNT(9)*(2*int).9*2*4= 72B
1642+  *  - Array to hold isr function pointers IRQ_MAX(56)*sizeof(bfin_isr_t)= 896B
1643+  *  - Array for bit twidlling 32 bytes.
1644+  *  - Global Mask 8 bytes.
1645+  *  - Total = 1008 Bytes Aprox
1646+  *
1647+  * Time requirements
1648+  *    The worst case time is about the same for jumping to the user ISR. With a
1649+  *    variance of one conditional statement.
1650+  *
1651+  * 2. Using link list.
1652+  * Space requirement:
1653+  *  - Array to hold CEC mask CEC_INTERRUPT_COUNT(9)*(sizeof(vectors)).
1654+  *                                                                 9*3*4= 108B
1655+  *  - Array to hold isr IRQ_MAX(56)*sizeof(bfin_isr_t) The structure has
1656+  *    additional pointers                                         56*7*4=1568B
1657+  *  - Global Mask 8 bytes.
1658+  *    Total = 1684.
1659+  * Time requirements
1660+  *    In the worst case all the lines can be on one CEC line to 56 entries have
1661+  *    to be traversed to find the right user ISR.
1662+  *    But this implementation has benefit of being flexible, Providing
1663+  *    additional user assigned priority. and may consume less space
1664+  *    if all devices are not supported.
1665+  */
1666+
1667+ /**
1668+  * TODO: To place the dispatcher routine code in L1.
1669+  */
1670+
1671+ #if INTERRUPT_USE_TABLE
1672+
1673+
1674+ /******************************************************************************
1675+  * Static variables
1676+  *****************************************************************************/
1677+ /**
1678+  * @var sic_isr0_mask
1679+  * @brief copy of the mask of SIC ISR. The SIC ISR is cleared by the device
1680+  * the relevant SIC_ISRx bit is not cleared unless the interrupt
1681+  * service routine clears the mechanism that generated interrupt
1682+  */
1683+ static uint32_t sic_isr0_mask = 0;
1684+
1685+ /**
1686+  * @var sic_isr0_mask
1687+  * @brief copy of the mask of SIC ISR. The SIC ISR is cleared by the device
1688+  * the relevant SIC_ISRx bit is not cleared unless the interrupt
1689+  * service routine clears the mechanism that generated interrupt
1690+  */
1691+ static uint32_t sic_isr1_mask = 0;
1692+
1693+
1694+ /**
1695+  * @var sic_isr
1696+  * @brief An array of sic register mask for each of the 16 core interrupt lines
1697+  */
1698+ static struct {
1699+   uint32_t mask0;
1700+   uint32_t mask1;
1701+ } vectors[CEC_INTERRUPT_COUNT];
1702+
1703+ /**
1704+  * @var ivt
1705+  * @brief Contains a table of ISR and arguments. The ISR jumps directly to
1706+  * these ISR.
1707+  */
1708+ static bfin_isr_t ivt[IRQ_MAX];
1709+
1710+ /**
1711+  * http://graphics.stanford.edu/~seander/bithacks.html for more details
1712+  */
1713+ static const char clz_table[32] =
1714+ {
1715+     0, 31, 9, 30, 3, 8, 18, 29, 2, 5, 7, 14, 12, 17,
1716+     22, 28, 1, 10, 4, 19, 6, 15, 13, 23, 11, 20, 16,
1717+     24, 21, 25, 26, 27
1718+ };
1719+
1720+ /**
1721+  * finds the first bit set from the left. look at
1722+  * http://graphics.stanford.edu/~seander/bithacks.html for more details
1723+  * @param n
1724+  * @return
1725+  */
1726+ static unsigned long clz(unsigned long n)
1727+ {
1728+   unsigned long c = 0x7dcd629;       /* magic constant... */
1729+
1730+   n |= (n >> 1);
1731+   n |= (n >> 2);
1732+   n |= (n >> 4);
1733+   n |= (n >> 8);
1734+   n |= (n >> 16);
1735+   if (n == 0) return 32;
1736+   n = c + (c * n);
1737+   return 31 - clz_table[n >> 27];       /* For little endian    */
1738+ }
1739+
1740+
1741+
1742+ /**
1743+  * Centralized Interrupt dispatcher routine. This routine dispatches interrupts
1744+  * to the user ISR. The priority is according to the blackfin SIC.
1745+  * The first level of priority is handled in the hardware at the core event
1746+  * controller. The second level of interrupt is handled according to the line
1747+  * number that goes in to the SIC.
1748+  * * SIC_0 has higher priority than SIC 1.
1749+  * * Inside the SIC the priority is assigned according to the line number.
1750+  *   Lower the line number higher the priority.
1751+  *
1752+  *   In order to change the interrupt priority we may
1753+  *   1. change the SIC IAR registers or
1754+  *   2. Assign priority and extract it inside this function and call the ISR
1755+  *   according tot the priority.
1756+  *
1757+  * @param vector IVG number.
1758+  * @return
1759+  */
1760+ static rtems_isr interruptHandler(rtems_vector_number vector) {
1761+   uint32_t mask = 0;
1762+   int id = 0;
1763+   /**
1764+    * Enable for debugging
1765+    *
1766+    * static volatile uint32_t spurious_sic0    = 0;
1767+    * static volatile uint32_t spurious_source  = 0;
1768+    * static volatile uint32_t spurious_sic1    = 0;
1769+    */
1770+
1771+   /**
1772+    * Extract the vector number relative to the SIC start line
1773+    */
1774+   vector -= CEC_INTERRUPT_BASE_VECTOR;
1775+
1776+   /**
1777+    * Check for bounds
1778+    */
1779+   if (vector >= 0 && vector < CEC_INTERRUPT_COUNT) {
1780+
1781+     /**
1782+      * Extract information and execute ISR from SIC 0
1783+      */
1784+     mask = *(uint32_t volatile *) SIC_ISR &
1785+         *(uint32_t volatile *) SIC_IMASK & vectors[vector].mask0;
1786+     id      = clz(mask);
1787+     if ( SIC_ISR0_MAX > id ) {
1788+       /** Parameter check */
1789+       if( NULL != ivt[id].pFunc) {
1790+         /** Call the relevant function with argument */
1791+         ivt[id].pFunc( ivt[id].pArg );
1792+       } else {
1793+         /**
1794+          * spurious interrupt we should not be getting this
1795+          * spurious_sic0++;
1796+          * spurious_source = id;
1797+          */
1798+       }
1799+     } else {
1800+       /**
1801+        * we look at SIC 1
1802+        */
1803+     }
1804+
1805+
1806+     /**
1807+      * Extract information and execute ISR from SIC 1
1808+      */
1809+     mask    = *(uint32_t volatile *) (SIC_ISR + SIC_ISR_PITCH) &
1810+         *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH) &
1811+         vectors[vector].mask1;
1812+     id      = clz(mask)+SIC_ISR0_MAX;
1813+     if ( IRQ_MAX > id ) {
1814+       /** Parameter Check */
1815+       if( NULL != ivt[id].pFunc ) {
1816+         /** Call the relevant function with argument */
1817+         ivt[id].pFunc( ivt[id].pArg );
1818+       } else {
1819+         /**
1820+          * spurious interrupt we should not be getting this
1821+          *
1822+          * spurious_sic1++;
1823+          * spurious_source = id;
1824+          */
1825+       }
1826+     } else {
1827+       /**
1828+        * we continue
1829+        */
1830+     }
1831+
1832+   }
1833+ }
1834+
1835+
1836+
1837+ /**
1838+  * This routine registers a new ISR. It will write a new entry to the IVT table
1839+  * @param isr contains a callback function and source
1840+  * @return rtems status code
1841+  */
1842+ rtems_status_code bfin_interrupt_register(bfin_isr_t *isr) {
1843+   rtems_interrupt_level isrLevel;
1844+   int               id        = 0;
1845+   int               position  = 0;
1846+
1847+   /**
1848+    * Sanity Check
1849+    */
1850+   if ( NULL == isr ){
1851+     return RTEMS_UNSATISFIED;
1852+   }
1853+
1854+   /**
1855+    * Sanity check. The register function should at least provide callback func
1856+    */
1857+   if ( NULL == isr->pFunc ) {
1858+     return RTEMS_UNSATISFIED;
1859+   }
1860+
1861+   id = isr->source;
1862+
1863+   /**
1864+    * Parameter Check. We already have a function registered here. First
1865+    * unregister and then a new function can be allocated.
1866+    */
1867+   if ( NULL != ivt[id].pFunc ) {
1868+     return RTEMS_UNSATISFIED;
1869+   }
1870+
1871+   rtems_interrupt_disable(isrLevel);
1872+   /**
1873+    * Assign the new function pointer to the ISR Dispatcher
1874+    * */
1875+   ivt[id].pFunc    = isr->pFunc;
1876+   ivt[id].pArg     = isr->pArg;
1877+
1878+
1879+   /** find out which isr mask has to be set to enable the interrupt */
1880+   if ( SIC_ISR0_MAX > id ) {
1881+     sic_isr0_mask |= 0x1<<id;
1882+     *(uint32_t volatile *) SIC_IMASK  |= 0x1<<id;
1883+   } else {
1884+     position = id - SIC_ISR0_MAX;
1885+     sic_isr1_mask |= 0x1<<position;
1886+     *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH)  |= 0x1<<position;
1887+   }
1888+
1889+   rtems_interrupt_enable(isrLevel);
1890+
1891+   return RTEMS_SUCCESSFUL;
1892+ }
1893+
1894+
1895+ /**
1896+  * This function unregisters a registered interrupt handler.
1897+  * @param isr
1898+  */
1899+ rtems_status_code bfin_interrupt_unregister(bfin_isr_t *isr) {
1900+   rtems_interrupt_level isrLevel;
1901+   int               id        = 0;
1902+   int               position  = 0;
1903+
1904+   /**
1905+    * Sanity Check
1906+    */
1907+   if ( NULL == isr ){
1908+     return RTEMS_UNSATISFIED;
1909+   }
1910+
1911+   id = isr->source;
1912+
1913+   rtems_interrupt_disable(isrLevel);
1914+   /**
1915+    * Assign the new function pointer to the ISR Dispatcher
1916+    * */
1917+   ivt[id].pFunc    = NULL;
1918+   ivt[id].pArg     = NULL;
1919+
1920+
1921+   /** find out which isr mask has to be set to enable the interrupt */
1922+   if ( SIC_ISR0_MAX > id ) {
1923+     sic_isr0_mask &= ~(0x1<<id);
1924+     *(uint32_t volatile *) SIC_IMASK  &= ~(0x1<<id);
1925+   } else {
1926+     position = id - SIC_ISR0_MAX;
1927+     sic_isr1_mask &= ~(0x1<<position);
1928+     *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH)  &= ~(0x1<<position);
1929+   }
1930+
1931+   rtems_interrupt_enable(isrLevel);
1932+
1933+   return RTEMS_SUCCESSFUL;
1934+ }
1935+
1936+
1937+
1938+
1939+ /**
1940+  * blackfin interrupt initialization routine. It initializes the bfin ISR
1941+  * dispatcher. It will also create SIC CEC map which will be used for
1942+  * identifying the ISR.
1943+  */
1944+ void bfin_interrupt_init(void) {
1945+   int source;
1946+   int vector;
1947+   uint32_t r;
1948+   int i;
1949+   int j;
1950+
1951+   *(uint32_t volatile *) SIC_IMASK = 0;
1952+   *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH) = 0;
1953+
1954+   memset(vectors, 0, sizeof(vectors));
1955+   /* build mask0 showing what SIC sources drive each CEC vector */
1956+   source = 0;
1957+
1958+   /**
1959+    * The bf52x has 8 IAR registers but they do not have a constant pitch.
1960+    *
1961+    */
1962+   for (i = 0; i < SIC_IAR_COUNT; i++) {
1963+     if ( SIC_IAR_COUNT_SET0 > i ) {
1964+       r = *(uint32_t volatile *) (SIC_IAR_BASE_ADDRESS + i * SIC_IAR_PITCH);
1965+     } else {
1966+       r = *(uint32_t volatile *) (SIC_IAR_BASE_ADDRESS_0 +
1967+           ((i-SIC_IAR_COUNT_SET0) * SIC_IAR_PITCH));
1968+     }
1969+
1970+     for (j = 0; j < 8; j++) {
1971+       vector = r & 0x0f;
1972+       if (vector >= 0 && vector < CEC_INTERRUPT_COUNT) {
1973+         /* install our local handler */
1974+         if (vectors[vector].mask0 == 0 && vectors[vector].mask1 == 0){
1975+           set_vector(interruptHandler, vector + CEC_INTERRUPT_BASE_VECTOR, 1);
1976+         }
1977+         if ( SIC_ISR0_MAX > source ) {
1978+           vectors[vector].mask0 |= (1 << source);
1979+         } else {
1980+           vectors[vector].mask1 |= (1 << (source - SIC_ISR0_MAX));
1981+         }
1982+       }
1983+       r >>= 4;
1984+       source++;
1985+     }
1986+   }
1987+ }
1988+
1989+
1990+
1991+
1992+
1993+ #else
1994+
1995+ static struct {
1996+   uint32_t mask0;
1997+   uint32_t mask1;
1998+   bfin_isr_t *head;
1999+ } vectors[CEC_INTERRUPT_COUNT];
2000+
2001+ static uint32_t globalMask0;
2002+ static uint32_t globalMask1;
2003+
2004+ static rtems_isr interruptHandler(rtems_vector_number vector) {
2005+   bfin_isr_t *isr = NULL;
2006+   uint32_t sourceMask0 = 0;
2007+   uint32_t sourceMask1 = 0;
2008+   rtems_interrupt_level isrLevel;
2009+
2010+   rtems_interrupt_disable(isrLevel);
2011+   vector -= CEC_INTERRUPT_BASE_VECTOR;
2012+   if (vector >= 0 && vector < CEC_INTERRUPT_COUNT) {
2013+     isr = vectors[vector].head;
2014+     sourceMask0 = *(uint32_t volatile *) SIC_ISR &
2015+         *(uint32_t volatile *) SIC_IMASK;
2016+     sourceMask1 = *(uint32_t volatile *) (SIC_ISR + SIC_ISR_PITCH) &
2017+         *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH);
2018+     while (isr) {
2019+       if ((sourceMask0 & isr->mask0) || (sourceMask1 & isr->mask1)) {
2020+         isr->isr(isr->_arg);
2021+         sourceMask0 = *(uint32_t volatile *) SIC_ISR &
2022+             *(uint32_t volatile *) SIC_IMASK;
2023+         sourceMask1 = *(uint32_t volatile *) (SIC_ISR + SIC_ISR_PITCH) &
2024+             *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH);
2025+       }
2026+       isr = isr->next;
2027+     }
2028+   }
2029+   rtems_interrupt_enable(isrLevel);
2030+ }
2031+
2032+ /**
2033+  * Initializes the interrupt module
2034+  */
2035+ void bfin_interrupt_init(void) {
2036+   int source;
2037+   int vector;
2038+   uint32_t r;
2039+   int i;
2040+   int j;
2041+
2042+   globalMask0 = ~(uint32_t) 0;
2043+   globalMask1 = ~(uint32_t) 0;
2044+   *(uint32_t volatile *) SIC_IMASK = 0;
2045+   *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH) = 0;
2046+
2047+   memset(vectors, 0, sizeof(vectors));
2048+   /* build mask0 showing what SIC sources drive each CEC vector */
2049+   source = 0;
2050+
2051+   /**
2052+    * The bf52x has 8 IAR registers but they do not have a constant pitch.
2053+    *
2054+    */
2055+   for (i = 0; i < SIC_IAR_COUNT; i++) {
2056+     if ( SIC_IAR_COUNT_SET0 > i ) {
2057+       r = *(uint32_t volatile *) (SIC_IAR_BASE_ADDRESS + i * SIC_IAR_PITCH);
2058+     } else {
2059+       r = *(uint32_t volatile *) (SIC_IAR_BASE_ADDRESS_0 +
2060+           ((i-SIC_IAR_COUNT_SET0) * SIC_IAR_PITCH));
2061+     }
2062+     for (j = 0; j < 8; j++) {
2063+       vector = r & 0x0f;
2064+       if (vector >= 0 && vector < CEC_INTERRUPT_COUNT) {
2065+         /* install our local handler */
2066+         if (vectors[vector].mask0 == 0 && vectors[vector].mask1 == 0){
2067+           set_vector(interruptHandler, vector + CEC_INTERRUPT_BASE_VECTOR, 1);
2068+         }
2069+         if ( SIC_ISR0_MAX > source ) {
2070+           vectors[vector].mask0 |= (1 << source);
2071+         } else {
2072+           vectors[vector].mask1 |= (1 << (source - SIC_ISR0_MAX));
2073+         }
2074+       }
2075+       r >>= 4;
2076+       source++;
2077+     }
2078+   }
2079+ }
2080+
2081+ /* modify SIC_IMASK based on ISR list for a particular CEC vector */
2082+ static void setMask(uint32_t vector) {
2083+   bfin_isr_t *isr = NULL;
2084+   uint32_t mask = 0;
2085+   uint32_t r    = 0;
2086+
2087+   mask = 0;
2088+   isr = vectors[vector].head;
2089+   while (isr) {
2090+     mask |= isr->mask0;
2091+     isr = isr->next;
2092+   }
2093+   r = *(uint32_t volatile *) SIC_IMASK;
2094+   r &= ~vectors[vector].mask0;
2095+   r |= mask;
2096+   r &= globalMask0;
2097+   *(uint32_t volatile *) SIC_IMASK = r;
2098+
2099+
2100+   mask = 0;
2101+   isr = vectors[vector].head;
2102+   while (isr) {
2103+     mask |= isr->mask1;
2104+     isr = isr->next;
2105+   }
2106+   r = *(uint32_t volatile *) (SIC_IMASK+ SIC_IMASK_PITCH);
2107+   r &= ~vectors[vector].mask1;
2108+   r |= mask;
2109+   r &= globalMask1;
2110+   *(uint32_t volatile *) (SIC_IMASK+ SIC_IMASK_PITCH) = r;
2111+ }
2112+
2113+ /* add an ISR to the list for whichever vector it belongs to */
2114+ rtems_status_code bfin_interrupt_register(bfin_isr_t *isr) {
2115+   bfin_isr_t *walk;
2116+   rtems_interrupt_level isrLevel;
2117+
2118+   /* find the appropriate vector */
2119+   for (isr->vector = 0; isr->vector < CEC_INTERRUPT_COUNT; isr->vector++)
2120+     if ( (vectors[isr->vector].mask0 & (1 << isr->source) ) || \
2121+         (vectors[isr->vector].mask1 & (1 << (isr->source - SIC_ISR0_MAX)) ))
2122+       break;
2123+   if (isr->vector < CEC_INTERRUPT_COUNT) {
2124+     isr->next = NULL;
2125+     isr->mask0 = 0;
2126+     isr->mask1 = 0;
2127+     rtems_interrupt_disable(isrLevel);
2128+     /* find the current end of the list */
2129+     walk = vectors[isr->vector].head;
2130+     while (walk && walk->next)
2131+       walk = walk->next;
2132+     /* append new isr to list */
2133+     if (walk)
2134+       walk->next = isr;
2135+     else
2136+       vectors[isr->vector].head = isr;
2137+     rtems_interrupt_enable(isrLevel);
2138+   } else
2139+     /* we failed, but make vector a legal value so other calls into
2140+              this module with this isr descriptor won't do anything bad */
2141+     isr->vector = 0;
2142+   return RTEMS_SUCCESSFUL;
2143+ }
2144+
2145+ rtems_status_code bfin_interrupt_unregister(bfin_isr_t *isr) {
2146+   bfin_isr_t *walk, *prev;
2147+   rtems_interrupt_level isrLevel;
2148+
2149+   rtems_interrupt_disable(isrLevel);
2150+   walk = vectors[isr->vector].head;
2151+   prev = NULL;
2152+   /* find this isr in our list */
2153+   while (walk && walk != isr) {
2154+     prev = walk;
2155+     walk = walk->next;
2156+   }
2157+   if (walk) {
2158+     /* if found, remove it */
2159+     if (prev)
2160+       prev->next = walk->next;
2161+     else
2162+       vectors[isr->vector].head = walk->next;
2163+     /* fix up SIC_IMASK if necessary */
2164+     setMask(isr->vector);
2165+   }
2166+   rtems_interrupt_enable(isrLevel);
2167+   return RTEMS_SUCCESSFUL;
2168+ }
2169+
2170+ void bfin_interrupt_enable(bfin_isr_t *isr, bool enable) {
2171+   rtems_interrupt_level isrLevel;
2172+
2173+   rtems_interrupt_disable(isrLevel);
2174+   if ( SIC_ISR0_MAX > isr->source ) {
2175+     isr->mask0 = enable ? (1 << isr->source) : 0;
2176+     *(uint32_t volatile *) SIC_IMASK |= isr->mask0;
2177+   }  else {
2178+     isr->mask1 = enable ? (1 << (isr->source - SIC_ISR0_MAX)) : 0;
2179+     *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH) |= isr->mask1;
2180+   }
2181+
2182+   //setMask(isr->vector);
2183+   rtems_interrupt_enable(isrLevel);
2184+ }
2185+
2186+ void bfin_interrupt_enable_all(int source, bool enable) {
2187+   rtems_interrupt_level isrLevel;
2188+   int vector;
2189+   bfin_isr_t *walk;
2190+
2191+   for (vector = 0; vector < CEC_INTERRUPT_COUNT; vector++)
2192+     if ( (vectors[vector].mask0 & (1 << source) ) || \
2193+         (vectors[vector].mask1 & (1 << (source - SIC_ISR0_MAX)) ))
2194+       break;
2195+   if (vector < CEC_INTERRUPT_COUNT) {
2196+     rtems_interrupt_disable(isrLevel);
2197+     walk = vectors[vector].head;
2198+     while (walk) {
2199+       walk->mask0 = enable ? (1 << source) : 0;
2200+       walk = walk->next;
2201+     }
2202+
2203+     walk = vectors[vector].head;
2204+     while (walk) {
2205+       walk->mask1 = enable ? (1 << (source - SIC_ISR0_MAX)) : 0;
2206+       walk = walk->next;
2207+     }
2208+     setMask(vector);
2209+     rtems_interrupt_enable(isrLevel);
2210+   }
2211+ }
2212+
2213+ void bfin_interrupt_enable_global(int source, bool enable) {
2214+   int vector;
2215+   rtems_interrupt_level isrLevel;
2216+
2217+   for (vector = 0; vector < CEC_INTERRUPT_COUNT; vector++)
2218+     if ( (vectors[vector].mask0 & (1 << source) ) || \
2219+         (vectors[vector].mask1 & (1 << (source - SIC_ISR0_MAX)) ))
2220+       break;
2221+   if (vector < CEC_INTERRUPT_COUNT) {
2222+     rtems_interrupt_disable(isrLevel);
2223+     if ( SIC_ISR0_MAX > source ) {
2224+       if (enable)
2225+         globalMask0 |= 1 << source;
2226+       else
2227+         globalMask0 &= ~(1 << source);
2228+     }else {
2229+       if (enable)
2230+         globalMask1 |= 1 << (source - SIC_ISR0_MAX);
2231+       else
2232+         globalMask1 &= ~(1 << (source - SIC_ISR0_MAX));
2233+     }
2234+     setMask(vector);
2235+     rtems_interrupt_enable(isrLevel);
2236+   }
2237+ }
2238+
2239+ #endif
2240diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libcpu/bfin/bf52x/interrupt/interrupt.h rtems/c/src/lib/libcpu/bfin/bf52x/interrupt/interrupt.h
2241*** rtems-4.10.0/c/src/lib/libcpu/bfin/bf52x/interrupt/interrupt.h      1969-12-31 19:00:00.000000000 -0500
2242--- rtems/c/src/lib/libcpu/bfin/bf52x/interrupt/interrupt.h     2011-04-19 11:00:07.000000000 -0400
2243***************
2244*** 0 ****
2245--- 1,146 ----
2246+ /**
2247+  *@file interrupt.h
2248+  *
2249+  *@brief
2250+  *  - This file implements interrupt dispatcher. The init code is taken from
2251+  *  the 533 implementation for blackfin. Since 52X supports 56 line and 2 ISR
2252+  *  registers some portion is written twice.
2253+  *
2254+  * Target:   TLL6527v1-0
2255+  * Compiler:
2256+  *
2257+  * COPYRIGHT (c) 2010 by ECE Northeastern University.
2258+  *
2259+  * The license and distribution terms for this file may be
2260+  * found in the file LICENSE in this distribution or at
2261+  * http://www.rtems.com/license
2262+  *
2263+  * @author Rohan Kangralkar, ECE, Northeastern University
2264+  *         (kangralkar.r@husky.neu.edu)
2265+  *
2266+  * LastChange:
2267+  * $Id: interrupt.h 48 2011-04-19 15:00:07Z rkangral $
2268+  *
2269+  */
2270+
2271+ #ifndef _BFIN_INTERRUPT_H_
2272+ #define _BFIN_INTERRUPT_H_
2273+
2274+
2275+ #ifdef __cplusplus
2276+ extern "C" {
2277+ #endif
2278+
2279+ /** The type of interrupts handled by the SIC
2280+  */
2281+ typedef enum {
2282+     IRQ_PLL_WAKEUP_INTERRUPT,                 /* 0 */
2283+     IRQ_DMA_ERROR_0,                          /* 1 */
2284+     IRQ_DMAR0_BLOCK_INTERRUPT,                /* 2 */
2285+     IRQ_DMAR1_BLOCK_INTERRUPT,                /* 3 */
2286+     IRQ_DMAR0_OVERFLOW_ERROR,                 /* 4 */
2287+     IRQ_DMAR1_OVERFLOW_ERROR,                 /* 5 */
2288+     IRQ_PPI_STATUS,                           /* 6 */
2289+     IRQ_MAC_STATUS,                           /* 7 */
2290+     IRQ_SPORT0_STATUS,                        /* 8 */
2291+     IRQ_SPORT1_STATUS,                        /* 9 */
2292+     IRQ_RESERVED_10,                          /* 10 */
2293+     IRQ_RESERVED_11,                          /* 11 */
2294+     IRQ_UART0_STATUS,                         /* 12 */
2295+     IRQ_UART1_STATUS,                         /* 13 */
2296+     IRQ_REAL_TIME_CLOCK,                      /* 14 */
2297+     IRQ_DMA0_PPI_NFC,                         /* 15 */
2298+     IRQ_DMA3_SPORT0_RX,                       /* 16 */
2299+     IRQ_DMA4_SPORT0_TX,                       /* 17 */
2300+     IRQ_DMA5_SPORT1_RX,                       /* 18 */
2301+     IRQ_DMA6_SPORT1_TX,                       /* 19 */
2302+     IRQ_TWI_INTERRUPT,                        /* 20 */
2303+     IRQ_DMA7_SPI,                             /* 21 */
2304+     IRQ_DMA8_UART0_RX,                        /* 22 */
2305+     IRQ_DMA9_UART0_TX,                        /* 23 */
2306+     IRQ_DMA10_UART1_RX,                       /* 24 */
2307+     IRQ_DMA11_UART1_TX,                       /* 25 */
2308+     IRQ_OTP,                                  /* 26 */
2309+     IRQ_GP_COUNTER,                           /* 27 */
2310+     IRQ_DMA1_MAC_RX_HOSTDP,                   /* 28 */
2311+     IRQ_PORT_H_INTERRUPT_A,                   /* 29 */
2312+     IRQ_DMA2_MAC_TX_NFC,                      /* 30 */
2313+     IRQ_PORT_H_INTERRUPT_B,                   /* 31 */
2314+     SIC_ISR0_MAX,                             /* 32 ***/
2315+     IRQ_TIMER0 = SIC_ISR0_MAX,                /* 32 */
2316+     IRQ_TIMER1,                               /* 33 */
2317+     IRQ_TIMER2,                               /* 34 */
2318+     IRQ_TIMER3,                               /* 35 */
2319+     IRQ_TIMER4,                               /* 36 */
2320+     IRQ_TIMER5,                               /* 37 */
2321+     IRQ_TIMER6,                               /* 38 */
2322+     IRQ_TIMER7,                               /* 39 */
2323+     IRQ_PORT_G_INTERRUPT_A,                   /* 40 */
2324+     IRQ_PORT_G_INTERRUPT_B,                   /* 41 */
2325+     IRQ_MDMA0_STREAM_0_INTERRUPT,             /* 42 */
2326+     IRQ_MDMA1_STREAM_0_INTERRUPT,             /* 43 */
2327+     IRQ_SOFTWARE_WATCHDOG_INTERRUPT,          /* 44 */
2328+     IRQ_PORT_F_INTERRUPT_A,                   /* 45 */
2329+     IRQ_PORT_F_INTERRUPT_B,                   /* 46 */
2330+     IRQ_SPI_STATUS,                           /* 47 */
2331+     IRQ_NFC_STATUS,                           /* 48 */
2332+     IRQ_HOSTDP_STATUS,                        /* 49 */
2333+     IRQ_HOREAD_DONE_INTERRUPT,                /* 50 */
2334+     IRQ_RESERVED_19,                          /* 51 */
2335+     IRQ_USB_INT0_INTERRUPT,                   /* 52 */
2336+     IRQ_USB_INT1_INTERRUPT,                   /* 53 */
2337+     IRQ_USB_INT2_INTERRUPT,                   /* 54 */
2338+     IRQ_USB_DMAINT,                           /* 55 */
2339+     IRQ_MAX,                                  /* 56 */
2340+ } e_isr_t;
2341+
2342+
2343+
2344+
2345+ /* source is the source to the SIC (the bit number in SIC_ISR).  isr is
2346+    the function that will be called when the interrupt is active. */
2347+ typedef struct bfin_isr_s {
2348+ #if INTERRUPT_USE_TABLE
2349+   e_isr_t source;
2350+   void (*pFunc)(void *arg);
2351+   void *pArg;
2352+   int priority; /** not used */
2353+ #else
2354+   int source;
2355+   void (*isr)(void *arg);
2356+   void *_arg;
2357+   /* the following are for internal use only */
2358+   uint32_t mask0;
2359+   uint32_t mask1;
2360+   uint32_t vector;
2361+   struct bfin_isr_s *next;
2362+ #endif
2363+ } bfin_isr_t;
2364+
2365+ /**
2366+  * This routine registers a new ISR. It will write a new entry to the IVT table
2367+  * @param isr contains a callback function and source
2368+  * @return rtems status code
2369+  */
2370+ rtems_status_code bfin_interrupt_register(bfin_isr_t *isr);
2371+
2372+ /**
2373+  * This function unregisters a registered interrupt handler.
2374+  * @param isr
2375+  */
2376+ rtems_status_code bfin_interrupt_unregister(bfin_isr_t *isr);
2377+
2378+ /**
2379+  * blackfin interrupt initialization routine. It initializes the bfin ISR
2380+  * dispatcher. It will also create SIC CEC map which will be used for
2381+  * identifying the ISR.
2382+  */
2383+ void bfin_interrupt_init(void);
2384+
2385+
2386+ #ifdef __cplusplus
2387+ }
2388+ #endif
2389+
2390+ #endif /* _BFIN_INTERRUPT_H_ */
2391+
2392diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libcpu/bfin/ChangeLog rtems/c/src/lib/libcpu/bfin/ChangeLog
2393*** rtems-4.10.0/c/src/lib/libcpu/bfin/ChangeLog        2011-02-02 10:17:24.000000000 -0500
2394--- rtems/c/src/lib/libcpu/bfin/ChangeLog       2011-04-20 11:31:22.000000000 -0400
2395***************
2396*** 1,3 ****
2397--- 1,17 ----
2398+ 2011-04-40  Rohan Kangralkar <rkangral@ece.neu.edu>
2399+
2400+   * bf52x/include: Added additional MMR.
2401+   * bf52x/interrupt: The BF52X processors have a different System interrupt
2402+     controller than present in the 53X range of processors. The 52X have 8
2403+     interrupt assignment registers. The implementation uses tables to increase
2404+     predictability.
2405+   * serial/uart.?: Added DMA based and interrupt based transfer support. The
2406+     old uart code used a single ISR for TX and RX and tried to identify and
2407+     multiplex inside the ISR. In the new code the type of interrupt is
2408+     identified by the central ISR dispatcher bf52x/interrupt or interrupt/.
2409+     This simplifies the UART ISR.
2410+
2411+
2412  2011-02-02    Ralf Corsépius <ralf.corsepius@rtems.org>
2413 
2414        * configure.ac: Require autoconf-2.68, automake-1.11.1.
2415diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libcpu/bfin/configure.ac rtems/c/src/lib/libcpu/bfin/configure.ac
2416*** rtems-4.10.0/c/src/lib/libcpu/bfin/configure.ac     2011-02-02 10:17:24.000000000 -0500
2417--- rtems/c/src/lib/libcpu/bfin/configure.ac    2011-02-25 15:46:42.000000000 -0500
2418***************
2419*** 1,6 ****
2420  ## Process this file with autoconf to produce a configure script.
2421  ##
2422! ## $Id: configure.ac,v 1.2.2.1 2011/02/02 15:17:24 ralf Exp $
2423  ##
2424 
2425  AC_PREREQ([2.68])
2426--- 1,6 ----
2427  ## Process this file with autoconf to produce a configure script.
2428  ##
2429! ## $Id: configure.ac 27 2011-02-25 20:46:42Z rkangral $
2430  ##
2431 
2432  AC_PREREQ([2.68])
2433***************
2434*** 24,29 ****
2435--- 24,33 ----
2436  RTEMS_CHECK_NETWORKING
2437  AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
2438 
2439+ # AM_CONDITIONAL(shared, test "$RTEMS_CPU_MODEL" = "bf52x")
2440+ AM_CONDITIONAL(bf52x, test "$RTEMS_CPU_MODEL" = "bf52x")
2441+
2442+
2443  RTEMS_AMPOLISH3
2444 
2445  # Explicitly list all Makefiles here
2446diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libcpu/bfin/include/dmaRegs.h rtems/c/src/lib/libcpu/bfin/include/dmaRegs.h
2447*** rtems-4.10.0/c/src/lib/libcpu/bfin/include/dmaRegs.h        2008-08-15 16:18:41.000000000 -0400
2448--- rtems/c/src/lib/libcpu/bfin/include/dmaRegs.h       2011-02-25 15:46:42.000000000 -0500
2449***************
2450*** 7,13 ****
2451   *  found in the file LICENSE in this distribution or at
2452   *  http://www.rtems.com/license/LICENSE.
2453   *
2454!  *  $Id: dmaRegs.h,v 1.1 2008/08/15 20:18:41 joel Exp $
2455   */
2456 
2457  #ifndef _dmaRegs_h_
2458--- 7,13 ----
2459   *  found in the file LICENSE in this distribution or at
2460   *  http://www.rtems.com/license/LICENSE.
2461   *
2462!  *  $Id: dmaRegs.h 27 2011-02-25 20:46:42Z rkangral $
2463   */
2464 
2465  #ifndef _dmaRegs_h_
2466diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libcpu/bfin/include/sicRegs.h rtems/c/src/lib/libcpu/bfin/include/sicRegs.h
2467*** rtems-4.10.0/c/src/lib/libcpu/bfin/include/sicRegs.h        2009-11-30 00:03:49.000000000 -0500
2468--- rtems/c/src/lib/libcpu/bfin/include/sicRegs.h       2011-02-25 15:46:42.000000000 -0500
2469***************
2470*** 7,13 ****
2471   *  found in the file LICENSE in this distribution or at
2472   *  http://www.rtems.com/license/LICENSE.
2473   *
2474!  *  $Id: sicRegs.h,v 1.3 2009/11/30 05:03:49 ralf Exp $
2475   */
2476 
2477  #ifndef _sicRegs_h_
2478--- 7,13 ----
2479   *  found in the file LICENSE in this distribution or at
2480   *  http://www.rtems.com/license/LICENSE.
2481   *
2482!  *  $Id: sicRegs.h 27 2011-02-25 20:46:42Z rkangral $
2483   */
2484 
2485  #ifndef _sicRegs_h_
2486***************
2487*** 16,23 ****
2488--- 16,29 ----
2489  /* register addresses */
2490 
2491  #define SIC_IMASK                (SIC_BASE_ADDRESS + 0x000c)
2492+ #define SIC_IMASK_PITCH          (0x40)
2493+
2494+ #define SIC_ISR                  (SIC_BASE_ADDRESS + 0x0020)
2495+ #define SIC_ISR_PITCH            (0x40)
2496+
2497  #define SIC_IAR_BASE_ADDRESS     (SIC_BASE_ADDRESS + 0x0010)
2498  #define SIC_IAR_PITCH                                   0x04
2499+
2500  #define SIC_IAR0                 (SIC_BASE_ADDRESS + 0x0010)
2501  #if SIC_IAR_COUNT > 1
2502  #define SIC_IAR1                 (SIC_BASE_ADDRESS + 0x0014)
2503***************
2504*** 28,34 ****
2505  #if SIC_IAR_COUNT > 3
2506  #define SIC_IAR3                 (SIC_BASE_ADDRESS + 0x001c)
2507  #endif
2508! #define SIC_ISR                  (SIC_BASE_ADDRESS + 0x0020)
2509  #define SIC_IWR                  (SIC_BASE_ADDRESS + 0x0024)
2510 
2511 
2512--- 34,40 ----
2513  #if SIC_IAR_COUNT > 3
2514  #define SIC_IAR3                 (SIC_BASE_ADDRESS + 0x001c)
2515  #endif
2516!
2517  #define SIC_IWR                  (SIC_BASE_ADDRESS + 0x0024)
2518 
2519 
2520diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libcpu/bfin/include/uartRegs.h rtems/c/src/lib/libcpu/bfin/include/uartRegs.h
2521*** rtems-4.10.0/c/src/lib/libcpu/bfin/include/uartRegs.h       2008-08-15 16:18:41.000000000 -0400
2522--- rtems/c/src/lib/libcpu/bfin/include/uartRegs.h      2011-02-25 15:46:42.000000000 -0500
2523***************
2524*** 7,13 ****
2525   *  found in the file LICENSE in this distribution or at
2526   *  http://www.rtems.com/license/LICENSE.
2527   *
2528!  *  $Id: uartRegs.h,v 1.1 2008/08/15 20:18:41 joel Exp $
2529   */
2530 
2531  #ifndef _uartRegs_h_
2532--- 7,13 ----
2533   *  found in the file LICENSE in this distribution or at
2534   *  http://www.rtems.com/license/LICENSE.
2535   *
2536!  *  $Id: uartRegs.h 27 2011-02-25 20:46:42Z rkangral $
2537   */
2538 
2539  #ifndef _uartRegs_h_
2540diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libcpu/bfin/Makefile.am rtems/c/src/lib/libcpu/bfin/Makefile.am
2541*** rtems-4.10.0/c/src/lib/libcpu/bfin/Makefile.am      2008-08-15 16:18:40.000000000 -0400
2542--- rtems/c/src/lib/libcpu/bfin/Makefile.am     2011-02-25 15:46:42.000000000 -0500
2543***************
2544*** 1,5 ****
2545  ##
2546! ## $Id: Makefile.am,v 1.1 2008/08/15 20:18:40 joel Exp $
2547  ##
2548 
2549  ACLOCAL_AMFLAGS = -I ../../../aclocal
2550--- 1,5 ----
2551  ##
2552! ## $Id: Makefile.am 27 2011-02-25 20:46:42Z rkangral $
2553  ##
2554 
2555  ACLOCAL_AMFLAGS = -I ../../../aclocal
2556***************
2557*** 10,18 ****
2558--- 10,40 ----
2559 
2560  noinst_PROGRAMS =
2561 
2562+ include_bspdir = $(includedir)/bsp
2563  include_libcpudir = $(includedir)/libcpu
2564+
2565+ include_bsp_HEADERS =
2566  include_libcpu_HEADERS =
2567 
2568+
2569+ ############
2570+ # Start of bf52x files
2571+ if bf52x
2572+
2573+ include_HEADERS = bf52x/include/bf52x.h
2574+
2575+ ## INTERRUPT
2576+ include_bsp_HEADERS += bf52x/interrupt/interrupt.h
2577+ noinst_PROGRAMS += bf52x/interrupt.rel
2578+ bf52x_interrupt_rel_SOURCES = bf52x/interrupt/interrupt.c \
2579+                               bf52x/interrupt/interrupt.h
2580+ bf52x_interrupt_rel_CPPFLAGS = $(AM_CPPFLAGS)
2581+ bf52x_interrupt_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
2582+
2583+ endif
2584+ # endof bf52x
2585+ ############
2586+
2587  include_libcpu_HEADERS += include/bf533.h
2588  include_libcpu_HEADERS += include/bf537.h
2589  include_libcpu_HEADERS += include/cecRegs.h
2590***************
2591*** 47,58 ****
2592--- 69,85 ----
2593  mmu_rel_CPPFLAGS = $(AM_CPPFLAGS)
2594  mmu_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
2595 
2596+ if bf52x
2597+
2598+ else
2599  include_libcpu_HEADERS += interrupt/interrupt.h
2600  noinst_PROGRAMS += interrupt.rel
2601  interrupt_rel_SOURCES = interrupt/interrupt.c
2602  interrupt_rel_CPPFLAGS = $(AM_CPPFLAGS)
2603  interrupt_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
2604 
2605+ endif
2606+
2607  noinst_PROGRAMS += clock.rel
2608  clock_rel_SOURCES = clock/clock.c
2609  clock_rel_CPPFLAGS = $(AM_CPPFLAGS)
2610diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libcpu/bfin/preinstall.am rtems/c/src/lib/libcpu/bfin/preinstall.am
2611*** rtems-4.10.0/c/src/lib/libcpu/bfin/preinstall.am    2011-02-08 11:13:15.000000000 -0500
2612--- rtems/c/src/lib/libcpu/bfin/preinstall.am   2011-02-17 10:19:06.000000000 -0500
2613***************
2614*** 13,23 ****
2615--- 13,42 ----
2616  PREINSTALL_FILES =
2617  CLEANFILES = $(PREINSTALL_FILES)
2618 
2619+ $(PROJECT_INCLUDE)/$(dirstamp):
2620+       @$(MKDIR_P) $(PROJECT_INCLUDE)
2621+       @: > $(PROJECT_INCLUDE)/$(dirstamp)
2622+ PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
2623+
2624+ $(PROJECT_INCLUDE)/bsp/$(dirstamp):
2625+       @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp
2626+       @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp)
2627+ PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp)
2628+
2629  $(PROJECT_INCLUDE)/libcpu/$(dirstamp):
2630        @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu
2631        @: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
2632  PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
2633 
2634+ if bf52x
2635+ $(PROJECT_INCLUDE)/bf52x.h: bf52x/include/bf52x.h $(PROJECT_INCLUDE)/$(dirstamp)
2636+       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bf52x.h
2637+ PREINSTALL_FILES += $(PROJECT_INCLUDE)/bf52x.h
2638+
2639+ $(PROJECT_INCLUDE)/bsp/interrupt.h: bf52x/interrupt/interrupt.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
2640+       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/interrupt.h
2641+ PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/interrupt.h
2642+ endif
2643  $(PROJECT_INCLUDE)/libcpu/bf533.h: include/bf533.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
2644        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/bf533.h
2645  PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/bf533.h
2646***************
2647*** 102,111 ****
2648        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/mmu.h
2649  PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/mmu.h
2650 
2651  $(PROJECT_INCLUDE)/libcpu/interrupt.h: interrupt/interrupt.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
2652        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/interrupt.h
2653  PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/interrupt.h
2654!
2655  $(PROJECT_INCLUDE)/libcpu/uart.h: serial/uart.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
2656        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/uart.h
2657  PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/uart.h
2658--- 121,132 ----
2659        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/mmu.h
2660  PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/mmu.h
2661 
2662+ if bf52x
2663+ else
2664  $(PROJECT_INCLUDE)/libcpu/interrupt.h: interrupt/interrupt.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
2665        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/interrupt.h
2666  PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/interrupt.h
2667! endif
2668  $(PROJECT_INCLUDE)/libcpu/uart.h: serial/uart.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
2669        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/uart.h
2670  PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/uart.h
2671diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libcpu/bfin/serial/uart.c rtems/c/src/lib/libcpu/bfin/serial/uart.c
2672*** rtems-4.10.0/c/src/lib/libcpu/bfin/serial/uart.c    2009-12-10 23:15:58.000000000 -0500
2673--- rtems/c/src/lib/libcpu/bfin/serial/uart.c   2011-04-19 11:38:37.000000000 -0400
2674***************
2675*** 7,13 ****
2676   *  found in the file LICENSE in this distribution or at
2677   *  http://www.rtems.com/license/LICENSE.
2678   *
2679!  *  $Id: uart.c,v 1.3 2009/12/11 04:15:58 ralf Exp $
2680   */
2681 
2682 
2683--- 7,16 ----
2684   *  found in the file LICENSE in this distribution or at
2685   *  http://www.rtems.com/license/LICENSE.
2686   *
2687!  *  Modified:
2688!  *  $ $Author: rkangral $ Added interrupt support and DMA support
2689!  *
2690!  *  $Id: uart.c 49 2011-04-19 15:38:37Z rkangral $
2691   */
2692 
2693 
2694***************
2695*** 18,26 ****
2696  #include <stdlib.h>
2697 
2698  #include <libcpu/uartRegs.h>
2699  #include "uart.h"
2700 
2701-
2702  /* flags */
2703  #define BFIN_UART_XMIT_BUSY 0x01
2704 
2705--- 21,29 ----
2706  #include <stdlib.h>
2707 
2708  #include <libcpu/uartRegs.h>
2709+ #include <libcpu/dmaRegs.h>
2710  #include "uart.h"
2711 
2712  /* flags */
2713  #define BFIN_UART_XMIT_BUSY 0x01
2714 
2715***************
2716*** 28,72 ****
2717  static bfin_uart_config_t *uartsConfig;
2718 
2719 
2720- static void initializeHardware(int minor) {
2721-   uint16_t divisor;
2722-   char *base;
2723-   uint16_t r;
2724-
2725-   base = uartsConfig->channels[minor].base_address;
2726-
2727-   *(uint16_t volatile *) (base + UART_IER_OFFSET) = 0;
2728-
2729-   if (uartsConfig->channels[minor].force_baud)
2730-     divisor = (uint16_t) (uartsConfig->freq /
2731-                           (uartsConfig->channels[minor].force_baud * 16));
2732-   else
2733-     divisor = (uint16_t) (uartsConfig->freq / (9600 * 16));
2734-   *(uint16_t volatile *) (base + UART_LCR_OFFSET) = UART_LCR_DLAB;
2735-   *(uint16_t volatile *) (base + UART_DLL_OFFSET) = (divisor & 0xff);
2736-   *(uint16_t volatile *) (base + UART_DLH_OFFSET) = ((divisor >> 8) & 0xff);
2737-
2738-   *(uint16_t volatile *) (base + UART_LCR_OFFSET) = UART_LCR_WLS_8;
2739-
2740-   *(uint16_t volatile *) (base + UART_GCTL_OFFSET) = UART_GCTL_UCEN;
2741-
2742-   r = *(uint16_t volatile *) (base + UART_LSR_OFFSET);
2743-   r = *(uint16_t volatile *) (base + UART_RBR_OFFSET);
2744-   r = *(uint16_t volatile *) (base + UART_IIR_OFFSET);
2745-
2746-   return;
2747- }
2748-
2749  static int pollRead(int minor) {
2750    int c;
2751!   char *base;
2752 
2753!   base = uartsConfig->channels[minor].base_address;
2754 
2755    /* check to see if driver is using interrupts so this call will be
2756       harmless (though non-functional) in case some debug code tries to
2757       use it */
2758!   if (!uartsConfig->channels[minor].use_interrupts &&
2759        *((uint16_t volatile *) (base + UART_LSR_OFFSET)) & UART_LSR_DR)
2760      c = *((uint16_t volatile *) (base + UART_RBR_OFFSET));
2761    else
2762--- 31,46 ----
2763  static bfin_uart_config_t *uartsConfig;
2764 
2765 
2766  static int pollRead(int minor) {
2767    int c;
2768!   uint32_t base;
2769 
2770!   base = uartsConfig->channels[minor].uart_baseAddress;
2771 
2772    /* check to see if driver is using interrupts so this call will be
2773       harmless (though non-functional) in case some debug code tries to
2774       use it */
2775!   if (!uartsConfig->channels[minor].uart_useInterrupts &&
2776        *((uint16_t volatile *) (base + UART_LSR_OFFSET)) & UART_LSR_DR)
2777      c = *((uint16_t volatile *) (base + UART_RBR_OFFSET));
2778    else
2779***************
2780*** 75,81 ****
2781    return c;
2782  }
2783 
2784! char bfin_uart_poll_read(int minor) {
2785    int c;
2786 
2787    do {
2788--- 49,55 ----
2789    return c;
2790  }
2791 
2792! char bfin_uart_poll_read(rtems_device_minor_number minor) {
2793    int c;
2794 
2795    do {
2796***************
2797*** 86,94 ****
2798  }
2799 
2800  void bfin_uart_poll_write(int minor, char c) {
2801!   char *base;
2802 
2803!   base = uartsConfig->channels[minor].base_address;
2804 
2805    while (!(*((uint16_t volatile *) (base + UART_LSR_OFFSET)) & UART_LSR_THRE))
2806      ;
2807--- 60,68 ----
2808  }
2809 
2810  void bfin_uart_poll_write(int minor, char c) {
2811!   uint32_t base;
2812 
2813!   base = uartsConfig->channels[minor].uart_baseAddress;
2814 
2815    while (!(*((uint16_t volatile *) (base + UART_LSR_OFFSET)) & UART_LSR_THRE))
2816      ;
2817***************
2818*** 157,200 ****
2819    return count;
2820  }
2821 
2822- static void enableInterrupts(int minor) {
2823-   char *base;
2824 
2825!   base = uartsConfig->channels[minor].base_address;
2826 
2827!   *(uint16_t volatile *) (base + UART_IER_OFFSET) = UART_IER_ETBEI |
2828!                                                     UART_IER_ERBFI;
2829! }
2830 
2831- static void disableAllInterrupts(void) {
2832-   int i;
2833-   char *base;
2834 
2835!   for (i = 0; i < uartsConfig->num_channels; i++) {
2836!     base = uartsConfig->channels[i].base_address;
2837!     *(uint16_t volatile *) (base + UART_IER_OFFSET) = 0;
2838    }
2839- }
2840 
2841! static ssize_t interruptWrite(int minor, const char *buf, size_t len) {
2842!   char *base;
2843 
2844!   base = uartsConfig->channels[minor].base_address;
2845 
2846!   uartsConfig->channels[minor].flags |= BFIN_UART_XMIT_BUSY;
2847!   *(uint16_t volatile *) (base + UART_THR_OFFSET) = *buf;
2848 
2849!   /* one byte written */
2850!   return 1;
2851  }
2852 
2853  static int setAttributes(int minor, const struct termios *termios) {
2854!   char *base;
2855    int baud;
2856    uint16_t divisor;
2857    uint16_t lcr;
2858 
2859!   base = uartsConfig->channels[minor].base_address;
2860    switch (termios->c_cflag & CBAUD) {
2861    case B0:
2862      baud = 0;
2863--- 129,214 ----
2864    return count;
2865  }
2866 
2867 
2868! /**
2869!  * Routine to initialize the hardware. It initialize the DMA,
2870!  * interrupt if required.
2871!  * @param channel channel information
2872!  */
2873! static void initializeHardware(bfin_uart_channel_t *channel) {
2874!   uint16_t divisor        = 0;
2875!   uint32_t base           = 0;
2876!   uint32_t tx_dma_base    = 0;
2877!
2878!   if ( NULL == channel ) {
2879!     return;
2880!   }
2881 
2882!   base        = channel->uart_baseAddress;
2883!   tx_dma_base = channel->uart_txDmaBaseAddress;
2884!   /**
2885!    * RX based DMA and interrupt is not supported yet
2886!    * uint32_t tx_dma_base    = 0;
2887!    *
2888!    * rx_dma_base = channel->uart_rxDmaBaseAddress;
2889!    */
2890 
2891 
2892!   *(uint16_t volatile *) (base + UART_IER_OFFSET) = 0;
2893!
2894!   if ( 0 != channel->uart_baud) {
2895!     divisor = (uint16_t) (uartsConfig->freq /
2896!         (channel->uart_baud * 16));
2897!   } else {
2898!     divisor = (uint16_t) (uartsConfig->freq / (9600 * 16));
2899    }
2900 
2901!   *(uint16_t volatile *) (base + UART_LCR_OFFSET) = UART_LCR_DLAB;
2902!   *(uint16_t volatile *) (base + UART_DLL_OFFSET) = (divisor & 0xff);
2903!   *(uint16_t volatile *) (base + UART_DLH_OFFSET) = ((divisor >> 8) & 0xff);
2904 
2905!   *(uint16_t volatile *) (base + UART_LCR_OFFSET) = UART_LCR_WLS_8;
2906 
2907!   *(uint16_t volatile *) (base + UART_GCTL_OFFSET) = UART_GCTL_UCEN;
2908 
2909!   /**
2910!    * To clear previous status
2911!    * divisor is a temp variable here
2912!    */
2913!   divisor = *(uint16_t volatile *) (base + UART_LSR_OFFSET);
2914!   divisor = *(uint16_t volatile *) (base + UART_RBR_OFFSET);
2915!   divisor = *(uint16_t volatile *) (base + UART_IIR_OFFSET);
2916!
2917!   if ( channel->uart_useDma ) {
2918!     *(uint16_t  volatile *)(tx_dma_base + DMA_CONFIG_OFFSET) = 0;
2919!     *(uint16_t  volatile *)(tx_dma_base + DMA_CONFIG_OFFSET) = DMA_CONFIG_DI_EN
2920!         | DMA_CONFIG_SYNC ;
2921!     *(uint16_t  volatile *)(tx_dma_base + DMA_IRQ_STATUS_OFFSET) |=
2922!         DMA_IRQ_STATUS_DMA_DONE | DMA_IRQ_STATUS_DMA_ERR;
2923!
2924!   } else {
2925!     /**
2926!     * We use polling or interrupts only sending one char at a time :(
2927!     */
2928!   }
2929!
2930!   return;
2931  }
2932 
2933+
2934+ /**
2935+  * Set the UART attributes.
2936+  * @param minor
2937+  * @param termios
2938+  * @return
2939+  */
2940  static int setAttributes(int minor, const struct termios *termios) {
2941!   uint32_t base;
2942    int baud;
2943    uint16_t divisor;
2944    uint16_t lcr;
2945 
2946!   base = uartsConfig->channels[minor].uart_baseAddress;
2947    switch (termios->c_cflag & CBAUD) {
2948    case B0:
2949      baud = 0;
2950***************
2951*** 260,267 ****
2952      baud = -1;
2953      break;
2954    }
2955!   if (baud > 0 && uartsConfig->channels[minor].force_baud)
2956!     baud = uartsConfig->channels[minor].force_baud;
2957    switch (termios->c_cflag & CSIZE) {
2958    case CS5:
2959      lcr = UART_LCR_WLS_5;
2960--- 274,281 ----
2961      baud = -1;
2962      break;
2963    }
2964!   if (baud > 0 && uartsConfig->channels[minor].uart_baud)
2965!     baud = uartsConfig->channels[minor].uart_baud;
2966    switch (termios->c_cflag & CSIZE) {
2967    case CS5:
2968      lcr = UART_LCR_WLS_5;
2969***************
2970*** 282,289 ****
2971      lcr |= UART_LCR_PEN | UART_LCR_EPS;
2972      break;
2973    case PARENB | PARODD:
2974!     lcr |= UART_LCR_PEN;
2975!     break;
2976    default:
2977      break;
2978    }
2979--- 296,303 ----
2980      lcr |= UART_LCR_PEN | UART_LCR_EPS;
2981      break;
2982    case PARENB | PARODD:
2983!   lcr |= UART_LCR_PEN;
2984!   break;
2985    default:
2986      break;
2987    }
2988***************
2989*** 301,414 ****
2990    return 0;
2991  }
2992 
2993! void bfin_uart_isr(int source) {
2994!   int i;
2995!   char *base;
2996!   uint16_t uartStat;
2997!   char c;
2998!   uint8_t uartLSR;
2999!
3000!   /* Just use one ISR and check for all UART interrupt sources in it.
3001!      This is less efficient than making use of the vector to narrow down
3002!      the things we need to check, but not all Blackfins separate the
3003!      UART interrupt sources in the same ways.  This way we don't have
3004!      to make this code dependent on the type of Blackfin.  */
3005!   for (i = 0; i < uartsConfig->num_channels; i++) {
3006!     if (uartsConfig->channels[i].use_interrupts) {
3007!       base = uartsConfig->channels[i].base_address;
3008!       uartStat = *(uint16_t volatile *) (base + UART_IIR_OFFSET);
3009!       if ((uartStat & UART_IIR_NINT) == 0) {
3010!         switch (uartStat & UART_IIR_STATUS_MASK) {
3011!         case UART_IIR_STATUS_THRE:
3012!           if (uartsConfig->channels[i].termios &&
3013!               (uartsConfig->channels[i].flags & BFIN_UART_XMIT_BUSY)) {
3014!             uartsConfig->channels[i].flags &= ~BFIN_UART_XMIT_BUSY;
3015!             rtems_termios_dequeue_characters(uartsConfig->channels[i].termios,
3016!                                              1);
3017!           }
3018!           break;
3019!         case UART_IIR_STATUS_RDR:
3020!           c = *(uint16_t volatile *) (base + UART_RBR_OFFSET);
3021!           if (uartsConfig->channels[i].termios)
3022!             rtems_termios_enqueue_raw_characters(
3023!                 uartsConfig->channels[i].termios, &c, 1);
3024!           break;
3025!         case UART_IIR_STATUS_LS:
3026!           uartLSR = *(uint16_t volatile *) (base + UART_LSR_OFFSET);
3027!           /* break, framing error, parity error, or overrun error
3028!              has been detected */
3029!           break;
3030!         default:
3031!           break;
3032!         }
3033!       }
3034!     }
3035    }
3036  }
3037 
3038! rtems_status_code bfin_uart_initialize(rtems_device_major_number major,
3039!                                        bfin_uart_config_t *config) {
3040!   rtems_status_code status;
3041!   int i;
3042 
3043!   status = RTEMS_SUCCESSFUL;
3044 
3045-   rtems_termios_initialize();
3046 
3047!   /*
3048!    *  Register Device Names
3049     */
3050 
3051!   uartsConfig = config;
3052!   for (i = 0; i < config->num_channels; i++) {
3053!     config->channels[i].termios = NULL;
3054!     config->channels[i].flags = 0;
3055!     initializeHardware(i);
3056!     status = rtems_io_register_name(config->channels[i].name, major, i);
3057    }
3058 
3059!    return RTEMS_SUCCESSFUL;
3060  }
3061 
3062  rtems_device_driver bfin_uart_open(rtems_device_major_number major,
3063!                                    rtems_device_minor_number minor,
3064!                                    void *arg) {
3065!   rtems_status_code sc;
3066!   rtems_libio_open_close_args_t *args;
3067    static const rtems_termios_callbacks pollCallbacks = {
3068!     NULL,                        /* firstOpen */
3069!     NULL,                        /* lastClose */
3070!     pollRead,                    /* pollRead */
3071!     pollWrite,                   /* write */
3072!     setAttributes,               /* setAttributes */
3073!     NULL,                        /* stopRemoteTx */
3074!     NULL,                        /* startRemoteTx */
3075!     TERMIOS_POLLED               /* outputUsesInterrupts */
3076    };
3077    static const rtems_termios_callbacks interruptCallbacks = {
3078!     NULL,                        /* firstOpen */
3079!     NULL,                        /* lastClose */
3080!     NULL,                        /* pollRead */
3081!     interruptWrite,              /* write */
3082!     setAttributes,               /* setAttributes */
3083!     NULL,                        /* stopRemoteTx */
3084!     NULL,                        /* startRemoteTx */
3085!     TERMIOS_IRQ_DRIVEN           /* outputUsesInterrupts */
3086    };
3087 
3088!   if (uartsConfig == NULL || minor < 0 || minor >= uartsConfig->num_channels)
3089      return RTEMS_INVALID_NUMBER;
3090 
3091-   sc = rtems_termios_open(major, minor, arg,
3092-                           uartsConfig->channels[minor].use_interrupts ?
3093-                           &interruptCallbacks : &pollCallbacks);
3094    args = arg;
3095    uartsConfig->channels[minor].termios = args->iop->data1;
3096 
3097!   if (uartsConfig->channels[minor].use_interrupts)
3098!     enableInterrupts(minor);
3099!   atexit(disableAllInterrupts);
3100 
3101    return sc;
3102  }
3103 
3104--- 315,640 ----
3105    return 0;
3106  }
3107 
3108! /**
3109!  * Interrupt based uart tx routine. The routine writes one character at a time.
3110!  *
3111!  * @param minor Minor number to indicate uart number
3112!  * @param buf Character buffer which stores characters to be transmitted.
3113!  * @param len Length of buffer to be transmitted.
3114!  * @return
3115!  */
3116! static ssize_t uart_interruptWrite(int minor, const char *buf, size_t len) {
3117!   uint32_t              base      = 0;
3118!   bfin_uart_channel_t*  channel   = NULL;
3119!   rtems_interrupt_level isrLevel;
3120!
3121!   /**
3122!    * Sanity Check
3123!    */
3124!   if (NULL == buf || NULL == channel || NULL == uartsConfig || minor < 0) {
3125!     return 0;
3126!   }
3127!
3128!   channel = &(uartsConfig->channels[minor]);
3129!
3130!   if ( NULL == channel || channel->flags &  BFIN_UART_XMIT_BUSY ) {
3131!     return 0;
3132    }
3133+
3134+   rtems_interrupt_disable(isrLevel);
3135+
3136+   base = channel->uart_baseAddress;
3137+
3138+   channel->flags |= BFIN_UART_XMIT_BUSY;
3139+   channel->length = 1;
3140+   *(uint16_t volatile *) (base + UART_THR_OFFSET) = *buf;
3141+   *(uint16_t volatile *) (base + UART_IER_OFFSET) = UART_IER_ETBEI;
3142+
3143+   rtems_interrupt_enable(isrLevel);
3144+
3145+   return 0;
3146  }
3147 
3148! /**
3149! * This function implements RX ISR
3150! */
3151! void bfinUart_rxIsr(void *_arg)
3152! {
3153!   /**
3154!    * TODO: UART RX ISR implementation.
3155!    */
3156 
3157! }
3158 
3159 
3160! /**
3161!  * This function implements TX ISR. The function gets called when the TX FIFO is
3162!  * empty. It clears the interrupt and dequeues the character. It only tx one
3163!  * character at a time.
3164!  *
3165!  * TODO: error handling.
3166!  * @param _arg gets the channel information.
3167!  */
3168! void bfinUart_txIsr(void *_arg) {
3169!   bfin_uart_channel_t*  channel = NULL;
3170!   uint32_t              base    = 0;
3171!
3172!   /**
3173!    * Sanity check
3174     */
3175+   if (NULL == _arg) {
3176+     /** It should never be NULL */
3177+     return;
3178+   }
3179 
3180!   channel = (bfin_uart_channel_t *) _arg;
3181!
3182!   base = channel->uart_baseAddress;
3183!
3184!   *(uint16_t volatile *) (base + UART_IER_OFFSET) &= ~UART_IER_ETBEI;
3185!   channel->flags &= ~BFIN_UART_XMIT_BUSY;
3186!
3187!   rtems_termios_dequeue_characters(channel->termios, channel->length);
3188!
3189!   return;
3190! }
3191!
3192!
3193!
3194!
3195! /**
3196!  * interrupt based DMA write Routine. It configure the DMA to write len bytes.
3197!  * The DMA supports 64K data only.
3198!  *
3199!  * @param minor Identification number of the UART.
3200!  * @param buf Character buffer pointer
3201!  * @param len length of data items to be written
3202!  * @return data already written
3203!  */
3204! static ssize_t uart_DmaWrite(int minor, const char *buf, size_t len) {
3205!   uint32_t              base        = 0;
3206!   bfin_uart_channel_t*  channel     = NULL;
3207!   uint32_t              tx_dma_base = 0;
3208!   rtems_interrupt_level isrLevel;
3209!
3210!   /**
3211!    * Sanity Check
3212!    */
3213!   if ( NULL == buf || 0 > minor || NULL == uartsConfig ) {
3214!     return 0;
3215!   }
3216!
3217!   channel = &(uartsConfig->channels[minor]);
3218!
3219!   /**
3220!    * Sanity Check and check for transmit busy.
3221!    */
3222!   if ( NULL == channel || BFIN_UART_XMIT_BUSY & channel->flags ) {
3223!     return 0;
3224!   }
3225!
3226!   rtems_interrupt_disable(isrLevel);
3227!
3228!   base        = channel->uart_baseAddress;
3229!   tx_dma_base = channel->uart_txDmaBaseAddress;
3230!
3231!   channel->flags |= BFIN_UART_XMIT_BUSY;
3232!   channel->length = len;
3233!
3234!   *(uint16_t volatile *) (tx_dma_base + DMA_CONFIG_OFFSET) &= ~DMA_CONFIG_DMAEN;
3235!   *(uint32_t volatile *) (tx_dma_base + DMA_START_ADDR_OFFSET) = (uint32_t)buf;
3236!   *(uint16_t volatile *) (tx_dma_base + DMA_X_COUNT_OFFSET) = channel->length;
3237!   *(uint16_t volatile *) (tx_dma_base + DMA_X_MODIFY_OFFSET) = 1;
3238!   *(uint16_t volatile *) (tx_dma_base + DMA_CONFIG_OFFSET) |= DMA_CONFIG_DMAEN;
3239!   *(uint16_t volatile *) (base + UART_IER_OFFSET) = UART_IER_ETBEI;
3240!
3241!   rtems_interrupt_enable(isrLevel);
3242!
3243!   return 0;
3244! }
3245!
3246!
3247! /**
3248!  * RX DMA ISR.
3249!  * The polling route is used for receiving the characters. This is a place
3250!  * holder for future implementation.
3251!  * @param _arg
3252!  */
3253! void bfinUart_rxDmaIsr(void *_arg) {
3254! /**
3255!  * TODO: Implementation of RX DMA
3256!  */
3257! }
3258!
3259! /**
3260!  * This function implements TX dma ISR. It clears the IRQ and dequeues a char
3261!  * The channel argument will have the base address. Since there are two uart
3262!  * and both the uarts can use the same tx dma isr.
3263!  *
3264!  * TODO: 1. Error checking 2. sending correct length ie after looking at the
3265!  * number of elements the uart transmitted.
3266!  *
3267!  * @param _arg argument passed to the interrupt handler. It contains the
3268!  * channel argument.
3269!  */
3270! void bfinUart_txDmaIsr(void *_arg) {
3271!   bfin_uart_channel_t*  channel     = NULL;
3272!   uint32_t              tx_dma_base = 0;
3273!
3274!   /**
3275!    * Sanity check
3276!    */
3277!   if (NULL == _arg) {
3278!     /** It should never be NULL */
3279!     return;
3280!   }
3281!
3282!   channel = (bfin_uart_channel_t *) _arg;
3283!
3284!   tx_dma_base = channel->uart_txDmaBaseAddress;
3285!
3286!   if ((*(uint16_t volatile *) (tx_dma_base + DMA_IRQ_STATUS_OFFSET)
3287!       & DMA_IRQ_STATUS_DMA_DONE)) {
3288!
3289!     *(uint16_t volatile *) (tx_dma_base + DMA_IRQ_STATUS_OFFSET)
3290!                           |= DMA_IRQ_STATUS_DMA_DONE | DMA_IRQ_STATUS_DMA_ERR;
3291!     channel->flags &= ~BFIN_UART_XMIT_BUSY;
3292!     rtems_termios_dequeue_characters(channel->termios, channel->length);
3293!   } else {
3294!     /* UART DMA did not generate interrupt.
3295!      * This routine must not be called.
3296!      */
3297    }
3298 
3299!   return;
3300! }
3301!
3302! /**
3303!  * Function called during exit
3304!  */
3305! void uart_exit(void)
3306! {
3307!   /**
3308!    * TODO: Flushing of quques
3309!    */
3310!
3311  }
3312 
3313+ /**
3314+  * Opens the device in different modes. The supported modes are
3315+  * 1. Polling
3316+  * 2. Interrupt
3317+  * 3. DMA
3318+  * At exit the uart_Exit function will be called to flush the device.
3319+  *
3320+  * @param major Major number of the device
3321+  * @param minor Minor number of the device
3322+  * @param arg
3323+  * @return
3324+  */
3325  rtems_device_driver bfin_uart_open(rtems_device_major_number major,
3326!     rtems_device_minor_number minor, void *arg) {
3327!   rtems_status_code             sc    = RTEMS_NOT_DEFINED;;
3328!   rtems_libio_open_close_args_t *args = NULL;
3329!
3330!   /**
3331!    * Callback function for polling
3332!    */
3333    static const rtems_termios_callbacks pollCallbacks = {
3334!       NULL,                        /* firstOpen */
3335!       NULL,                        /* lastClose */
3336!       pollRead,                    /* pollRead */
3337!       pollWrite,                   /* write */
3338!       setAttributes,               /* setAttributes */
3339!       NULL,                        /* stopRemoteTx */
3340!       NULL,                        /* startRemoteTx */
3341!       TERMIOS_POLLED               /* outputUsesInterrupts */
3342    };
3343+
3344+   /**
3345+    * Callback function for interrupt based transfers without DMA.
3346+    * We use interrupts for writing only. For reading we use polling.
3347+    */
3348    static const rtems_termios_callbacks interruptCallbacks = {
3349!       NULL,                        /* firstOpen */
3350!       NULL,                        /* lastClose */
3351!       pollRead,                    /* pollRead */
3352!       uart_interruptWrite,              /* write */
3353!       setAttributes,               /* setAttributes */
3354!       NULL,                        /* stopRemoteTx */
3355!       NULL,                        /* startRemoteTx */
3356!       TERMIOS_IRQ_DRIVEN           /* outputUsesInterrupts */
3357!   };
3358!
3359!   /**
3360!    * Callback function for interrupt based DMA transfers.
3361!    * We use interrupts for writing only. For reading we use polling.
3362!    */
3363!   static const rtems_termios_callbacks interruptDmaCallbacks = {
3364!       NULL,                        /* firstOpen */
3365!       NULL,                        /* lastClose */
3366!       NULL,                        /* pollRead */
3367!       uart_DmaWrite,              /* write */
3368!       setAttributes,               /* setAttributes */
3369!       NULL,                        /* stopRemoteTx */
3370!       NULL,                        /* startRemoteTx */
3371!       TERMIOS_IRQ_DRIVEN           /* outputUsesInterrupts */
3372    };
3373 
3374!
3375!   if ( NULL == uartsConfig || 0 > minor || minor >= uartsConfig->num_channels) {
3376      return RTEMS_INVALID_NUMBER;
3377+   }
3378+
3379+   /**
3380+    * Opens device for handling uart send request either by
3381+    * 1. interrupt with DMA
3382+    * 2. interrupt based
3383+    * 3. Polling
3384+    */
3385+   if ( uartsConfig->channels[minor].uart_useDma ) {
3386+     sc = rtems_termios_open(major, minor, arg, &interruptDmaCallbacks);
3387+   } else {
3388+     sc = rtems_termios_open(major, minor, arg,
3389+         uartsConfig->channels[minor].uart_useInterrupts ?
3390+             &interruptCallbacks : &pollCallbacks);
3391+   }
3392 
3393    args = arg;
3394    uartsConfig->channels[minor].termios = args->iop->data1;
3395 
3396!   atexit(uart_exit);
3397 
3398    return sc;
3399  }
3400 
3401+
3402+ /**
3403+ * Uart initialization function.
3404+ * @param major major number of the device
3405+ * @param config configuration parameters
3406+ * @return rtems status code
3407+ */
3408+ rtems_status_code bfin_uart_initialize(rtems_device_major_number major,
3409+     bfin_uart_config_t *config) {
3410+   rtems_status_code sc = RTEMS_NOT_DEFINED;
3411+   int               i  = 0;
3412+
3413+   rtems_termios_initialize();
3414+
3415+   /*
3416+    *  Register Device Names
3417+    */
3418+   uartsConfig = config;
3419+   for (i = 0; i < config->num_channels; i++) {
3420+     config->channels[i].termios = NULL;
3421+     config->channels[i].flags = 0;
3422+     initializeHardware(&(config->channels[i]));
3423+     sc = rtems_io_register_name(config->channels[i].name, major, i);
3424+     if (RTEMS_SUCCESSFUL != sc) {
3425+       return sc;
3426+     }
3427+   }
3428+
3429+   return sc;
3430+ }
3431diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/c/src/lib/libcpu/bfin/serial/uart.h rtems/c/src/lib/libcpu/bfin/serial/uart.h
3432*** rtems-4.10.0/c/src/lib/libcpu/bfin/serial/uart.h    2009-11-30 00:03:49.000000000 -0500
3433--- rtems/c/src/lib/libcpu/bfin/serial/uart.h   2011-04-12 18:05:42.000000000 -0400
3434***************
3435*** 8,35 ****
3436   *  found in the file LICENSE in this distribution or at
3437   *  http://www.rtems.com/license/LICENSE.
3438   *
3439!  *  $Id: uart.h,v 1.3 2009/11/30 05:03:49 ralf Exp $
3440   */
3441 
3442! #ifndef _uart_h_
3443! #define _uart_h_
3444 
3445 
3446  #ifdef __cplusplus
3447  extern "C" {
3448  #endif
3449 
3450!
3451  typedef struct {
3452!   const char *name;
3453!   void *base_address;
3454!   bool  use_interrupts;
3455!   int force_baud;
3456!   /* the following are for internal use */
3457!   void *termios;
3458!   uint8_t volatile flags;
3459  } bfin_uart_channel_t;
3460 
3461  typedef struct {
3462    uint32_t freq;
3463    int num_channels;
3464--- 8,45 ----
3465   *  found in the file LICENSE in this distribution or at
3466   *  http://www.rtems.com/license/LICENSE.
3467   *
3468!  *  Modified:
3469!  *  $Author: rkangral $ Added interrupt support and DMA support
3470!  *
3471!  *  $Id: uart.h 47 2011-04-12 22:05:42Z rkangral $
3472   */
3473 
3474!
3475! #ifndef _UART_H_
3476! #define _UART_H_
3477 
3478 
3479  #ifdef __cplusplus
3480  extern "C" {
3481  #endif
3482 
3483! /** bfin_uart_channel object
3484!  */
3485  typedef struct {
3486!   const char        *name;                 /** Holds name of the device */
3487!   uint32_t          uart_baseAddress;           /** UART base address */
3488!   uint32_t          uart_rxDmaBaseAddress;      /** RX DMA base address */
3489!   uint32_t          uart_txDmaBaseAddress;      /** TX DMA base address */
3490!   bool              uart_useInterrupts;         /** are interrupts used */
3491!   bool              uart_useDma;                /** is dma used */
3492!   int               uart_baud;                  /** baud rate, 0 for default */
3493!
3494!   void              *termios;                   /** termios associated */
3495!   uint8_t volatile  flags;                      /** flags for internal use */
3496!   uint16_t          length;                     /** length for internal use */
3497  } bfin_uart_channel_t;
3498 
3499+
3500  typedef struct {
3501    uint32_t freq;
3502    int num_channels;
3503***************
3504*** 36,59 ****
3505    bfin_uart_channel_t *channels;
3506  } bfin_uart_config_t;
3507 
3508 
3509! char bfin_uart_poll_read(int minor);
3510 
3511  void bfin_uart_poll_write(int minor, char c);
3512 
3513  rtems_status_code bfin_uart_initialize(rtems_device_major_number major,
3514!                                        bfin_uart_config_t *config);
3515 
3516  rtems_device_driver bfin_uart_open(rtems_device_major_number major,
3517!                                    rtems_device_minor_number minor,
3518!                                    void *arg);
3519 
3520! void bfin_uart_isr(int source);
3521 
3522 
3523  #ifdef __cplusplus
3524  }
3525  #endif
3526 
3527! #endif /* _uart_h_ */
3528 
3529--- 46,140 ----
3530    bfin_uart_channel_t *channels;
3531  } bfin_uart_config_t;
3532 
3533+ /**
3534+  * @param base_address defines the UART base address
3535+  * @param source defines the source that caused the interrupt. This argument
3536+  * will help us in identifying if Rx or TX caused the interrupt.
3537+  */
3538+ typedef struct {
3539+   uint32_t base_address;
3540+   int source;
3541+ } bfin_uart_arg_t;
3542+
3543 
3544!
3545! char bfin_uart_poll_read(rtems_device_minor_number minor);
3546 
3547  void bfin_uart_poll_write(int minor, char c);
3548 
3549+
3550+ /**
3551+ * Uart initialization function.
3552+ * @param major major number of the device
3553+ * @param config configuration parameters
3554+ * @return rtems status code
3555+ */
3556  rtems_status_code bfin_uart_initialize(rtems_device_major_number major,
3557!     bfin_uart_config_t *config);
3558!
3559!
3560 
3561+ /**
3562+  * Opens the device in different modes. The supported modes are
3563+  * 1. Polling
3564+  * 2. Interrupt
3565+  * 3. DMA
3566+  * At exit the uart_Exit function will be called to flush the device.
3567+  *
3568+  * @param major Major number of the device
3569+  * @param minor Minor number of the device
3570+  * @param arg
3571+  * @return
3572+  */
3573  rtems_device_driver bfin_uart_open(rtems_device_major_number major,
3574!     rtems_device_minor_number minor, void *arg);
3575!
3576!
3577!
3578! /**
3579!  * This function implements TX dma ISR. It clears the IRQ and dequeues a char
3580!  * The channel argument will have the base address. Since there are two uart
3581!  * and both the uarts can use the same tx dma isr.
3582!  *
3583!  * TODO: 1. Error checking 2. sending correct length ie after looking at the
3584!  * number of elements the uart transmitted.
3585!  *
3586!  * @param _arg argument passed to the interrupt handler. It contains the
3587!  * channel argument.
3588!  */
3589! void bfinUart_txDmaIsr(void *_arg);
3590!
3591!
3592!
3593! /**
3594!  * RX DMA ISR.
3595!  * The polling route is used for receiving the characters. This is a place
3596!  * holder for future implementation.
3597!  * @param _arg
3598!  */
3599! void bfinUart_rxDmaIsr(void *_arg);
3600!
3601!
3602! /**
3603!  * This function implements TX ISR. The function gets called when the TX FIFO is
3604!  * empty. It clears the interrupt and dequeues the character. It only tx one
3605!  * character at a time.
3606!  *
3607!  * TODO: error handling.
3608!  * @param _arg gets the channel information.
3609!  */
3610! void bfinUart_txIsr(void *_arg);
3611!
3612 
3613! /**
3614! * This function implements RX ISR
3615! */
3616! void bfinUart_rxIsr(void *_arg);
3617 
3618 
3619  #ifdef __cplusplus
3620  }
3621  #endif
3622 
3623! #endif /* _UART_H_ */
3624 
3625diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/cpukit/score/cpu/bfin/ChangeLog rtems/cpukit/score/cpu/bfin/ChangeLog
3626*** rtems-4.10.0/cpukit/score/cpu/bfin/ChangeLog        2010-04-20 09:27:48.000000000 -0400
3627--- rtems/cpukit/score/cpu/bfin/ChangeLog       2011-04-20 11:31:22.000000000 -0400
3628***************
3629*** 1,3 ****
3630--- 1,10 ----
3631+ 2011-04-20  Rohan Kangralkar <rkangral@ece.neu.edu>
3632+
3633+   * bfin/rtems/bf52x.h: This file defines basic MMR for the Blackfin 52x CPU.
3634+      The MMR have been taken from the ADSP-BF52x Blackfin Processor
3635+      Hardware Reference from Analog Devices. Mentioned Chapters
3636+      refer to this Documentation.
3637+
3638  2010-04-20    Allan Hessenflow <allanh@kallisti.com>
3639 
3640        * cpu_asm.S: L0-L3 were part of the interrupt context, but as
3641diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/cpukit/score/cpu/bfin/Makefile.am rtems/cpukit/score/cpu/bfin/Makefile.am
3642*** rtems-4.10.0/cpukit/score/cpu/bfin/Makefile.am      2010-03-27 10:59:26.000000000 -0400
3643--- rtems/cpukit/score/cpu/bfin/Makefile.am     2011-04-20 11:31:22.000000000 -0400
3644***************
3645*** 8,14 ****
3646  include_rtems_HEADERS = rtems/asm.h
3647 
3648  include_rtems_bfindir = $(includedir)/rtems/bfin
3649! include_rtems_bfin_HEADERS = rtems/bfin/bfin.h rtems/bfin/bf533.h
3650 
3651  include_rtems_scoredir = $(includedir)/rtems/score
3652  include_rtems_score_HEADERS = rtems/score/cpu.h rtems/score/bfin.h \
3653--- 8,15 ----
3654  include_rtems_HEADERS = rtems/asm.h
3655 
3656  include_rtems_bfindir = $(includedir)/rtems/bfin
3657! include_rtems_bfin_HEADERS = rtems/bfin/bfin.h rtems/bfin/bf533.h \
3658!     rtems/bfin/bf52x.h
3659 
3660  include_rtems_scoredir = $(includedir)/rtems/score
3661  include_rtems_score_HEADERS = rtems/score/cpu.h rtems/score/bfin.h \
3662diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/cpukit/score/cpu/bfin/preinstall.am rtems/cpukit/score/cpu/bfin/preinstall.am
3663*** rtems-4.10.0/cpukit/score/cpu/bfin/preinstall.am    2011-02-08 11:13:15.000000000 -0500
3664--- rtems/cpukit/score/cpu/bfin/preinstall.am   2011-02-14 18:39:06.000000000 -0500
3665***************
3666*** 35,40 ****
3667--- 35,44 ----
3668        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/bfin/bf533.h
3669  PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/bfin/bf533.h
3670 
3671+ $(PROJECT_INCLUDE)/rtems/bfin/bf52x.h: rtems/bfin/bf52x.h $(PROJECT_INCLUDE)/rtems/bfin/$(dirstamp)
3672+       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/bfin/bf52x.h
3673+ PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/bfin/bf52x.h
3674+
3675  $(PROJECT_INCLUDE)/rtems/score/$(dirstamp):
3676        @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score
3677        @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
3678diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/cpukit/score/cpu/bfin/rtems/bfin/bf52x.h rtems/cpukit/score/cpu/bfin/rtems/bfin/bf52x.h
3679*** rtems-4.10.0/cpukit/score/cpu/bfin/rtems/bfin/bf52x.h       1969-12-31 19:00:00.000000000 -0500
3680--- rtems/cpukit/score/cpu/bfin/rtems/bfin/bf52x.h      2011-02-22 17:19:49.000000000 -0500
3681***************
3682*** 0 ****
3683--- 1,431 ----
3684+ /**
3685+  *@file bf52x.h
3686+  *
3687+  *  This file defines basic MMR for the Blackfin 52x CPU.
3688+  *  The MMR have been taken from the ADSP-BF52x Blackfin Processor
3689+  *  Hardware Reference from Analog Devices. Mentioned Chapters
3690+  *  refer to this Documentation.
3691+  *
3692+  *    Based on bf533.h
3693+  *
3694+  *  COPYRIGHT (c) 2006.
3695+  *  Atos Automacao Industrial LTDA.
3696+  *             modified by Alain Schaefer <alain.schaefer@easc.ch>
3697+  *                     and Antonio Giovanini <antonio@atos.com.br>
3698+  *
3699+  *  The license and distribution terms for this file may be
3700+  *  found in the file LICENSE in this distribution or at
3701+  *  http://www.rtems.com/license/LICENSE.
3702+  *
3703+  *
3704+  * @author    Rohan Kangralkar, ECE Department Northeastern University
3705+  * @date        02/15/2011
3706+  *
3707+  * HISTORY:
3708+  * $Id$
3709+  *
3710+  *
3711+  */
3712+
3713+ #ifndef _RTEMS_BFIN_52x_H
3714+ #define _RTEMS_BFIN_52x_H
3715+
3716+ #include <rtems/bfin/bfin.h>
3717+
3718+ #ifdef __cplusplus
3719+ extern "C" {
3720+ #endif
3721+
3722+
3723+ /* Clock and System Control  Chapter 8 */
3724+ #define PLL_CTL                0xFFC00000L
3725+ #define PLL_DIV                0xFFC00004L
3726+ #define VR_CTL                 0xFFC00008L
3727+ #define PLL_STAT               0xFFC0000CL
3728+ #define PLL_LOCKCNT            0xFFC00010L
3729+ #define SWRST                  0xFFC00100L
3730+ #define SYSCR                  0xFFC00104L
3731+
3732+ /* SPI Controller           Chapter 10 */
3733+ #define SPI_CTL                0xFFC00500L
3734+ #define SPI_FLG                0xFFC00504L
3735+ #define SPI_STAT               0xFFC00508L
3736+ #define SPI_TDBR               0xFFC0050CL
3737+ #define SPI_RDBR               0xFFC00510L
3738+ #define SPI_BAUD               0xFFC00514L
3739+ #define SPI_SHADOW             0xFFC00518L
3740+
3741+ /* SPORT0 Controller */
3742+ #define SPORT0_TCR1            0xFFC00800L
3743+ #define SPORT0_TCR2            0xFFC00804L
3744+ #define SPORT0_TCLKDIV         0xFFC00808L
3745+ #define SPORT0_TFSDIV          0xFFC0080CL
3746+ #define SPORT0_TX              0xFFC00810L
3747+ #define SPORT0_RX              0xFFC00818L
3748+ #define SPORT0_RCR1            0xFFC00820L
3749+ #define SPORT0_RCR2            0xFFC00824L
3750+ #define SPORT0_RCLKDIV         0xFFC00828L
3751+ #define SPORT0_RFSDIV          0xFFC0082CL
3752+ #define SPORT0_STAT            0xFFC00830L
3753+ #define SPORT0_CHNL            0xFFC00834L
3754+ #define SPORT0_MCMC1           0xFFC00838L
3755+ #define SPORT0_MCMC2           0xFFC0083CL
3756+ #define SPORT0_MTCS0           0xFFC00840L
3757+ #define SPORT0_MTCS1           0xFFC00844L
3758+ #define SPORT0_MTCS2           0xFFC00848L
3759+ #define SPORT0_MTCS3           0xFFC0084CL
3760+ #define SPORT0_MRCS0           0xFFC00850L
3761+ #define SPORT0_MRCS1           0xFFC00854L
3762+ #define SPORT0_MRCS2           0xFFC00858L
3763+ #define SPORT0_MRCS3           0xFFC0085CL
3764+
3765+ /* Parallel Peripheral Interface (PPI) Chapter 11 */
3766+
3767+ #define PPI_CONTROL            0xFFC01000L
3768+ #define PPI_STATUS             0xFFC01004L
3769+ #define PPI_COUNT              0xFFC01008L
3770+ #define PPI_DELAY              0xFFC0100CL
3771+ #define PPI_FRAME              0xFFC01010L
3772+
3773+ /*********  PPI MASKS ***********/
3774+ /*  PPI_CONTROL Masks */
3775+ #define PORT_EN                0x00000001
3776+ #define PORT_DIR               0x00000002
3777+ #define XFR_TYPE               0x0000000C
3778+ #define PORT_CFG               0x00000030
3779+ #define FLD_SEL                0x00000040
3780+ #define PACK_EN                0x00000080
3781+ #define DMA32                  0x00000100
3782+ #define SKIP_EN                0x00000200
3783+ #define SKIP_EO                0x00000400
3784+ #define DLENGTH                0x00003800
3785+ #define DLEN_8                 0x0
3786+ #define DLEN(x)                (((x-9) & 0x07) << 11)
3787+ #define POL                    0x0000C000
3788+
3789+ /* PPI_STATUS Masks */
3790+ #define FLD                    0x00000400
3791+ #define FT_ERR                 0x00000800
3792+ #define OVR                    0x00001000
3793+ #define UNDR                   0x00002000
3794+ #define ERR_DET                0x00004000
3795+ #define ERR_NCOR               0x00008000
3796+
3797+ /* SPORT1 Controller        Chapter 12 */
3798+ #define SPORT1_TCR1            0xFFC00900L
3799+ #define SPORT1_TCR2            0xFFC00904L
3800+ #define SPORT1_TCLKDIV         0xFFC00908L
3801+ #define SPORT1_TFSDIV          0xFFC0090CL
3802+ #define SPORT1_TX              0xFFC00910L
3803+ #define SPORT1_RX              0xFFC00918L
3804+ #define SPORT1_RCR1            0xFFC00920L
3805+ #define SPORT1_RCR2            0xFFC00924L
3806+ #define SPORT1_RCLKDIV         0xFFC00928L
3807+ #define SPORT1_RFSDIV          0xFFC0092CL
3808+ #define SPORT1_STAT            0xFFC00930L
3809+ #define SPORT1_CHNL            0xFFC00934L
3810+ #define SPORT1_MCMC1           0xFFC00938L
3811+ #define SPORT1_MCMC2           0xFFC0093CL
3812+ #define SPORT1_MTCS0           0xFFC00940L
3813+ #define SPORT1_MTCS1           0xFFC00944L
3814+ #define SPORT1_MTCS2           0xFFC00948L
3815+ #define SPORT1_MTCS3           0xFFC0094CL
3816+ #define SPORT1_MRCS0           0xFFC00950L
3817+ #define SPORT1_MRCS1           0xFFC00954L
3818+ #define SPORT1_MRCS2           0xFFC00958L
3819+ #define SPORT1_MRCS3           0xFFC0095CL
3820+
3821+ /* SPORTx_TCR1 Masks */
3822+ #define TSPEN                  0x0001
3823+ #define ITCLK                  0x0002
3824+ #define TDTYPE                 0x000C
3825+ #define TLSBIT                 0x0010
3826+ #define ITFS                   0x0200
3827+ #define TFSR                   0x0400
3828+ #define DITFS                  0x0800
3829+ #define LTFS                   0x1000
3830+ #define LATFS                  0x2000
3831+ #define TCKFE                  0x4000
3832+
3833+ /* SPORTx_TCR2 Masks */
3834+ #define SLEN                   0x001F
3835+ #define TXSE                   0x0100
3836+ #define TSFSE                  0x0200
3837+ #define TRFST                  0x0400
3838+
3839+ /* SPORTx_RCR1 Masks */
3840+ #define RSPEN                  0x0001
3841+ #define IRCLK                  0x0002
3842+ #define RDTYPE                 0x000C
3843+ #define RULAW                  0x0008
3844+ #define RALAW                  0x000C
3845+ #define RLSBIT                 0x0010
3846+ #define IRFS                   0x0200
3847+ #define RFSR                   0x0400
3848+ #define LRFS                   0x1000
3849+ #define LARFS                  0x2000
3850+ #define RCKFE                  0x4000
3851+
3852+ /* SPORTx_RCR2 Masks */
3853+ #define SLEN                   0x001F
3854+ #define RXSE                   0x0100
3855+ #define RSFSE                  0x0200
3856+ #define RRFST                  0x0400
3857+
3858+ /* SPORTx_STAT Masks */
3859+ #define RXNE                   0x0001
3860+ #define RUVF                   0x0002
3861+ #define ROVF                   0x0004
3862+ #define TXF                    0x0008
3863+ #define TUVF                   0x0010
3864+ #define TOVF                   0x0020
3865+ #define TXHRE                  0x0040
3866+
3867+ /* SPORTx_MCMC1 Masks */
3868+ #define WSIZE                  0x0000F000
3869+ #define WOFF                   0x000003FF
3870+
3871+ /* SPORTx_MCMC2 Masks */
3872+ #define MCCRM                  0x00000003
3873+ #define MCDTXPE                0x00000004
3874+ #define MCDRXPE                0x00000008
3875+ #define MCMEN                  0x00000010
3876+ #define FSDR                   0x00000080
3877+ #define MFD                    0x0000F000
3878+
3879+ /* UART Controller          Chapter 13 */
3880+ #define UART_THR               0xFFC00400L
3881+ #define UART_RBR               0xFFC00400L
3882+ #define UART_DLL               0xFFC00400L
3883+ #define UART_IER               0xFFC00404L
3884+ #define UART_DLH               0xFFC00404L
3885+ #define UART_IIR               0xFFC00408L
3886+ #define UART_LCR               0xFFC0040CL
3887+ #define UART_MCR               0xFFC00410L
3888+ #define UART_LSR               0xFFC00414L
3889+ #define UART_SCR               0xFFC0041CL
3890+ #define UART_GCTL              0xFFC00424L
3891+
3892+ /*
3893+  * UART CONTROLLER MASKS
3894+  */
3895+
3896+ /* UART_LCR */
3897+ #define DLAB                   0x80
3898+ #define SB                     0x40
3899+ #define STP                    0x20
3900+ #define EPS                    0x10
3901+ #define PEN                    0x08
3902+ #define STB                    0x04
3903+ #define WLS(x)                 ((x-5) & 0x03)
3904+
3905+ #define DLAB_P                 0x07
3906+ #define SB_P                   0x06
3907+ #define STP_P                  0x05
3908+ #define EPS_P                  0x04
3909+ #define PEN_P                  0x03
3910+ #define STB_P                  0x02
3911+ #define WLS_P1                 0x01
3912+ #define WLS_P0                 0x00
3913+
3914+ /* UART_MCR */
3915+ #define LOOP_ENA               0x10
3916+ #define LOOP_ENA_P             0x04
3917+
3918+ /* UART_LSR */
3919+ #define TEMT                   0x40
3920+ #define THRE                   0x20
3921+ #define BI                     0x10
3922+ #define FE                     0x08
3923+ #define PE                     0x04
3924+ #define OE                     0x02
3925+ #define DR                     0x01
3926+
3927+ #define TEMP_P                 0x06
3928+ #define THRE_P                 0x05
3929+ #define BI_P                   0x04
3930+ #define FE_P                   0x03
3931+ #define PE_P                   0x02
3932+ #define OE_P                   0x01
3933+ #define DR_P                   0x00
3934+
3935+ /* UART_IER */
3936+ #define ELSI                   0x04
3937+ #define ETBEI                  0x02
3938+ #define ERBFI                  0x01
3939+
3940+ #define ELSI_P                 0x02
3941+ #define ETBEI_P                0x01
3942+ #define ERBFI_P                0x00
3943+
3944+ /* UART_IIR */
3945+ #define STATUS(x)              ((x << 1) & 0x06)
3946+ #define NINT                   0x01
3947+ #define STATUS_P1              0x02
3948+ #define STATUS_P0              0x01
3949+ #define NINT_P                 0x00
3950+
3951+ /* UART_GCTL */
3952+ #define FFE                    0x20
3953+ #define FPE                    0x10
3954+ #define RPOLC                  0x08
3955+ #define TPOLC                  0x04
3956+ #define IREN                   0x02
3957+ #define UCEN                   0x01
3958+
3959+ #define FFE_P                  0x05
3960+ #define FPE_P                  0x04
3961+ #define RPOLC_P                0x03
3962+ #define TPOLC_P                0x02
3963+ #define IREN_P                 0x01
3964+ #define UCEN_P                 0x00
3965+
3966+ /* General Purpose IO        Chapter 14*/
3967+ #define FIO_FLAG_D             0xFFC00700L
3968+ #define FIO_FLAG_C             0xFFC00704L
3969+ #define FIO_FLAG_S             0xFFC00708L
3970+ #define FIO_FLAG_T             0xFFC0070CL
3971+ #define FIO_MASKA_D            0xFFC00710L
3972+ #define FIO_MASKA_C            0xFFC00714L
3973+ #define FIO_MASKA_S            0xFFC00718L
3974+ #define FIO_MASKA_T            0xFFC0071CL
3975+ #define FIO_MASKB_D            0xFFC00720L
3976+ #define FIO_MASKB_C            0xFFC00724L
3977+ #define FIO_MASKB_S            0xFFC00728L
3978+ #define FIO_MASKB_T            0xFFC0072CL
3979+ #define FIO_DIR                0xFFC00730L
3980+ #define FIO_POLAR              0xFFC00734L
3981+ #define FIO_EDGE               0xFFC00738L
3982+ #define FIO_BOTH               0xFFC0073CL
3983+ #define FIO_INEN               0xFFC00740L
3984+
3985+
3986+ /* General Purpose IO        Chapter 9*/
3987+ #define PORTH_FER              0xFFC03208
3988+ #define PORTH_MUX              0xFFC03218
3989+ #define PORTHIO_DIR            0xFFC01730
3990+ #define PORTHIO_INEN           0xFFC01740
3991+ #define PORTHIO                0xFFC01700
3992+ #define PORTHIO_SET            0xFFC01708
3993+ #define PORTHIO_CLEAR          0xFFC01704
3994+ #define PORTHIO_TOGGLE         0xFFC0170C
3995+
3996+
3997+ #define FIO_INEN               0xFFC00740L
3998+ #define FIO_POLAR              0xFFC00734L
3999+ #define FIO_EDGE               0xFFC00738L
4000+ #define FIO_BOTH               0xFFC0073CL
4001+
4002+
4003+
4004+ #define FIO_FLAG_C             0xFFC00704L
4005+ #define FIO_FLAG_S             0xFFC00708L
4006+ #define FIO_FLAG_T             0xFFC0070CL
4007+ #define FIO_MASKA_D            0xFFC00710L
4008+ #define FIO_MASKA_C            0xFFC00714L
4009+ #define FIO_MASKA_S            0xFFC00718L
4010+ #define FIO_MASKA_T            0xFFC0071CL
4011+ #define FIO_MASKB_D            0xFFC00720L
4012+ #define FIO_MASKB_C            0xFFC00724L
4013+ #define FIO_MASKB_S            0xFFC00728L
4014+ #define FIO_MASKB_T            0xFFC0072CL
4015+
4016+
4017+ /*  General Purpose IO Masks */
4018+ #define PF0                    0x0001
4019+ #define PF1                    0x0002
4020+ #define PF2                    0x0004
4021+ #define PF3                    0x0008
4022+ #define PF4                    0x0010
4023+ #define PF5                    0x0020
4024+ #define PF6                    0x0040
4025+ #define PF7                    0x0080
4026+ #define PF8                    0x0100
4027+ #define PF9                    0x0200
4028+ #define PF10                   0x0400
4029+ #define PF11                   0x0800
4030+ #define PF12                   0x1000
4031+ #define PF13                   0x2000
4032+ #define PF14                   0x4000
4033+ #define PF15                   0x8000
4034+
4035+
4036+ /* TIMER 0, 1, 2            Chapter 15 */
4037+ #define TIMER0_CONFIG          0xFFC00600L
4038+ #define TIMER0_COUNTER         0xFFC00604L
4039+ #define TIMER0_PERIOD          0xFFC00608L
4040+ #define TIMER0_WIDTH           0xFFC0060CL
4041+
4042+ #define TIMER1_CONFIG          0xFFC00610L
4043+ #define TIMER1_COUNTER         0xFFC00614L
4044+ #define TIMER1_PERIOD          0xFFC00618L
4045+ #define TIMER1_WIDTH           0xFFC0061CL
4046+
4047+ #define TIMER2_CONFIG          0xFFC00620L
4048+ #define TIMER2_COUNTER         0xFFC00624L
4049+ #define TIMER2_PERIOD          0xFFC00628L
4050+ #define TIMER2_WIDTH           0xFFC0062CL
4051+
4052+ #define TIMER_ENABLE           0xFFC00640L
4053+ #define TIMER_DISABLE          0xFFC00644L
4054+ #define TIMER_STATUS           0xFFC00648L
4055+
4056+ /* Real Time Clock          Chapter 16 */
4057+ #define RTC_STAT               0xFFC00300L
4058+ #define RTC_ICTL               0xFFC00304L
4059+ #define RTC_ISTAT              0xFFC00308L
4060+ #define RTC_SWCNT              0xFFC0030CL
4061+ #define RTC_ALARM              0xFFC00310L
4062+ #define RTC_FAST               0xFFC00314L
4063+ #define RTC_PREN               0xFFC00314L
4064+
4065+ /* RTC_FAST Mask (RTC_PREN Mask) */
4066+ #define ENABLE_PRESCALE        0x00000001
4067+ #define PREN                   0x00000001
4068+
4069+ /* Asynchronous Memory Controller EBUI, Chapter 17*/
4070+ #define EBIU_AMGCTL            0xFFC00A00L
4071+ #define EBIU_AMBCTL0           0xFFC00A04L
4072+ #define EBIU_AMBCTL1           0xFFC00A08L
4073+
4074+ /* SDRAM Controller External Bus Interface Unit */
4075+
4076+ #define EBIU_SDGCTL            0xFFC00A10L
4077+ #define EBIU_SDBCTL            0xFFC00A14L
4078+ #define EBIU_SDRRC             0xFFC00A18L
4079+ #define EBIU_SDSTAT            0xFFC00A1CL
4080+
4081+
4082+
4083+
4084+ /* DCPLB_DATA and ICPLB_DATA Registers */
4085+ /*** Bit Positions */
4086+ #define CPLB_VALID_P            0x00000000  /* 0=invalid entry, 1=valid entry */
4087+ #define CPLB_LOCK_P             0x00000001  /* 0=entry may be replaced, 1=entry locked */
4088+ #define CPLB_USER_RD_P          0x00000002  /* 0=no read access, 1=read access allowed (user mode) */
4089+ /*** Masks */
4090+ #define CPLB_VALID             0x00000001  /* 0=invalid entry, 1=valid entry */
4091+ #define CPLB_LOCK              0x00000002  /* 0=entry may be replaced, 1=entry locked */
4092+ #define CPLB_USER_RD           0x00000004  /* 0=no read access, 1=read access allowed (user mode) */
4093+ #define PAGE_SIZE_1KB          0x00000000  /* 1 KB page size */
4094+ #define PAGE_SIZE_4KB          0x00010000  /* 4 KB page size */
4095+ #define PAGE_SIZE_1MB          0x00020000  /* 1 MB page size */
4096+ #define PAGE_SIZE_4MB          0x00030000  /* 4 MB page size */
4097+ #define CPLB_PORTPRIO             0x00000200  /* 0=low priority port, 1= high priority port */
4098+ #define CPLB_L1_CHBL           0x00001000  /* 0=non-cacheable in L1, 1=cacheable in L1 */
4099+ /*** ICPLB_DATA only */
4100+ #define CPLB_LRUPRIO              0x00000100  /* 0=can be replaced by any line, 1=priority for non-replacement */
4101+ /*** DCPLB_DATA only */
4102+ #define CPLB_USER_WR           0x00000008  /* 0=no write access, 0=write access allowed (user mode) */
4103+ #define CPLB_SUPV_WR           0x00000010  /* 0=no write access, 0=write access allowed (supervisor mode) */
4104+ #define CPLB_DIRTY             0x00000080  /* 1=dirty, 0=clean */
4105+ #define CPLB_L1_AOW                       0x00008000  /* 0=do not allocate cache lines on write-through writes,  */
4106+                                                                                   /* 1= allocate cache lines on write-through writes. */
4107+ #define CPLB_WT                0x00004000  /* 0=write-back, 1=write-through */
4108+
4109+
4110+ #ifdef __cplusplus
4111+ }
4112+ #endif
4113+
4114+ #endif /* _RTEMS_SCORE_BFIN_H */
4115diff -crBN -X /home/student/rkangral/exclude rtems-4.10.0/cpukit/score/cpu/bfin/rtems/score/cpu.h rtems/cpukit/score/cpu/bfin/rtems/score/cpu.h
4116*** rtems-4.10.0/cpukit/score/cpu/bfin/rtems/score/cpu.h        2010-04-17 15:24:16.000000000 -0400
4117--- rtems/cpukit/score/cpu/bfin/rtems/score/cpu.h       2011-02-22 17:19:20.000000000 -0500
4118***************
4119*** 625,631 ****
4120   *
4121   *  XXX document implementation including references if appropriate
4122   */
4123! #define CPU_STACK_MINIMUM_SIZE          (1024*4)
4124 
4125  /**
4126   *  CPU's worst alignment requirement for data types on a byte boundary.  This
4127--- 625,631 ----
4128   *
4129   *  XXX document implementation including references if appropriate
4130   */
4131! #define CPU_STACK_MINIMUM_SIZE          (1024*8)
4132 
4133  /**
4134   *  CPU's worst alignment requirement for data types on a byte boundary.  This
4135***************
4136*** 693,699 ****
4137   *
4138   *  XXX document implementation including references if appropriate
4139   */
4140! #define CPU_STACK_ALIGNMENT        0
4141 
4142  /*
4143   *  ISR handler macros
4144--- 693,699 ----
4145   *
4146   *  XXX document implementation including references if appropriate
4147   */
4148! #define CPU_STACK_ALIGNMENT        8
4149 
4150  /*
4151   *  ISR handler macros