Ticket #1781: patch_v1.0

File patch_v1.0, 125.9 KB (added by Rohan, on Apr 19, 2011 at 5:43:47 PM)

Blackfin 52X patch

Line 
1diff -crBN -X exclude rtems_orig/c/src/lib/libbsp/bfin/bf537Stamp/console/console.c rtems/c/src/lib/libbsp/bfin/bf537Stamp/console/console.c
2*** rtems_orig/c/src/lib/libbsp/bfin/bf537Stamp/console/console.c       2011-04-19 11:04:26.000000000 -0400
3--- rtems/c/src/lib/libbsp/bfin/bf537Stamp/console/console.c    2011-03-15 16:59:39.000000000 -0400
4***************
5*** 7,13 ****
6   *  found in the file LICENSE in this distribution or at
7   *  http://www.rtems.com/license/LICENSE.
8   *
9!  *  $Id: console.c,v 1.5 2009/12/11 04:10:27 ralf Exp $
10   */
11 
12 
13--- 7,13 ----
14   *  found in the file LICENSE in this distribution or at
15   *  http://www.rtems.com/license/LICENSE.
16   *
17!  *  $Id: console.c 36 2011-03-15 20:59:39Z rkangral $
18   */
19 
20 
21***************
22*** 26,41 ****
23  */
24 
25  static bfin_uart_channel_t channels[] = {
26!   {"/dev/console",
27!    (char *) UART0_BASE_ADDRESS,
28!    CONSOLE_USE_INTERRUPTS,
29! #ifdef CONSOLE_FORCE_BAUD
30!    CONSOLE_FORCE_BAUD,
31! #else
32!    0,
33! #endif
34!    NULL,
35!    0}
36 
37  #if (!BFIN_ON_SKYEYE)
38  ,
39--- 26,46 ----
40  */
41 
42  static bfin_uart_channel_t channels[] = {
43!     {"/dev/console",
44!      UART0_BASE_ADDRESS,
45!      0,
46!      0,
47!      CONSOLE_USE_INTERRUPTS,
48!      0,
49!   #ifdef CONSOLE_FORCE_BAUD
50!      CONSOLE_FORCE_BAUD,
51!   #else
52!      0,
53!   #endif
54!      NULL,
55!      0,
56!      0}
57!   };
58 
59  #if (!BFIN_ON_SKYEYE)
60  ,
61***************
62*** 56,65 ****
63 
64  #if CONSOLE_USE_INTERRUPTS
65  static bfin_isr_t bfinUARTISRs[] = {
66!   {SIC_DMA8_UART0_RX_VECTOR, bfin_uart_isr, 0, 0, NULL},
67!   {SIC_DMA10_UART1_RX_VECTOR, bfin_uart_isr, 0, 0, NULL},
68!   {SIC_DMA9_UART0_TX_VECTOR, bfin_uart_isr, 0, 0, NULL},
69!   {SIC_DMA11_UART1_TX_VECTOR, bfin_uart_isr, 0, 0, NULL}
70  };
71  #endif
72 
73--- 61,70 ----
74 
75  #if CONSOLE_USE_INTERRUPTS
76  static bfin_isr_t bfinUARTISRs[] = {
77!   {SIC_DMA8_UART0_RX_VECTOR, bfinUart_rxIsr, 0, 0, NULL},
78!   {SIC_DMA10_UART1_RX_VECTOR, bfinUart_rxIsr, 0, 0, NULL},
79!   {SIC_DMA9_UART0_TX_VECTOR, bfinUart_txIsr, 0, 0, NULL},
80!   {SIC_DMA11_UART1_TX_VECTOR, bfinUart_txIsr, 0, 0, NULL}
81  };
82  #endif
83 
84diff -crBN -X exclude rtems_orig/c/src/lib/libbsp/bfin/eZKit533/console/console-io.c rtems/c/src/lib/libbsp/bfin/eZKit533/console/console-io.c
85*** rtems_orig/c/src/lib/libbsp/bfin/eZKit533/console/console-io.c      2011-04-19 11:04:26.000000000 -0400
86--- rtems/c/src/lib/libbsp/bfin/eZKit533/console/console-io.c   2011-03-15 16:59:39.000000000 -0400
87***************
88*** 11,17 ****
89   *  found in the file LICENSE in this distribution or at
90   *  http://www.rtems.com/license/LICENSE.
91   *
92!  *  $Id: console-io.c,v 1.5 2009/12/11 04:09:43 ralf Exp $
93   */
94 
95 
96--- 11,17 ----
97   *  found in the file LICENSE in this distribution or at
98   *  http://www.rtems.com/license/LICENSE.
99   *
100!  *  $Id: console-io.c 36 2011-03-15 20:59:39Z rkangral $
101   */
102 
103 
104***************
105*** 26,39 ****
106 
107  static bfin_uart_channel_t channels[] = {
108    {"/dev/console",
109!    (char *) UART0_BASE_ADDRESS,
110     CONSOLE_USE_INTERRUPTS,
111  #ifdef CONSOLE_FORCE_BAUD
112     CONSOLE_FORCE_BAUD,
113  #else
114     0,
115  #endif
116     NULL,
117     0}
118  };
119 
120--- 26,43 ----
121 
122  static bfin_uart_channel_t channels[] = {
123    {"/dev/console",
124!    UART0_BASE_ADDRESS,
125!    0,
126!    0,
127     CONSOLE_USE_INTERRUPTS,
128+    0,
129  #ifdef CONSOLE_FORCE_BAUD
130     CONSOLE_FORCE_BAUD,
131  #else
132     0,
133  #endif
134     NULL,
135+    0,
136     0}
137  };
138 
139***************
140*** 45,52 ****
141 
142  #if CONSOLE_USE_INTERRUPTS
143  static bfin_isr_t bfinUARTISRs[] = {
144!   {SIC_DMA6_UART0_RX_VECTOR, bfin_uart_isr, 0, 0, NULL},
145!   {SIC_DMA7_UART0_TX_VECTOR, bfin_uart_isr, 0, 0, NULL},
146  };
147  #endif
148 
149--- 49,56 ----
150 
151  #if CONSOLE_USE_INTERRUPTS
152  static bfin_isr_t bfinUARTISRs[] = {
153!   {SIC_DMA6_UART0_RX_VECTOR, bfinUart_rxIsr, 0, 0, NULL},
154!   {SIC_DMA7_UART0_TX_VECTOR, bfinUart_txIsr, 0, 0, NULL},
155  };
156  #endif
157 
158diff -crBN -X exclude rtems_orig/c/src/lib/libbsp/bfin/TLL6527M/bsp_specs rtems/c/src/lib/libbsp/bfin/TLL6527M/bsp_specs
159*** rtems_orig/c/src/lib/libbsp/bfin/TLL6527M/bsp_specs 1969-12-31 19:00:00.000000000 -0500
160--- rtems/c/src/lib/libbsp/bfin/TLL6527M/bsp_specs      2011-02-25 15:53:20.000000000 -0500
161***************
162*** 0 ****
163--- 1,10 ----
164+ %rename endfile old_endfile
165+ %rename startfile old_startfile
166+ %rename link old_link
167+
168+ *startfile:
169+ %{!qrtems: %(old_startfile)} \
170+ %{!nostdlib: %{qrtems: start.o%s -e __start}}
171+
172+ *link:
173+ %{!qrtems: %(old_link)} %{qrtems: -dc -dp -N}
174diff -crBN -X exclude rtems_orig/c/src/lib/libbsp/bfin/TLL6527M/configure.ac rtems/c/src/lib/libbsp/bfin/TLL6527M/configure.ac
175*** rtems_orig/c/src/lib/libbsp/bfin/TLL6527M/configure.ac      1969-12-31 19:00:00.000000000 -0500
176--- rtems/c/src/lib/libbsp/bfin/TLL6527M/configure.ac   2011-03-15 16:59:39.000000000 -0400
177***************
178*** 0 ****
179--- 1,47 ----
180+ ## Process this file with autoconf to produce a configure script.
181+ ##
182+ ## $Id: configure.ac 36 2011-03-15 20:59:39Z rkangral $
183+
184+ AC_PREREQ(2.68)
185+ AC_INIT([rtems-c-src-lib-libbsp-bfin-TLL6527M],[_RTEMS_VERSION],[http://www.rtems.org/bugzilla])
186+ AC_CONFIG_SRCDIR([bsp_specs])
187+ RTEMS_TOP(../../../../../..)
188+
189+ RTEMS_CANONICAL_TARGET_CPU
190+ AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.11.1])
191+ RTEMS_BSP_CONFIGURE
192+
193+ RTEMS_PROG_CC_FOR_TARGET
194+ RTEMS_CANONICALIZE_TOOLS
195+ RTEMS_PROG_CCAS
196+
197+ ## bsp-specific options
198+ RTEMS_BSPOPTS_SET([CONSOLE_USE_INTERRUPTS],[*],[1])
199+ RTEMS_BSPOPTS_HELP([CONSOLE_USE_INTERRUPTS],
200+ [The console driver can operate in either polled or interrupt mode.])
201+
202+ RTEMS_BSPOPTS_SET([UART_USE_DMA],[*],[1])
203+ RTEMS_BSPOPTS_HELP([UART_USE_DMA],
204+ [The uart driver can operate in dma mode with interrupts.
205+ Set to 1 if DMA operation is required ])
206+
207+ RTEMS_BSPOPTS_SET([CONSOLE_BAUDRATE],[*],[9600])
208+ RTEMS_BSPOPTS_HELP([CONSOLE_BAUDRATE],
209+ [The baudrate of the console uart.])
210+
211+ RTEMS_BSPOPTS_SET([INTERRUPT_USE_TABLE],[*],[1])
212+ RTEMS_BSPOPTS_HELP([INTERRUPT_USE_TABLE],
213+ [Select if INTERRUPT use table or link list])
214+
215+
216+
217+ RTEMS_BSPOPTS_SET([BFIN_ON_SKYEYE],[*],[0])
218+ RTEMS_BSPOPTS_HELP([BFIN_ON_SKYEYE],
219+ [(BSP--Skyeye)
220+  If defined, disable features which are not supported on Skyeye.])
221+
222+ RTEMS_BSP_CLEANUP_OPTIONS(0, 0)
223+
224+ # Explicitly list all Makefiles here
225+ AC_CONFIG_FILES([Makefile])
226+ AC_OUTPUT
227diff -crBN -X exclude rtems_orig/c/src/lib/libbsp/bfin/TLL6527M/console/console.c rtems/c/src/lib/libbsp/bfin/TLL6527M/console/console.c
228*** rtems_orig/c/src/lib/libbsp/bfin/TLL6527M/console/console.c 1969-12-31 19:00:00.000000000 -0500
229--- rtems/c/src/lib/libbsp/bfin/TLL6527M/console/console.c      2011-04-19 11:00:07.000000000 -0400
230***************
231*** 0 ****
232--- 1,182 ----
233+ /**
234+  *@file console.c
235+  *
236+  *@brief
237+  *  - This file implements uart console for TLL6527M. TLL6527M has BF527 with
238+  *  second uart (uart-1) connected to the console.
239+  *
240+  * Target:   TLL6527v1-0
241+  * Compiler:
242+  *
243+  * COPYRIGHT (c) 2010 by ECE Northeastern University.
244+  *
245+  * The license and distribution terms for this file may be
246+  * found in the file LICENSE in this distribution or at
247+  * http://www.rtems.com/license
248+  *
249+  * @author Rohan Kangralkar, ECE, Northeastern University
250+  *         (kangralkar.r@husky.neu.edu)
251+  *
252+  * LastChange:
253+  * $Id: console.c 48 2011-04-19 15:00:07Z rkangral $
254+  *
255+  */
256+
257+ #include <rtems.h>
258+ #include <rtems/libio.h>
259+ #include <bsp.h>
260+ #include <rtems/bspIo.h>
261+
262+ #include <bsp/interrupt.h>
263+ #include <libcpu/uart.h>
264+
265+ /***************************************************
266+ LOCAL DEFINES
267+  ***************************************************/
268+
269+
270+ /***************************************************
271+ STATIC GLOBALS
272+  ***************************************************/
273+ /**
274+  * Declaration of UART
275+  */
276+ static bfin_uart_channel_t channels[] = {
277+   {"/dev/console",
278+     UART1_BASE_ADDRESS,
279+     DMA10_BASE_ADDRESS,
280+     DMA11_BASE_ADDRESS,
281+     CONSOLE_USE_INTERRUPTS,
282+     UART_USE_DMA,
283+     CONSOLE_BAUDRATE,
284+     NULL,
285+     0,
286+     0}
287+ };
288+
289+ /**
290+  * Over all configuration
291+  */
292+ static bfin_uart_config_t config = {
293+     SCLK,
294+     sizeof(channels) / sizeof(channels[0]),
295+     channels
296+ };
297+
298+
299+ #if CONSOLE_USE_INTERRUPTS
300+ /**
301+  * The Rx and Tx isr will get the same argument
302+  * The isr will have to find if it was the rx that caused the interrupt or
303+  * the tx
304+  */
305+ static bfin_isr_t bfinUARTISRs[] = {
306+ #if UART_USE_DMA
307+     /* For First uart */
308+     {IRQ_DMA10_UART1_RX, bfinUart_rxDmaIsr, (void *)&channels[0], 0},
309+     {IRQ_DMA11_UART1_TX, bfinUart_txDmaIsr, (void *)&channels[0], 0},
310+     /* For second uart */
311+ #else
312+     /* For First uart */
313+     {IRQ_DMA10_UART1_RX, bfinUart_rxIsr, &channels[0], 0},
314+     {IRQ_DMA11_UART1_TX, bfinUart_txIsr, &channels[0], 0},
315+     /* For second uart */
316+ #endif
317+ };
318+ #endif
319+
320+
321+ static void TLL6527_BSP_output_char(char c) {
322+
323+   bfin_uart_poll_write(0, c);
324+ }
325+
326+ static int TLL6527_BSP_poll_char(void) {
327+
328+   return bfin_uart_poll_read(0);
329+ }
330+
331+ BSP_output_char_function_type     BSP_output_char = TLL6527_BSP_output_char;
332+ BSP_polling_getchar_function_type BSP_poll_char   = TLL6527_BSP_poll_char;
333+
334+
335+
336+ rtems_device_driver console_close(rtems_device_major_number major,
337+     rtems_device_minor_number minor,
338+     void *arg) {
339+
340+   return rtems_termios_close(arg);
341+ }
342+
343+ rtems_device_driver console_read(rtems_device_major_number major,
344+     rtems_device_minor_number minor,
345+     void *arg) {
346+
347+   return rtems_termios_read(arg);
348+ }
349+
350+ rtems_device_driver console_write(rtems_device_major_number major,
351+     rtems_device_minor_number minor,
352+     void *arg) {
353+
354+   return rtems_termios_write(arg);
355+ }
356+
357+ rtems_device_driver console_control(rtems_device_major_number major,
358+     rtems_device_minor_number minor,
359+     void *arg) {
360+
361+   return rtems_termios_ioctl(arg);
362+ }
363+
364+
365+
366+ /*
367+  *  Open entry point
368+  */
369+ rtems_device_driver console_open(rtems_device_major_number major,
370+     rtems_device_minor_number minor,
371+     void *arg) {
372+
373+   return bfin_uart_open(major, minor, arg);
374+ }
375+
376+
377+
378+ /**
379+  *
380+  * This routine initializes the console IO driver.
381+  *
382+  * Parameters
383+  * @param major major number
384+  * @param minor minor number
385+  *
386+  * Output parameters:  NONE
387+  *
388+  * @return void
389+  */
390+ rtems_device_driver console_initialize(rtems_device_major_number major,
391+     rtems_device_minor_number minor,
392+     void *arg) {
393+   rtems_status_code status = RTEMS_NOT_DEFINED;
394+ #if CONSOLE_USE_INTERRUPTS
395+   int               i      = 0;
396+ #endif
397+
398+   status = bfin_uart_initialize(major, &config);
399+   if (status != RTEMS_SUCCESSFUL) {
400+     rtems_fatal_error_occurred(status);
401+   }
402+
403+ #if CONSOLE_USE_INTERRUPTS
404+   for (i = 0; i < sizeof(bfinUARTISRs) / sizeof(bfinUARTISRs[0]); i++) {
405+     bfin_interrupt_register(&bfinUARTISRs[i]);
406+ #if INTERRUPT_USE_TABLE
407+ #else
408+     bfin_interrupt_enable(&bfinUARTISRs[i], 1);
409+ #endif
410+   }
411+ #endif
412+
413+   return RTEMS_SUCCESSFUL;
414+ }
415diff -crBN -X exclude rtems_orig/c/src/lib/libbsp/bfin/TLL6527M/include/bsp.h rtems/c/src/lib/libbsp/bfin/TLL6527M/include/bsp.h
416*** rtems_orig/c/src/lib/libbsp/bfin/TLL6527M/include/bsp.h     1969-12-31 19:00:00.000000000 -0500
417--- rtems/c/src/lib/libbsp/bfin/TLL6527M/include/bsp.h  2011-04-19 11:00:07.000000000 -0400
418***************
419*** 0 ****
420--- 1,79 ----
421+ /**
422+  *@file bsp.h
423+  * 
424+  *  This include file contains all board IO definitions for TLL6527M.
425+  *
426+  * COPYRIGHT (c) 2010 by ECE Northeastern University.
427+  *
428+  * The license and distribution terms for this file may be
429+  * found in the file LICENSE in this distribution or at
430+  * http://www.rtems.com/license
431+  *
432+  *  $Id: bsp.h 48 2011-04-19 15:00:07Z rkangral $
433+  */
434
435+
436+ #ifndef _BSP_H
437+ #define _BSP_H
438+
439+
440+ #ifdef __cplusplus
441+ extern "C" {
442+ #endif
443+
444+ #include <bspopts.h>
445+
446+ #include <rtems.h>
447+ #include <rtems/console.h>
448+ #include <rtems/clockdrv.h>
449+ #include <rtems/score/bfin.h>
450+ #include <rtems/bfin/bf52x.h>
451+ #include <bf52x.h>
452+
453+
454+ /*
455+  * PLL and clock setup values:
456+  */
457+
458+ /*
459+  *  PLL configuration for TLL6527M
460+  *
461+  *  XTL   =  27 MHz
462+  *  CLKIN =  13 MHz
463+  *  VCO   = 391 MHz
464+  *  CCLK  = 391 MHz
465+  *  SCLK  = 130 MHz
466+  */
467+
468+ #define PLL_CSEL    0x0000      /* CCLK = VCO      */
469+ #define PLL_SSEL    0x0003      /* SCLK = CCLK/3   */
470+ #define PLL_MSEL    0x3A00      /* VCO = 29xCLKIN  */
471+ #define PLL_DF      0x0001      /* CLKIN = XTL/2   */
472+
473+ #define CLKIN             (25000000)  /* Input clock to the PLL */
474+ #define CCLK        (600000000)   /* CORE CLOCK     */
475+ #define SCLK        (100000000)   /* SYSTEM CLOCK   */
476+
477+ /*
478+  * UART setup values
479+  */
480+ #define BAUDRATE    57600       /* Console Baudrate   */
481+ #define WORD_5BITS  0x00        /* 5 bits word        */
482+ #define WORD_6BITS  0x01        /* 6 bits word        */
483+ #define WORD_7BITS  0x02        /* 7 bits word        */
484+ #define WORD_8BITS  0x03        /* 8 bits word        */
485+ #define EVEN_PARITY 0x18        /* Enable EVEN parity */
486+ #define ODD_PARITY  0x08        /* Enable ODD parity  */
487+ #define TWO_STP_BIT 0x04        /* 2 stop bits        */
488+
489+ rtems_isr_entry set_vector(                     /* returns old vector */
490+   rtems_isr_entry     handler,                  /* isr routine        */
491+   rtems_vector_number vector,                   /* vector number      */
492+   int                 type                      /* RTEMS or RAW intr  */
493+ );
494+
495+ #ifdef __cplusplus
496+ }
497+ #endif
498+
499+ #endif
500diff -crBN -X exclude rtems_orig/c/src/lib/libbsp/bfin/TLL6527M/include/cplb.h rtems/c/src/lib/libbsp/bfin/TLL6527M/include/cplb.h
501*** rtems_orig/c/src/lib/libbsp/bfin/TLL6527M/include/cplb.h    1969-12-31 19:00:00.000000000 -0500
502--- rtems/c/src/lib/libbsp/bfin/TLL6527M/include/cplb.h 2011-02-25 15:46:42.000000000 -0500
503***************
504*** 0 ****
505--- 1,34 ----
506+ /*  cplb.h
507+  * 
508+  *  Copyright (c) 2006 by Atos Automacao Industrial Ltda.
509+  *             written by Alain Schaefer <alain.schaefer@easc.ch>
510+  *
511+  *  The license and distribution terms for this file may be
512+  *  found in the file LICENSE in this distribution or at
513+  *  http://www.rtems.com/license/LICENSE.
514+  *
515+  *  $Id: cplb.h 27 2011-02-25 20:46:42Z rkangral $
516+  */
517+ #ifndef _CPLB_H
518+ #define _CPLB_H
519+
520+ /* CPLB configurations */
521+ #define CPLB_DEF_CACHE_WT     CPLB_L1_CHBL | CPLB_WT
522+ #define CPLB_DEF_CACHE_WB     CPLB_L1_CHBL
523+ #define CPLB_CACHE_ENABLED    CPLB_L1_CHBL | CPLB_DIRTY
524+
525+ #define CPLB_DEF_CACHE                CPLB_L1_CHBL | CPLB_WT
526+ #define CPLB_ALL_ACCESS       CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
527+
528+ #define CPLB_I_PAGE_MGMT      CPLB_LOCK | CPLB_VALID
529+ #define CPLB_D_PAGE_MGMT      CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
530+
531+ #define CPLB_DNOCACHE         CPLB_ALL_ACCESS | CPLB_VALID
532+ #define CPLB_DDOCACHE         CPLB_DNOCACHE | CPLB_DEF_CACHE
533+ #define CPLB_INOCACHE         CPLB_USER_RD | CPLB_VALID
534+ #define CPLB_IDOCACHE         CPLB_INOCACHE | CPLB_L1_CHBL
535+
536+ #define CPLB_DDOCACHE_WT      CPLB_DNOCACHE | CPLB_DEF_CACHE_WT
537+ #define CPLB_DDOCACHE_WB      CPLB_DNOCACHE | CPLB_DEF_CACHE_WB
538+
539+ #endif /* _CPLB_H */
540diff -crBN -X exclude rtems_orig/c/src/lib/libbsp/bfin/TLL6527M/include/tm27.h rtems/c/src/lib/libbsp/bfin/TLL6527M/include/tm27.h
541*** rtems_orig/c/src/lib/libbsp/bfin/TLL6527M/include/tm27.h    1969-12-31 19:00:00.000000000 -0500
542--- rtems/c/src/lib/libbsp/bfin/TLL6527M/include/tm27.h 2011-04-19 11:00:07.000000000 -0400
543***************
544*** 0 ****
545--- 1,37 ----
546+ /*
547+  *  tm27.h
548+  *
549+  * COPYRIGHT (c) 2010 by ECE Northeastern University.
550+  *
551+  * The license and distribution terms for this file may be
552+  * found in the file LICENSE in this distribution or at
553+  * http://www.rtems.com/license
554+  *
555+  *  $Id: tm27.h 48 2011-04-19 15:00:07Z rkangral $
556+  */
557+
558+ #ifndef _RTEMS_TMTEST27
559+ #error "This is an RTEMS internal file you must not include directly."
560+ #endif
561+
562+ #ifndef __tm27_h
563+ #define __tm27_h
564+
565+ /*
566+  *  Define the interrupt mechanism for Time Test 27
567+  */
568+
569+ #define MUST_WAIT_FOR_INTERRUPT 0
570+
571+ #define Install_tm27_vector(handler) \
572+ { \
573+   set_vector( handler, 0x06, 1 ); \
574+ }
575+
576+ #define Cause_tm27_intr() asm volatile("raise 0x06;" : :);
577+
578+ #define Clear_tm27_intr() /* empty */
579+
580+ #define Lower_tm27_intr() /* empty */
581+
582+ #endif
583diff -crBN -X exclude rtems_orig/c/src/lib/libbsp/bfin/TLL6527M/make/custom/TLL6527M.cfg rtems/c/src/lib/libbsp/bfin/TLL6527M/make/custom/TLL6527M.cfg
584*** rtems_orig/c/src/lib/libbsp/bfin/TLL6527M/make/custom/TLL6527M.cfg  1969-12-31 19:00:00.000000000 -0500
585--- rtems/c/src/lib/libbsp/bfin/TLL6527M/make/custom/TLL6527M.cfg       2011-02-25 15:55:50.000000000 -0500
586***************
587*** 0 ****
588--- 1,19 ----
589+ #
590+ #  Config file for Blackfin TLL6527M
591+ #
592+ #  $Id: TLL6527M.cfg 29 2011-02-25 20:55:50Z rkangral $
593+ #
594+
595+ include $(RTEMS_ROOT)/make/custom/default.cfg
596+
597+ RTEMS_CPU=bfin
598+ RTEMS_CPU_MODEL=bf52x
599+
600+ #  This contains the compiler options necessary to select the CPU model
601+ #  and (hopefully) optimize for it.
602+ #
603+ CPU_CFLAGS =-mcpu=bf527
604+
605+ # optimize flag: typically -O2
606+ # gcc-4.2.0 segfaults on -OX > -O0
607+ CFLAGS_OPTIMIZE_V = -O2 -g
608diff -crBN -X exclude rtems_orig/c/src/lib/libbsp/bfin/TLL6527M/Makefile.am rtems/c/src/lib/libbsp/bfin/TLL6527M/Makefile.am
609*** rtems_orig/c/src/lib/libbsp/bfin/TLL6527M/Makefile.am       1969-12-31 19:00:00.000000000 -0500
610--- rtems/c/src/lib/libbsp/bfin/TLL6527M/Makefile.am    2011-04-19 11:00:07.000000000 -0400
611***************
612*** 0 ****
613--- 1,52 ----
614+ ##
615+ ## $Id: Makefile.am 48 2011-04-19 15:00:07Z rkangral $
616+ ##
617+
618+ ACLOCAL_AMFLAGS = -I ../../../../aclocal
619+
620+ include $(top_srcdir)/../../../../automake/compile.am
621+
622+ include_bspdir = $(includedir)/bsp
623+
624+ dist_project_lib_DATA = bsp_specs
625+
626+ include_HEADERS = include/bsp.h
627+ include_HEADERS += include/tm27.h
628+ include_HEADERS += include/cplb.h
629+
630+ nodist_include_HEADERS = include/bspopts.h
631+ nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
632+ DISTCLEANFILES = include/bspopts.h
633+
634+ noinst_PROGRAMS =
635+
636+ include_HEADERS += ../../shared/include/coverhd.h
637+
638+ noinst_LIBRARIES = libbspstart.a
639+ libbspstart_a_SOURCES = ../shared/start/start.S
640+ project_lib_DATA = start.$(OBJEXT)
641+
642+ dist_project_lib_DATA += startup/linkcmds
643+
644+ noinst_LIBRARIES += libbsp.a
645+
646+ libbsp_a_SOURCES = ../../shared/bsplibc.c ../../shared/bsppost.c \
647+   ../../shared/bsppredriverhook.c startup/bspstart.c \
648+   ../../shared/bspclean.c ../../shared/sbrk.c ../../shared/setvec.c \
649+   ../../shared/bootcard.c ../../shared/gnatinstallhandler.c \
650+   ../../shared/bspgetworkarea.c
651+
652+ libbsp_a_SOURCES += console/console.c
653+
654+ libbsp_a_LIBADD  = ../../../libcpu/@RTEMS_CPU@/mmu.rel
655+ libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/interrupt.rel
656+ libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/cache.rel
657+ libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/uart.rel
658+ libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/clock.rel
659+ libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/rtc.rel
660+ libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/timer.rel
661+
662+ EXTRA_DIST = times
663+
664+ include $(srcdir)/preinstall.am
665+ include $(top_srcdir)/../../../../automake/local.am
666diff -crBN -X exclude rtems_orig/c/src/lib/libbsp/bfin/TLL6527M/preinstall.am rtems/c/src/lib/libbsp/bfin/TLL6527M/preinstall.am
667*** rtems_orig/c/src/lib/libbsp/bfin/TLL6527M/preinstall.am     1969-12-31 19:00:00.000000000 -0500
668--- rtems/c/src/lib/libbsp/bfin/TLL6527M/preinstall.am  2011-02-25 15:53:20.000000000 -0500
669***************
670*** 0 ****
671--- 1,71 ----
672+ ## Automatically generated by ampolish3 - Do not edit
673+
674+ if AMPOLISH3
675+ $(srcdir)/preinstall.am: Makefile.am
676+       $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
677+ endif
678+
679+ PREINSTALL_DIRS =
680+ DISTCLEANFILES += $(PREINSTALL_DIRS)
681+
682+ all-local: $(TMPINSTALL_FILES)
683+
684+ TMPINSTALL_FILES =
685+ CLEANFILES = $(TMPINSTALL_FILES)
686+
687+ all-am: $(PREINSTALL_FILES)
688+
689+ PREINSTALL_FILES =
690+ CLEANFILES += $(PREINSTALL_FILES)
691+
692+ $(PROJECT_LIB)/$(dirstamp):
693+       @$(MKDIR_P) $(PROJECT_LIB)
694+       @: > $(PROJECT_LIB)/$(dirstamp)
695+ PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp)
696+
697+ $(PROJECT_INCLUDE)/$(dirstamp):
698+       @$(MKDIR_P) $(PROJECT_INCLUDE)
699+       @: > $(PROJECT_INCLUDE)/$(dirstamp)
700+ PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
701+
702+ $(PROJECT_INCLUDE)/bsp/$(dirstamp):
703+       @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp
704+       @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp)
705+ PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp)
706+
707+ $(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp)
708+       $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs
709+ PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs
710+
711+ $(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp)
712+       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h
713+ PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h
714+
715+ $(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
716+       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
717+ PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
718+
719+ $(PROJECT_INCLUDE)/cplb.h: include/cplb.h $(PROJECT_INCLUDE)/$(dirstamp)
720+       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/cplb.h
721+ PREINSTALL_FILES += $(PROJECT_INCLUDE)/cplb.h
722+
723+ $(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
724+       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
725+ PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h
726+
727+ $(PROJECT_INCLUDE)/bsp/bootcard.h: ../../shared/include/bootcard.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
728+       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bootcard.h
729+ PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bootcard.h
730+
731+ $(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp)
732+       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h
733+ PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h
734+
735+ $(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
736+       $(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT)
737+ TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT)
738+
739+ $(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp)
740+       $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds
741+ PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds
742+
743diff -crBN -X exclude rtems_orig/c/src/lib/libbsp/bfin/TLL6527M/README rtems/c/src/lib/libbsp/bfin/TLL6527M/README
744*** rtems_orig/c/src/lib/libbsp/bfin/TLL6527M/README    1969-12-31 19:00:00.000000000 -0500
745--- rtems/c/src/lib/libbsp/bfin/TLL6527M/README 2011-03-15 16:59:39.000000000 -0400
746***************
747*** 0 ****
748--- 1,96 ----
749+ #
750+ #  $Id: README 36 2011-03-15 20:59:39Z rkangral $
751+ #
752+
753+ BSP NAME:           TLL6527M
754+ BOARD:              TLL6527M
755+ CPU FAMILY:         Blackfin
756+ CPU:                Blackfin 527
757+ MODE:               32 bit mode
758+
759+ DEBUG MONITOR:     
760+ SIMULATOR:         
761+
762+ PERIPHERALS
763+ ===========
764+ TIMERS:             internal
765+   RESOLUTION:         1 milisecond
766+ SERIAL PORTS:       2 internal UART (polled/interrupt/dma)
767+ REAL-TIME CLOCK:    internal
768+ DMA:                internal
769+ VIDEO:              none
770+ SCSI:               none
771+ NETWORKING:         none
772+
773+
774+ DRIVER INFORMATION
775+ ==================
776+ CLOCK DRIVER:       internal
777+ TIMER DRIVER:       internal
778+ I2C:
779+ SPI:
780+ PPI:
781+ SPORT:
782+
783+
784+ STDIO
785+ =====
786+ PORT:               Console port 1
787+ ELECTRICAL:         RS-232
788+ BAUD:               9600
789+ BITS PER CHARACTER: 8
790+ PARITY:             None
791+ STOP BITS:          1
792+
793+ NOTES
794+ =====
795+ The TLL56527M board contains analog devices blackfin 527 processor. In addition
796+ to the peripherals provided by bf527 the board has a temprature sensor,
797+ accelerometer and power module connected via I2C. It also has LCD interface,
798+ Card reader interface.
799+
800+ The analog device bf52X family of processors are different from the bf53x range
801+ of processors. This port supports the additional features that are not
802+ supported by the blackfin 53X family of processors.
803+   
804+ The TLL6527M does not use the interrupt module used by the bfin 53x since it has
805+ an additional system interrupt controller isr registers for additional lines.
806+ On the 53X these line are multiplexed.
807+ The centralized interrupt handler is implemented to use lookup tables for
808+ jumping to the user ISR. For more details look at files implemented under
809+ libcpu/bfin/bf52x/interrupt/*
810+
811+ This port supports only the uart peripheral. The uart is supported via
812+ polling, DMA, interrupt. The uart file is generic and is common between the
813+ ports. Under bsp configure.ac files
814+ * change the CONSOLE_BAUDRATE or to choose among different baudrate.
815+ * Set UART_USE_DMA for UART to use DMA based transfers. In DMA based transfer
816+   chunk of buffer is transmitted at once and then an interrupt is generated.
817+ * Set CONSOLE_USE_INTERRUPTS to use interrupt based transfers. After every
818+   character is transmitted an interrupt is generated.
819+ * If CONSOLE_USE_INTERRUPTS, UART_USE_DMA are both not set then the port uses
820+   polling to transmit data over uart. This call is blocking.
821+
822+ TLL6527 specific file are mentioned below.
823+ =====================================
824+ c/src/lib/libcpu/bfin/bf52x/*
825+ c/src/lib/libbsp/bfin/TLL6527M/*
826+
827+
828+ The port was compiled using
829+ ===========================
830+ 1. bfin-rtems4.11-gcc (GCC) 4.5.2 20101216
831+               (RTEMS gcc-4.5.2-3.el5/newlib-1.19.0-1.el5)
832+ 2. automake (GNU automake) 1.11.1
833+ 3. autoconf (GNU Autoconf) 2.68
834+
835+
836+ The port was configured using the flags
837+ ==========================================
838+ --target=bfin-rtems4.11 --enable-rtemsbsp=TLL6527M --enable-tests=samples
839+ --disable-posix --disable-itron
840+       
841+
842+ ISSUES:
843+ Could not place code in l1code (SRAM) because it was not being loaded by the
844+ gnu loaded.
845\ No newline at end of file
846diff -crBN -X exclude rtems_orig/c/src/lib/libbsp/bfin/TLL6527M/startup/bspstart.c rtems/c/src/lib/libbsp/bfin/TLL6527M/startup/bspstart.c
847*** rtems_orig/c/src/lib/libbsp/bfin/TLL6527M/startup/bspstart.c        1969-12-31 19:00:00.000000000 -0500
848--- rtems/c/src/lib/libbsp/bfin/TLL6527M/startup/bspstart.c     2011-04-19 11:00:07.000000000 -0400
849***************
850*** 0 ****
851--- 1,207 ----
852+ /*  bspstart.c for TLL6527M
853+  *
854+  *  This routine starts the application.  It includes application,
855+  *  board, and monitor specific initialization and configuration.
856+  *  The generic CPU dependent initialization has been performed
857+  *  before this routine is invoked.
858+  * 
859+  * COPYRIGHT (c) 2010 by ECE Northeastern University.
860+  *
861+  * The license and distribution terms for this file may be
862+  * found in the file LICENSE in this distribution or at
863+  * http://www.rtems.com/license
864+  *
865+  *  $Id: bspstart.c 48 2011-04-19 15:00:07Z rkangral $
866+  */
867+
868+
869+ #include <bsp.h>
870+ #include <cplb.h>
871+ #include <bsp/interrupt.h>
872+ #include <libcpu/ebiuRegs.h>
873+
874+ const unsigned int dcplbs_table[16][2] = { 
875+   { 0xFFA00000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },
876+   { 0xFF900000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },/* L1 Data B */
877+   { 0xFF800000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },/* L1 Data A */
878+   { 0xFFB00000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },
879+
880+   { 0x20300000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },/* Async Memory Bank 3 */
881+   { 0x20200000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },/* Async Memory Bank 2  */
882+   { 0x20100000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },/* Async Memory Bank 1 */
883+   { 0x20000000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) }, /* Async Memory Bank 0 */
884+
885+   { 0x02400000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
886+   { 0x02000000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
887+   { 0x00C00000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
888+   { 0x00800000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
889+   { 0x00400000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
890+   { 0x00000000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
891+
892+   { 0xffffffff, 0xffffffff }/* end of section - termination */
893+ };
894+
895+
896+ const unsigned int _icplbs_table[16][2] = {
897+   { 0xFFA00000, (PAGE_SIZE_1MB | CPLB_I_PAGE_MGMT | CPLB_I_PAGE_MGMT | 0x4) },
898+   /* L1 Code */
899+   { 0xEF000000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, /* AREA DE BOOT */
900+   { 0xFFB00000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },
901+
902+   { 0x20300000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Memory Bank 3 */
903+   { 0x20200000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Bank 2 (Secnd) */
904+   { 0x20100000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Bank 1 (Prim B) */
905+   { 0x20000000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Bank 0 (Prim A) */
906+
907+   { 0x02400000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
908+   { 0x02000000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
909+   { 0x00C00000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
910+   { 0x00800000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
911+   { 0x00400000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
912+   { 0x00000000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
913+
914+   { 0xffffffff, 0xffffffff }/* end of section - termination */
915+ };
916+
917+ /*
918+  *  Use the shared implementations of the following routines
919+  */
920+
921+ void bsp_libc_init( void *, uint32_t, int );
922+ void Init_PLL (void);
923+ void Init_EBIU (void);
924+ void Init_Flags(void);
925+ void Init_RTC (void);
926+ void initCPLB(void);
927+
928+
929+ void null_isr(void);
930+
931+ /*
932+  *  Function:   bsp_pretasking_hook
933+  *  Created:    95/03/10
934+  *
935+  *  Description:
936+  *      BSP pretasking hook.  Called just before drivers are initialized.
937+  *      Used to setup libc and install any BSP extensions.
938+  *
939+  *  NOTES:
940+  *      Must not use libc (to do io) from here, since drivers are
941+  *      not yet initialized.
942+  *
943+  */
944+
945+ void bsp_pretasking_hook(void)
946+ {
947+   bfin_interrupt_init();
948+ }
949+
950+ /*
951+  *  bsp_start
952+  *
953+  *  This routine does the bulk of the system initialization.
954+  */
955+
956+ void bsp_start( void )
957+ {
958+   /* BSP Hardware Initialization*/
959+   Init_RTC();   /* Blackfin Real Time Clock initialization */ 
960+   Init_PLL();   /* PLL initialization */
961+   Init_EBIU();  /* EBIU initialization */
962+   Init_Flags(); /* GPIO initialization */
963+
964+   /*
965+    *  Allocate the memory for the RTEMS Work Space.  This can come from
966+    *  a variety of places: hard coded address, malloc'ed from outside
967+    *  RTEMS world (e.g. simulator or primitive memory manager), or (as
968+    *  typically done by stock BSPs) by subtracting the required amount
969+    *  of work space from the last physical address on the CPU board.
970+    */
971+   int i=0;
972+   for (i=5;i<16;i++) {
973+     set_vector((rtems_isr_entry)null_isr, i, 1);
974+   }
975+   
976+ }
977+
978+  /*
979+   * Init_PLL
980+   *
981+   * Routine to initialize the PLL. The TLL6527M uses a 25 Mhz XTAL.
982+   */
983+ void Init_PLL (void)
984+ {
985+   unsigned short msel = 0;
986+   unsigned short ssel = 0;
987+
988+   msel = (unsigned short)( (float)CCLK/(float)CLKIN );
989+   ssel = (unsigned short)( (float)(CLKIN*msel)/(float)SCLK);
990+   
991+   asm("cli r0;");
992+
993+   *((uint32_t*)SIC_IWR) = 0x1;
994+
995+   /* Configure PLL registers */
996+   *((uint16_t*)PLL_DIV) = ssel;;
997+   msel = msel<<9;
998+   *((uint16_t*)PLL_CTL) = msel;
999+
1000+   /* Commands to set PLL values */
1001+   asm("idle;");
1002+   asm("sti r0;");
1003+ }
1004+
1005+  /*
1006+   * Init_EBIU
1007+   *
1008+   * Configure extern memory
1009+   */
1010+
1011+ void Init_EBIU (void)
1012+ {
1013+   /* Check if SDRAM is already enabled */
1014+   if ( 0 != (*(uint16_t *)EBIU_SDSTAT & EBIU_SDSTAT_SDRS) ){
1015+     asm("ssync;");
1016+     /* RDIV = (100MHz*64ms)/8192-(6+3)=0x406 cycles */
1017+     *(uint16_t *)EBIU_SDRRC  = 0x3F6; /* SHould have been 0x306*/
1018+     *(uint16_t *)EBIU_SDBCTL = EBIU_SDBCTL_EBCAW_10 | EBIU_SDBCTL_EBSZ_64M |
1019+         EBIU_SDBCTL_EBE;
1020+     *(uint32_t *)EBIU_SDGCTL = 0x8491998d;
1021+     asm("ssync;");
1022+   } else {
1023+     /* SDRAm is already programmed */
1024+   }
1025+ }
1026+
1027+  /*
1028+   * Init_Flags
1029+   *
1030+   * Enable LEDs port
1031+   */
1032+ void Init_Flags(void)
1033+ {
1034+   *((uint16_t*)PORTH_FER)    = 0x0;
1035+   *((uint16_t*)PORTH_MUX)    = 0x0;
1036+   *((uint16_t*)PORTHIO_DIR)  = 0x1<<15;
1037+   *((uint16_t*)PORTHIO_SET)  = 0x1<<15;
1038+ }
1039+
1040+
1041+
1042+ void initCPLB(void) {
1043+
1044+        int i = 0;
1045+        unsigned int *addr;
1046+        unsigned int *data;
1047+         
1048+        addr = (unsigned int *)0xffe00100;
1049+        data = (unsigned int *)0xffe00200;
1050+
1051+        while ( dcplbs_table[i][0] != 0xffffffff ) {
1052+                *addr = dcplbs_table[i][0];
1053+                *data = dcplbs_table[i][1];
1054+
1055+                addr++;
1056+                data++;
1057+        }
1058+ }
1059diff -crBN -X exclude rtems_orig/c/src/lib/libbsp/bfin/TLL6527M/startup/linkcmds rtems/c/src/lib/libbsp/bfin/TLL6527M/startup/linkcmds
1060*** rtems_orig/c/src/lib/libbsp/bfin/TLL6527M/startup/linkcmds  1969-12-31 19:00:00.000000000 -0500
1061--- rtems/c/src/lib/libbsp/bfin/TLL6527M/startup/linkcmds       2011-04-12 18:05:09.000000000 -0400
1062***************
1063*** 0 ****
1064--- 1,154 ----
1065+ OUTPUT_FORMAT("elf32-bfin", "elf32-bfin",
1066+             "elf32-bfin")
1067+
1068+ OUTPUT_ARCH(bfin)
1069+ ENTRY(__start)
1070+
1071+ /*
1072+  * Declare some sizes.
1073+  */
1074+ _RamBase    = DEFINED(_RamBase)   ? _RamBase : 0x0;
1075+ _RamSize    = DEFINED(_RamSize)   ? _RamSize : 0x04000000;
1076+ _HeapSize   = DEFINED(_HeapSize)  ? _HeapSize : 0x10000;
1077+ _StackSize  = DEFINED(_StackSize) ? _StackSize : 0x10000;
1078+
1079+ MEMORY
1080+ {
1081+       sdram(rwx)      : ORIGIN = 0x00000100, LENGTH = 0x04000000
1082+       
1083+       l1dataA(rwx)    : ORIGIN = 0xff800000, LENGTH = 0x00004000
1084+       l1dataAC(rwx)   : ORIGIN = 0xff804000, LENGTH = 0x00004000
1085+       l1dataB(rwx)    : ORIGIN = 0xff900000, LENGTH = 0x00004000
1086+       l1dataBC(rwx)   : ORIGIN = 0xff904000, LENGTH = 0x00004000
1087+       
1088+       l1code(rwx)     : ORIGIN = 0xffa00000, LENGTH = 0x0000C000
1089+       l1codeC(rwx)    : ORIGIN = 0xffa10000, LENGTH = 0x00004000
1090+       scratchpad(rwx) : ORIGIN = 0xffb00000, LENGTH = 0x00001000
1091+ }
1092+
1093+ SECTIONS
1094+ {
1095+
1096+     .init          :
1097+     {
1098+       *(.l1code)
1099+         KEEP (*(.init))
1100+     } > sdram   /*=0*/
1101+
1102+     .text :
1103+     {
1104+          CREATE_OBJECT_SYMBOLS
1105+         *(.text)
1106+         *(.rodata*)
1107+         *(.gnu.linkonce.r*)
1108+         
1109+         /*
1110+          * Special FreeBSD sysctl sections.
1111+          */
1112+         . = ALIGN (16);
1113+         ___start_set_sysctl_set = .;
1114+         *(set_sysctl_*);
1115+         ___stop_set_sysctl_set = ABSOLUTE(.);
1116+         *(set_domain_*);
1117+         *(set_pseudo_*);
1118+
1119+          _etext = .;
1120+
1121+         ___CTOR_LIST__ = .;
1122+         LONG((___CTOR_END__ - ___CTOR_LIST__) / 4 - 2)
1123+         *(.ctors)
1124+         LONG(0)
1125+         ___CTOR_END__ = .;
1126+         ___DTOR_LIST__ = .;
1127+         LONG((___DTOR_END__ - ___DTOR_LIST__) / 4 - 2)
1128+         *(.dtors)
1129+         LONG(0)
1130+         ___DTOR_END__ = .;         
1131+     } > sdram
1132+     
1133+     .fini :
1134+     {
1135+         KEEP (*(.fini))
1136+     } > sdram  /*=0*/
1137+     
1138+     .data :
1139+     {
1140+         *(.data)
1141+         *(.jcr)
1142+         *(.gnu.linkonce.d*)
1143+         CONSTRUCTORS
1144+          _edata = .;
1145+     } > sdram
1146+
1147+     .eh_frame : { *(.eh_frame) } > sdram
1148+     .data1   : { *(.data1) } > sdram
1149+     .eh_frame : { *(.eh_frame) } > sdram
1150+     .gcc_except_table : { *(.gcc_except_table*) } > sdram
1151+
1152+     .rodata :
1153+     {
1154+         *(.rodata)
1155+         *(.rodata.*)
1156+         *(.gnu.linkonce.r*)
1157+     } > sdram
1158+
1159+     
1160+     .bss :
1161+     {
1162+          _bss_start = .;
1163+         _clear_start = .;
1164+         *(.bss)
1165+         *(.gnu.linkonce.b.*)
1166+         *(COMMON)
1167+         . = ALIGN (64);
1168+         _stack_init = .;
1169+         . += _StackSize;
1170+         _clear_end = .;
1171+         _WorkAreaBase = .;
1172+          _end = .;
1173+          __end = .;
1174+     } > sdram
1175+     
1176+ /* Debugging stuff follows */
1177+
1178+   /* Stabs debugging sections.  */
1179+   .stab 0 : { *(.stab) }
1180+   .stabstr 0 : { *(.stabstr) }
1181+   .stab.excl 0 : { *(.stab.excl) }
1182+   .stab.exclstr 0 : { *(.stab.exclstr) }
1183+   .stab.index 0 : { *(.stab.index) }
1184+   .stab.indexstr 0 : { *(.stab.indexstr) }
1185+   .comment 0 : { *(.comment) }
1186+   /* DWARF debug sections.
1187+      Symbols in the DWARF debugging sections are relative to the beginning
1188+      of the section so we begin them at 0.  */
1189+   /* DWARF 1 */
1190+   .debug          0 : { *(.debug) }
1191+   .line           0 : { *(.line) }
1192+   /* GNU DWARF 1 extensions */
1193+   .debug_srcinfo  0 : { *(.debug_srcinfo) }
1194+   .debug_sfnames  0 : { *(.debug_sfnames) }
1195+   /* DWARF 1.1 and DWARF 2 */
1196+   .debug_aranges  0 : { *(.debug_aranges) }
1197+   .debug_pubnames 0 : { *(.debug_pubnames) }
1198+   /* DWARF 2 */
1199+   .debug_info     0 : { *(.debug_info) }
1200+   .debug_abbrev   0 : { *(.debug_abbrev) }
1201+   .debug_line     0 : { *(.debug_line) }
1202+   .debug_frame    0 : { *(.debug_frame) }
1203+   .debug_str      0 : { *(.debug_str) }
1204+   .debug_loc      0 : { *(.debug_loc) }
1205+   .debug_macinfo  0 : { *(.debug_macinfo) }
1206+   /* SGI/MIPS DWARF 2 extensions */
1207+   .debug_weaknames 0 : { *(.debug_weaknames) }
1208+   .debug_funcnames 0 : { *(.debug_funcnames) }
1209+   .debug_typenames 0 : { *(.debug_typenames) }
1210+   .debug_varnames  0 : { *(.debug_varnames) }
1211+   /*.stack 0x80000 : { _stack = .; *(.stack) }*/
1212+   /* These must appear regardless of  .  */   
1213+ }
1214+
1215+ __HeapSize = _HeapSize;
1216+ __edata = _edata;
1217+ __etext = _etext;
1218+
1219diff -crBN -X exclude rtems_orig/c/src/lib/libbsp/bfin/TLL6527M/times rtems/c/src/lib/libbsp/bfin/TLL6527M/times
1220*** rtems_orig/c/src/lib/libbsp/bfin/TLL6527M/times     1969-12-31 19:00:00.000000000 -0500
1221--- rtems/c/src/lib/libbsp/bfin/TLL6527M/times  2011-04-12 18:05:09.000000000 -0400
1222***************
1223*** 0 ****
1224--- 1,179 ----
1225+ #
1226+ #  Timing Test Suite Results for TLL6527M
1227+ #
1228+ #
1229+ #  $Id: times 46 2011-04-12 22:05:09Z rkangral $
1230+ #
1231+
1232+ Board: TLL6527M
1233+ CPU: Blackfin 527
1234+ Clock Speed: 600 MHz
1235+ Memory Configuration: SDRAM 100 MHz
1236+
1237+
1238+ *** TIME TEST 1 ***
1239+ rtems_semaphore_create 8
1240+ rtems_semaphore_delete 4
1241+ rtems_semaphore_obtain: available 0
1242+ rtems_semaphore_obtain: not available -- NO_WAIT 0
1243+ rtems_semaphore_release: no waiting tasks 1
1244+ *** END OF TEST 1 ***
1245+
1246+
1247+ *** TIME TEST 2 ***
1248+ rtems_semaphore_obtain: not available -- caller blocks 8
1249+ *** END OF TEST 2 ***
1250+
1251+
1252+ *** TIME TEST 3 ***
1253+
1254+ *** TIME TEST 4 ***
1255+
1256+ *** TIME TEST 5 ***
1257+
1258+ *** TIME TEST 6 ***
1259+ rtems_task_restart: calling task 3
1260+ rtems_task_suspend: returns to caller 1
1261+ rtems_task_resume: task readied -- returns to caller 1
1262+ rtems_task_delete: ready task 15
1263+ *** END OF TEST 6 ***
1264+
1265+ *** TIME TEST 7 ***
1266+
1267+
1268+ *** TIME TEST 8 ***
1269+ rtems_task_set_priority: obtain current priorityrtems_task_mode: reschedule -- preempts caller 0   
1270+ rtems_task_set_priority: returns to caller  2
1271+ rtems_task_mode: obtain current mode101 0
1272+ rtems_task_mode: no reschedule 0
1273+ rtems_task_mode: reschedule -- returns to caller
1274+  2
1275+ rtems_task_set_note 1
1276+ rtems_task_get_note 0
1277+ rtems_clock_set 2
1278+ rtems_clock_get_tod 12
1279+ *** END OF TEST 8 ***
1280+
1281+
1282+ *** TIME TEST 9 ***
1283+ rtems_message_queue_create 43
1284+ rtems_message_queue_send: no waiting tasks 2
1285+ rtems_message_queue_urgent: no waiting tasks 2
1286+ rtems_message_queue_receive: available 2
1287+ rtems_message_queue_flush: no messages flushed 0
1288+ rtems_message_queue_flush: messages flushed 1
1289+ rtems_message_queue_delete 8
1290+ *** END OF TEST 9 ***
1291+
1292+ *** TIME TEST 10 ***
1293+ rtems_message_queue_receive: not available -- NO_WAITrtems_message_queue_receive: not available -- caller blocks 1
1294+  8
1295+ *** END OF TEST 10 ***
1296+
1297+ *** TIME TEST 11 ***
1298+
1299+ *** TIME TEST 12 ***
1300+
1301+ *** TIME TEST 13 ***
1302+
1303+ *** TIME TEST 14 ***
1304+
1305+ *** TIME TEST 15 ***
1306+ rtems_event_receive: obtain current eventsrtems_event_receive: not available -- caller blocks  07 
1307+
1308+ rtems_event_receive: not available -- NO_WAITrtems_event_send: n
1309+
1310+
1311+
1312+ *** TIME TEST 16 ***
1313+
1314+ *** TIME TEST 17 ***
1315+     
1316+     
1317+ *** TIME TEST 18 ***
1318+ rtems_task_delete: calling task 22
1319+ *** END OF TEST 18 ***
1320+
1321+
1322+ *** TIME TEST 19 ***
1323+ rtems_signal_catch 1
1324+ rtems_signal_send: returns to caller 2
1325+ rtems_signal_send: signal to self 8
1326+ exi
1327+
1328+
1329+
1330+ *** TIME TEST 20 ***                                                                               
1331+ rtems_partition_create 12                                                                         
1332+ rtems_region_creatertems_region_get_segment: not available -- caller blocks 15
1333+ rtems_partition_get_buffer: available 3
1334+ rtems_partition_get_buffer: not available15 1
1335+ rtems_partition_return_buffer 2
1336+
1337+ rtems_partition_delete 2
1338+ rtems_region_get_segment: available 5rtems_region_return_segment: task readied -- returns to caller
1339+  rtems_region_get_segment: not available -- NO_WAIT 5
1340+ rtems_region_return_segment: no waiting tasks3 4
1341+
1342+ Ack! Something bad happened to the Blackfin!
1343+
1344+ SEQUENCER STATUS:
1345+  SEQSTAT: 0000c021  IPEND: 8068  SYSCFG: 0006
1346+   HWERRCAUSE: 0x3: external memory addressing error
1347+   EXCAUSE   : 0x21: undef inst
1348+   physical IVG6 asserted : <0x00009542> /* unknown address */
1349+   physical IVG15 asserted : <0x00009690> /* unknown address */
1350+  RETE: <0x00000100> /* unknown address */
1351+  RETN: <0x92a330ab> { ___smulsi3_highpart + 0x8ead486f }
1352+  RETX: <0x12001940> { ___smulsi3_highpart + 0xe0a3104 }
1353+  RETS: <0x000095fa> /* unknown address */
1354+  RETI: <0x0d48338c> { ___smulsi3_highpart + 0x9524b50 }
1355+ DCPLB_FAULT_ADDR: <0x000318f0> /* unknown address */
1356+ ICPLB_FAULT_ADDR: <0x12001940> { ___smulsi3_highpart + 0xe0a3104 }
1357
1358
1359+
1360+ *** TIME TEST 21 ***                                                                               
1361+
1362+ rtems_region_create FAILED -- expected (successful completion) got (address specified is invalid)
1363+
1364+ *** TIME TEST 22 ***
1365+
1366+ *** TIME TEST 23 ***
1367+
1368+
1369+ *** TIME TEST 24 ***
1370+     
1371+     
1372+ *** TIME TEST 25 ***
1373+ rtems_clock_tick 5
1374+ *** END OF TEST 25 ***
1375+
1376+
1377+ *** TIME TEST 26 ***
1378+
1379+ *** TIME TEST 27 ***
1380+ interrupt entry overhead: returns to interrupted taskinterrupt entry overhead: returns to preempting task  22
1381+
1382+ interrupt exit overhead: returns to interrupted task
1383+
1384+
1385+ *** TIME TEST 28 ***
1386+ rtems_port_create 1
1387+ rtems_port_external_to_internal 0
1388+ rtems_port_internal_to_external 0
1389+ rtems_port_delete 1
1390+ *** END OF TEST 28 ***
1391+
1392+
1393+ *** TIME TEST 29 ***
1394+ rtems_rate_monotonic_create 6
1395+ rtems_rate_monotonic_period: initiate period -- returns to caller 10
1396+ rtems_rate_monotonic_period: obtain status 2
1397+ rtems_rate_monotonic_cancel 3
1398+ rtems_rate_monotonic_delete: inactive 6
1399+ rtems_rate_monotonic_delete: active 3
1400+ rtems_rate_monotonic_period: conclude periods -- caller blocks 9
1401+ *** END OF TEST 29 ***
1402+
1403+         
1404\ No newline at end of file
1405diff -crBN -X exclude rtems_orig/c/src/lib/libcpu/bfin/bf52x/include/bf52x.h rtems/c/src/lib/libcpu/bfin/bf52x/include/bf52x.h
1406*** rtems_orig/c/src/lib/libcpu/bfin/bf52x/include/bf52x.h      1969-12-31 19:00:00.000000000 -0500
1407--- rtems/c/src/lib/libcpu/bfin/bf52x/include/bf52x.h   2011-04-19 11:00:07.000000000 -0400
1408***************
1409*** 0 ****
1410--- 1,133 ----
1411+ /**
1412+  *@file bf52x.h
1413+  *
1414+  *@brief
1415+  *  - This file provides the register address for the 52X model. The file is
1416+  *  based on the 533 implementation with some addition to support 52X range of
1417+  *  processors.
1418+  *
1419+  * Target:   TLL6527v1-0
1420+  * Compiler:
1421+  *
1422+  * COPYRIGHT (c) 2010 by ECE Northeastern University.
1423+  *
1424+  * The license and distribution terms for this file may be
1425+  * found in the file LICENSE in this distribution or at
1426+  * http://www.rtems.com/license
1427+  *
1428+  * @author Rohan Kangralkar, ECE, Northeastern University
1429+  *         (kangralkar.r@husky.neu.edu)
1430+  *
1431+  * LastChange:
1432+  * $Id: bf52x.h 48 2011-04-19 15:00:07Z rkangral $
1433+  *
1434+  */
1435+
1436+ #ifndef _BF52X_H_
1437+ #define _BF52X_H_
1438+
1439+ /* register (or register block) addresses */
1440+
1441+ #define SIC_BASE_ADDRESS                          0xffc00100
1442+ #define WDOG_BASE_ADDRESS                         0xffc00200
1443+ #define RTC_BASE_ADDRESS                          0xffc00300
1444+ #define UART0_BASE_ADDRESS                        0xffc00400
1445+ #define UART1_BASE_ADDRESS                        0xffc02000
1446+ #define SPI_BASE_ADDRESS                          0xffc00500
1447+ #define TIMER_BASE_ADDRESS                        0xffc00600
1448+ #define TIMER_CHANNELS                                     3
1449+ #define TIMER_PITCH                                     0x10
1450+ #define TIMER0_BASE_ADDRESS                       0xffc00600
1451+ #define TIMER1_BASE_ADDRESS                       0xffc00610
1452+ #define TIMER2_BASE_ADDRESS                       0xffc00620
1453+ #define TIMER_ENABLE                              0xffc00640
1454+ #define TIMER_DISABLE                             0xffc00644
1455+ #define TIMER_STATUS                              0xffc00648
1456+ #define PORTFIO_BASE_ADDRESS                      0xffc00700
1457+ #define SPORT0_BASE_ADDRESS                       0xffc00800
1458+ #define SPORT1_BASE_ADDRESS                       0xffc00900
1459+ #define EBIU_BASE_ADDRESS                         0xffc00a00
1460+ #define DMA_TC_PER                                0xffc00b0c
1461+ #define DMA_TC_CNT                                0xffc00b10
1462+ #define DMA_BASE_ADDRESS                          0xffc00c00
1463+ #define DMA_CHANNELS                                       8
1464+ #define DMA_PITCH                                       0x40
1465+ #define DMA0_BASE_ADDRESS                         0xffc00c00
1466+ #define DMA1_BASE_ADDRESS                         0xffc00c40
1467+ #define DMA2_BASE_ADDRESS                         0xffc00c80
1468+ #define DMA3_BASE_ADDRESS                         0xffc00cc0
1469+ #define DMA4_BASE_ADDRESS                         0xffc00d00
1470+ #define DMA5_BASE_ADDRESS                         0xffc00d40
1471+ #define DMA6_BASE_ADDRESS                         0xffc00d80
1472+ #define DMA7_BASE_ADDRESS                         0xffc00dc0
1473+ #define DMA8_BASE_ADDRESS                         0xffc00e00
1474+ #define DMA9_BASE_ADDRESS                         0xffc00e40
1475+ #define DMA10_BASE_ADDRESS                        0xffc00e80
1476+ #define DMA11_BASE_ADDRESS                        0xffc00ec0
1477+ #define MDMA_BASE_ADDRESS                         0xffc00e00
1478+ #define MDMA_CHANNELS                                      2
1479+ #define MDMA_D_S                                        0x40
1480+ #define MDMA_PITCH                                      0x80
1481+ #define MDMA0D_BASE_ADDRESS                       0xffc00e00
1482+ #define MDMA0S_BASE_ADDRESS                       0xffc00e40
1483+ #define MDMA1D_BASE_ADDRESS                       0xffc00e80
1484+ #define MDMA1S_BASE_ADDRESS                       0xffc00ec0
1485+ #define PPI_BASE_ADDRESS                          0xffc01000
1486+
1487+
1488+ /* register fields */
1489+
1490+ #define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_MASK       0xf800
1491+ #define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_SHIFT          11
1492+ #define DMA_TC_PER_DAB_TRAFFIC_PERIOD_MASK            0x0700
1493+ #define DMA_TC_PER_DAB_TRAFFIC_PERIOD_SHIFT                8
1494+ #define DMA_TC_PER_DEB_TRAFFIC_PERIOD_MASK            0x00f0
1495+ #define DMA_TC_PER_DEB_TRAFFIC_PERIOD_SHIFT                4
1496+ #define DMA_TC_PER_DCB_TRAFFIC_PERIOD_MASK            0x000f
1497+ #define DMA_TC_PER_DCB_TRAFFIC_PERIOD_SHIFT                0
1498+
1499+ #define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_MASK        0xf800
1500+ #define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_SHIFT           11
1501+ #define DMA_TC_CNT_DAB_TRAFFIC_COUNT_MASK             0x0700
1502+ #define DMA_TC_CNT_DAB_TRAFFIC_COUNT_SHIFT                 8
1503+ #define DMA_TC_CNT_DEB_TRAFFIC_COUNT_MASK             0x00f0
1504+ #define DMA_TC_CNT_DEB_TRAFFIC_COUNT_SHIFT                 4
1505+ #define DMA_TC_CNT_DCB_TRAFFIC_COUNT_MASK             0x000f
1506+ #define DMA_TC_CNT_DCB_TRAFFIC_COUNT_SHIFT                 0
1507+
1508+ #define TIMER_ENABLE_TIMEN2                           0x0004
1509+ #define TIMER_ENABLE_TIMEN1                           0x0002
1510+ #define TIMER_ENABLE_TIMEN0                           0x0001
1511+
1512+ #define TIMER_DISABLE_TIMDIS2                         0x0004
1513+ #define TIMER_DISABLE_TIMDIS1                         0x0002
1514+ #define TIMER_DISABLE_TIMDIS0                         0x0001
1515+
1516+ #define TIMER_STATUS_TRUN2                        0x00004000
1517+ #define TIMER_STATUS_TRUN1                        0x00002000
1518+ #define TIMER_STATUS_TRUN0                        0x00001000
1519+ #define TIMER_STATUS_TOVF_ERR2                    0x00000040
1520+ #define TIMER_STATUS_TOVF_ERR1                    0x00000020
1521+ #define TIMER_STATUS_TOVF_ERR0                    0x00000010
1522+ #define TIMER_STATUS_TIMIL2                       0x00000004
1523+ #define TIMER_STATUS_TIMIL1                       0x00000002
1524+ #define TIMER_STATUS_TIMIL0                       0x00000001
1525+
1526+ /* Core Event Controller vectors */
1527+
1528+ #define CEC_EMULATION_VECTOR                               0
1529+ #define CEC_RESET_VECTOR                                   1
1530+ #define CEC_NMI_VECTOR                                     2
1531+ #define CEC_EXCEPTIONS_VECTOR                              3
1532+ #define CEC_HARDWARE_ERROR_VECTOR                          5
1533+ #define CEC_CORE_TIMER_VECTOR                              6
1534+ #define CEC_INTERRUPT_BASE_VECTOR                          7
1535+ #define CEC_INTERRUPT_COUNT                                9
1536+
1537+
1538+ /* System Interrupt Controller vectors */
1539+
1540+ #define SIC_IAR_COUNT                                      8
1541+
1542+ #endif /* _BF52X_H_ */
1543+
1544diff -crBN -X exclude rtems_orig/c/src/lib/libcpu/bfin/bf52x/interrupt/interrupt.c rtems/c/src/lib/libcpu/bfin/bf52x/interrupt/interrupt.c
1545*** rtems_orig/c/src/lib/libcpu/bfin/bf52x/interrupt/interrupt.c        1969-12-31 19:00:00.000000000 -0500
1546--- rtems/c/src/lib/libcpu/bfin/bf52x/interrupt/interrupt.c     2011-04-19 11:38:37.000000000 -0400
1547***************
1548*** 0 ****
1549--- 1,643 ----
1550+ /**
1551+  *@file interrupt.c
1552+  *
1553+  *@brief
1554+  * - This file implements interrupt dispatcher. Most of the code is taken from
1555+  *  the 533 implementation for blackfin. Since 52X supports 56 line and 2 ISR
1556+  *  registers some portion is written twice.
1557+  *
1558+  * Target:   TLL6527v1-0
1559+  * Compiler:
1560+  *
1561+  * COPYRIGHT (c) 2010 by ECE Northeastern University.
1562+  *
1563+  * The license and distribution terms for this file may be
1564+  * found in the file LICENSE in this distribution or at
1565+  * http://www.rtems.com/license
1566+  *
1567+  * @author Rohan Kangralkar, ECE, Northeastern University
1568+  *         (kangralkar.r@husky.neu.edu)
1569+  *
1570+  * LastChange:
1571+  * $Id: interrupt.c 49 2011-04-19 15:38:37Z rkangral $
1572+  *
1573+  */
1574+
1575+ #include <rtems.h>
1576+ #include <rtems/libio.h>
1577+
1578+ #include <bsp.h>
1579+ #include <libcpu/cecRegs.h>
1580+ #include <libcpu/sicRegs.h>
1581+ #include "interrupt.h"
1582+
1583+ #define SIC_IAR_COUNT_SET0              4
1584+ #define SIC_IAR_BASE_ADDRESS_0  0xFFC00150
1585+
1586+ /**
1587+  * There are two implementations for the interrupt handler.
1588+  * 1. INTERRUPT_USE_TABLE: uses tables for finding the right ISR.
1589+  * 2. Uses link list to find the user ISR.
1590+  *
1591+  *
1592+  * 1. INTERRUPT_USE_TABLE
1593+  * Space requirement:
1594+  *  - Array to hold CEC masks size: CEC_INTERRUPT_COUNT(9)*(2*int).9*2*4= 72B
1595+  *  - Array to hold isr function pointers IRQ_MAX(56)*sizeof(bfin_isr_t)= 896B
1596+  *  - Array for bit twidlling 32 bytes.
1597+  *  - Global Mask 8 bytes.
1598+  *  - Total = 1008 Bytes Aprox
1599+  *
1600+  * Time requirements
1601+  *    The worst case time is about the same for jumping to the user ISR. With a
1602+  *    variance of one conditional statement.
1603+  *
1604+  * 2. Using link list.
1605+  * Space requirement:
1606+  *  - Array to hold CEC mask CEC_INTERRUPT_COUNT(9)*(sizeof(vectors)).
1607+  *                                                                 9*3*4= 108B
1608+  *  - Array to hold isr IRQ_MAX(56)*sizeof(bfin_isr_t) The structure has
1609+  *    additional pointers                                         56*7*4=1568B
1610+  *  - Global Mask 8 bytes.
1611+  *    Total = 1684.
1612+  * Time requirements
1613+  *    In the worst case all the lines can be on one CEC line to 56 entries have
1614+  *    to be traversed to find the right user ISR.
1615+  *    But this implementation has benefit of being flexible, Providing
1616+  *    additional user assigned priority. and may consume less space
1617+  *    if all devices are not supported.
1618+  */
1619+
1620+ /**
1621+  * TODO: To place the dispatcher routine code in L1.
1622+  */
1623+
1624+ #if INTERRUPT_USE_TABLE
1625+
1626+
1627+ /******************************************************************************
1628+  * Static variables
1629+  *****************************************************************************/
1630+ /**
1631+  * @var sic_isr0_mask
1632+  * @brief copy of the mask of SIC ISR. The SIC ISR is cleared by the device
1633+  * the relevant SIC_ISRx bit is not cleared unless the interrupt
1634+  * service routine clears the mechanism that generated interrupt
1635+  */
1636+ static uint32_t sic_isr0_mask = 0;
1637+
1638+ /**
1639+  * @var sic_isr0_mask
1640+  * @brief copy of the mask of SIC ISR. The SIC ISR is cleared by the device
1641+  * the relevant SIC_ISRx bit is not cleared unless the interrupt
1642+  * service routine clears the mechanism that generated interrupt
1643+  */
1644+ static uint32_t sic_isr1_mask = 0;
1645+
1646+
1647+ /**
1648+  * @var sic_isr
1649+  * @brief An array of sic register mask for each of the 16 core interrupt lines
1650+  */
1651+ static struct {
1652+   uint32_t mask0;
1653+   uint32_t mask1;
1654+ } vectors[CEC_INTERRUPT_COUNT];
1655+
1656+ /**
1657+  * @var ivt
1658+  * @brief Contains a table of ISR and arguments. The ISR jumps directly to
1659+  * these ISR.
1660+  */
1661+ static bfin_isr_t ivt[IRQ_MAX];
1662+
1663+ /**
1664+  * http://graphics.stanford.edu/~seander/bithacks.html for more details
1665+  */
1666+ static const char clz_table[32] =
1667+ {
1668+     0, 31, 9, 30, 3, 8, 18, 29, 2, 5, 7, 14, 12, 17,
1669+     22, 28, 1, 10, 4, 19, 6, 15, 13, 23, 11, 20, 16,
1670+     24, 21, 25, 26, 27
1671+ };
1672+
1673+ /**
1674+  * finds the first bit set from the left. look at
1675+  * http://graphics.stanford.edu/~seander/bithacks.html for more details
1676+  * @param n
1677+  * @return
1678+  */
1679+ static unsigned long clz(unsigned long n)
1680+ {
1681+   unsigned long c = 0x7dcd629;       /* magic constant... */
1682+
1683+   n |= (n >> 1);
1684+   n |= (n >> 2);
1685+   n |= (n >> 4);
1686+   n |= (n >> 8);
1687+   n |= (n >> 16);
1688+   if (n == 0) return 32;
1689+   n = c + (c * n);
1690+   return 31 - clz_table[n >> 27];       /* For little endian    */
1691+ }
1692+
1693+
1694+
1695+ /**
1696+  * Centralized Interrupt dispatcher routine. This routine dispatches interrupts
1697+  * to the user ISR. The priority is according to the blackfin SIC.
1698+  * The first level of priority is handled in the hardware at the core event
1699+  * controller. The second level of interrupt is handled according to the line
1700+  * number that goes in to the SIC.
1701+  * * SIC_0 has higher priority than SIC 1.
1702+  * * Inside the SIC the priority is assigned according to the line number.
1703+  *   Lower the line number higher the priority.
1704+  *
1705+  *   In order to change the interrupt priority we may
1706+  *   1. change the SIC IAR registers or
1707+  *   2. Assign priority and extract it inside this function and call the ISR
1708+  *   according tot the priority.
1709+  *
1710+  * @param vector IVG number.
1711+  * @return
1712+  */
1713+ static rtems_isr interruptHandler(rtems_vector_number vector) {
1714+   uint32_t mask = 0;
1715+   int id = 0;
1716+   /**
1717+    * Enable for debugging
1718+    *
1719+    * static volatile uint32_t spurious_sic0    = 0;
1720+    * static volatile uint32_t spurious_source  = 0;
1721+    * static volatile uint32_t spurious_sic1    = 0;
1722+    */
1723+
1724+   /**
1725+    * Extract the vector number relative to the SIC start line
1726+    */
1727+   vector -= CEC_INTERRUPT_BASE_VECTOR;
1728+
1729+   /**
1730+    * Check for bounds
1731+    */
1732+   if (vector >= 0 && vector < CEC_INTERRUPT_COUNT) {
1733+
1734+     /**
1735+      * Extract information and execute ISR from SIC 0
1736+      */
1737+     mask = *(uint32_t volatile *) SIC_ISR &
1738+         *(uint32_t volatile *) SIC_IMASK & vectors[vector].mask0;
1739+     id      = clz(mask);
1740+     if ( SIC_ISR0_MAX > id ) {
1741+       /** Parameter check */
1742+       if( NULL != ivt[id].pFunc) {
1743+         /** Call the relevant function with argument */
1744+         ivt[id].pFunc( ivt[id].pArg );
1745+       } else {
1746+         /**
1747+          * spurious interrupt we should not be getting this
1748+          * spurious_sic0++;
1749+          * spurious_source = id;
1750+          */
1751+       }
1752+     } else {
1753+       /**
1754+        * we look at SIC 1
1755+        */
1756+     }
1757+
1758+
1759+     /**
1760+      * Extract information and execute ISR from SIC 1
1761+      */
1762+     mask    = *(uint32_t volatile *) (SIC_ISR + SIC_ISR_PITCH) &
1763+         *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH) &
1764+         vectors[vector].mask1;
1765+     id      = clz(mask)+SIC_ISR0_MAX;
1766+     if ( IRQ_MAX > id ) {
1767+       /** Parameter Check */
1768+       if( NULL != ivt[id].pFunc ) {
1769+         /** Call the relevant function with argument */
1770+         ivt[id].pFunc( ivt[id].pArg );
1771+       } else {
1772+         /**
1773+          * spurious interrupt we should not be getting this
1774+          *
1775+          * spurious_sic1++;
1776+          * spurious_source = id;
1777+          */
1778+       }
1779+     } else {
1780+       /**
1781+        * we continue
1782+        */
1783+     }
1784+
1785+   }
1786+ }
1787+
1788+
1789+
1790+ /**
1791+  * This routine registers a new ISR. It will write a new entry to the IVT table
1792+  * @param isr contains a callback function and source
1793+  * @return rtems status code
1794+  */
1795+ rtems_status_code bfin_interrupt_register(bfin_isr_t *isr) {
1796+   rtems_interrupt_level isrLevel;
1797+   int               id        = 0;
1798+   int               position  = 0;
1799+
1800+   /**
1801+    * Sanity Check
1802+    */
1803+   if ( NULL == isr ){
1804+     return RTEMS_UNSATISFIED;
1805+   }
1806+
1807+   /**
1808+    * Sanity check. The register function should at least provide callback func
1809+    */
1810+   if ( NULL == isr->pFunc ) {
1811+     return RTEMS_UNSATISFIED;
1812+   }
1813+
1814+   id = isr->source;
1815+
1816+   /**
1817+    * Parameter Check. We already have a function registered here. First
1818+    * unregister and then a new function can be allocated.
1819+    */
1820+   if ( NULL != ivt[id].pFunc ) {
1821+     return RTEMS_UNSATISFIED;
1822+   }
1823+
1824+   rtems_interrupt_disable(isrLevel);
1825+   /**
1826+    * Assign the new function pointer to the ISR Dispatcher
1827+    * */
1828+   ivt[id].pFunc    = isr->pFunc;
1829+   ivt[id].pArg     = isr->pArg;
1830+
1831+
1832+   /** find out which isr mask has to be set to enable the interrupt */
1833+   if ( SIC_ISR0_MAX > id ) {
1834+     sic_isr0_mask |= 0x1<<id;
1835+     *(uint32_t volatile *) SIC_IMASK  |= 0x1<<id;
1836+   } else {
1837+     position = id - SIC_ISR0_MAX;
1838+     sic_isr1_mask |= 0x1<<position;
1839+     *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH)  |= 0x1<<position;
1840+   }
1841+
1842+   rtems_interrupt_enable(isrLevel);
1843+
1844+   return RTEMS_SUCCESSFUL;
1845+ }
1846+
1847+
1848+ /**
1849+  * This function unregisters a registered interrupt handler.
1850+  * @param isr
1851+  */
1852+ rtems_status_code bfin_interrupt_unregister(bfin_isr_t *isr) {
1853+   rtems_interrupt_level isrLevel;
1854+   int               id        = 0;
1855+   int               position  = 0;
1856+
1857+   /**
1858+    * Sanity Check
1859+    */
1860+   if ( NULL == isr ){
1861+     return RTEMS_UNSATISFIED;
1862+   }
1863+
1864+   id = isr->source;
1865+
1866+   rtems_interrupt_disable(isrLevel);
1867+   /**
1868+    * Assign the new function pointer to the ISR Dispatcher
1869+    * */
1870+   ivt[id].pFunc    = NULL;
1871+   ivt[id].pArg     = NULL;
1872+
1873+
1874+   /** find out which isr mask has to be set to enable the interrupt */
1875+   if ( SIC_ISR0_MAX > id ) {
1876+     sic_isr0_mask &= ~(0x1<<id);
1877+     *(uint32_t volatile *) SIC_IMASK  &= ~(0x1<<id);
1878+   } else {
1879+     position = id - SIC_ISR0_MAX;
1880+     sic_isr1_mask &= ~(0x1<<position);
1881+     *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH)  &= ~(0x1<<position);
1882+   }
1883+
1884+   rtems_interrupt_enable(isrLevel);
1885+
1886+   return RTEMS_SUCCESSFUL;
1887+ }
1888+
1889+
1890+
1891+
1892+ /**
1893+  * blackfin interrupt initialization routine. It initializes the bfin ISR
1894+  * dispatcher. It will also create SIC CEC map which will be used for
1895+  * identifying the ISR.
1896+  */
1897+ void bfin_interrupt_init(void) {
1898+   int source;
1899+   int vector;
1900+   uint32_t r;
1901+   int i;
1902+   int j;
1903+
1904+   *(uint32_t volatile *) SIC_IMASK = 0;
1905+   *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH) = 0;
1906+
1907+   memset(vectors, 0, sizeof(vectors));
1908+   /* build mask0 showing what SIC sources drive each CEC vector */
1909+   source = 0;
1910+
1911+   /**
1912+    * The bf52x has 8 IAR registers but they do not have a constant pitch.
1913+    *
1914+    */
1915+   for (i = 0; i < SIC_IAR_COUNT; i++) {
1916+     if ( SIC_IAR_COUNT_SET0 > i ) {
1917+       r = *(uint32_t volatile *) (SIC_IAR_BASE_ADDRESS + i * SIC_IAR_PITCH);
1918+     } else {
1919+       r = *(uint32_t volatile *) (SIC_IAR_BASE_ADDRESS_0 +
1920+           ((i-SIC_IAR_COUNT_SET0) * SIC_IAR_PITCH));
1921+     }
1922+
1923+     for (j = 0; j < 8; j++) {
1924+       vector = r & 0x0f;
1925+       if (vector >= 0 && vector < CEC_INTERRUPT_COUNT) {
1926+         /* install our local handler */
1927+         if (vectors[vector].mask0 == 0 && vectors[vector].mask1 == 0){
1928+           set_vector(interruptHandler, vector + CEC_INTERRUPT_BASE_VECTOR, 1);
1929+         }
1930+         if ( SIC_ISR0_MAX > source ) {
1931+           vectors[vector].mask0 |= (1 << source);
1932+         } else {
1933+           vectors[vector].mask1 |= (1 << (source - SIC_ISR0_MAX));
1934+         }
1935+       }
1936+       r >>= 4;
1937+       source++;
1938+     }
1939+   }
1940+ }
1941+
1942+
1943+
1944+
1945+
1946+ #else
1947+
1948+ static struct {
1949+   uint32_t mask0;
1950+   uint32_t mask1;
1951+   bfin_isr_t *head;
1952+ } vectors[CEC_INTERRUPT_COUNT];
1953+
1954+ static uint32_t globalMask0;
1955+ static uint32_t globalMask1;
1956+
1957+ static rtems_isr interruptHandler(rtems_vector_number vector) {
1958+   bfin_isr_t *isr = NULL;
1959+   uint32_t sourceMask0 = 0;
1960+   uint32_t sourceMask1 = 0;
1961+   rtems_interrupt_level isrLevel;
1962+
1963+   rtems_interrupt_disable(isrLevel);
1964+   vector -= CEC_INTERRUPT_BASE_VECTOR;
1965+   if (vector >= 0 && vector < CEC_INTERRUPT_COUNT) {
1966+     isr = vectors[vector].head;
1967+     sourceMask0 = *(uint32_t volatile *) SIC_ISR &
1968+         *(uint32_t volatile *) SIC_IMASK;
1969+     sourceMask1 = *(uint32_t volatile *) (SIC_ISR + SIC_ISR_PITCH) &
1970+         *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH);
1971+     while (isr) {
1972+       if ((sourceMask0 & isr->mask0) || (sourceMask1 & isr->mask1)) {
1973+         isr->isr(isr->_arg);
1974+         sourceMask0 = *(uint32_t volatile *) SIC_ISR &
1975+             *(uint32_t volatile *) SIC_IMASK;
1976+         sourceMask1 = *(uint32_t volatile *) (SIC_ISR + SIC_ISR_PITCH) &
1977+             *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH);
1978+       }
1979+       isr = isr->next;
1980+     }
1981+   }
1982+   rtems_interrupt_enable(isrLevel);
1983+ }
1984+
1985+ /**
1986+  * Initializes the interrupt module
1987+  */
1988+ void bfin_interrupt_init(void) {
1989+   int source;
1990+   int vector;
1991+   uint32_t r;
1992+   int i;
1993+   int j;
1994+
1995+   globalMask0 = ~(uint32_t) 0;
1996+   globalMask1 = ~(uint32_t) 0;
1997+   *(uint32_t volatile *) SIC_IMASK = 0;
1998+   *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH) = 0;
1999+
2000+   memset(vectors, 0, sizeof(vectors));
2001+   /* build mask0 showing what SIC sources drive each CEC vector */
2002+   source = 0;
2003+
2004+   /**
2005+    * The bf52x has 8 IAR registers but they do not have a constant pitch.
2006+    *
2007+    */
2008+   for (i = 0; i < SIC_IAR_COUNT; i++) {
2009+     if ( SIC_IAR_COUNT_SET0 > i ) {
2010+       r = *(uint32_t volatile *) (SIC_IAR_BASE_ADDRESS + i * SIC_IAR_PITCH);
2011+     } else {
2012+       r = *(uint32_t volatile *) (SIC_IAR_BASE_ADDRESS_0 +
2013+           ((i-SIC_IAR_COUNT_SET0) * SIC_IAR_PITCH));
2014+     }
2015+     for (j = 0; j < 8; j++) {
2016+       vector = r & 0x0f;
2017+       if (vector >= 0 && vector < CEC_INTERRUPT_COUNT) {
2018+         /* install our local handler */
2019+         if (vectors[vector].mask0 == 0 && vectors[vector].mask1 == 0){
2020+           set_vector(interruptHandler, vector + CEC_INTERRUPT_BASE_VECTOR, 1);
2021+         }
2022+         if ( SIC_ISR0_MAX > source ) {
2023+           vectors[vector].mask0 |= (1 << source);
2024+         } else {
2025+           vectors[vector].mask1 |= (1 << (source - SIC_ISR0_MAX));
2026+         }
2027+       }
2028+       r >>= 4;
2029+       source++;
2030+     }
2031+   }
2032+ }
2033+
2034+ /* modify SIC_IMASK based on ISR list for a particular CEC vector */
2035+ static void setMask(uint32_t vector) {
2036+   bfin_isr_t *isr = NULL;
2037+   uint32_t mask = 0;
2038+   uint32_t r    = 0;
2039+
2040+   mask = 0;
2041+   isr = vectors[vector].head;
2042+   while (isr) {
2043+     mask |= isr->mask0;
2044+     isr = isr->next;
2045+   }
2046+   r = *(uint32_t volatile *) SIC_IMASK;
2047+   r &= ~vectors[vector].mask0;
2048+   r |= mask;
2049+   r &= globalMask0;
2050+   *(uint32_t volatile *) SIC_IMASK = r;
2051+
2052+
2053+   mask = 0;
2054+   isr = vectors[vector].head;
2055+   while (isr) {
2056+     mask |= isr->mask1;
2057+     isr = isr->next;
2058+   }
2059+   r = *(uint32_t volatile *) (SIC_IMASK+ SIC_IMASK_PITCH);
2060+   r &= ~vectors[vector].mask1;
2061+   r |= mask;
2062+   r &= globalMask1;
2063+   *(uint32_t volatile *) (SIC_IMASK+ SIC_IMASK_PITCH) = r;
2064+ }
2065+
2066+ /* add an ISR to the list for whichever vector it belongs to */
2067+ rtems_status_code bfin_interrupt_register(bfin_isr_t *isr) {
2068+   bfin_isr_t *walk;
2069+   rtems_interrupt_level isrLevel;
2070+
2071+   /* find the appropriate vector */
2072+   for (isr->vector = 0; isr->vector < CEC_INTERRUPT_COUNT; isr->vector++)
2073+     if ( (vectors[isr->vector].mask0 & (1 << isr->source) ) || \
2074+         (vectors[isr->vector].mask1 & (1 << (isr->source - SIC_ISR0_MAX)) ))
2075+       break;
2076+   if (isr->vector < CEC_INTERRUPT_COUNT) {
2077+     isr->next = NULL;
2078+     isr->mask0 = 0;
2079+     isr->mask1 = 0;
2080+     rtems_interrupt_disable(isrLevel);
2081+     /* find the current end of the list */
2082+     walk = vectors[isr->vector].head;
2083+     while (walk && walk->next)
2084+       walk = walk->next;
2085+     /* append new isr to list */
2086+     if (walk)
2087+       walk->next = isr;
2088+     else
2089+       vectors[isr->vector].head = isr;
2090+     rtems_interrupt_enable(isrLevel);
2091+   } else
2092+     /* we failed, but make vector a legal value so other calls into
2093+              this module with this isr descriptor won't do anything bad */
2094+     isr->vector = 0;
2095+   return RTEMS_SUCCESSFUL;
2096+ }
2097+
2098+ rtems_status_code bfin_interrupt_unregister(bfin_isr_t *isr) {
2099+   bfin_isr_t *walk, *prev;
2100+   rtems_interrupt_level isrLevel;
2101+
2102+   rtems_interrupt_disable(isrLevel);
2103+   walk = vectors[isr->vector].head;
2104+   prev = NULL;
2105+   /* find this isr in our list */
2106+   while (walk && walk != isr) {
2107+     prev = walk;
2108+     walk = walk->next;
2109+   }
2110+   if (walk) {
2111+     /* if found, remove it */
2112+     if (prev)
2113+       prev->next = walk->next;
2114+     else
2115+       vectors[isr->vector].head = walk->next;
2116+     /* fix up SIC_IMASK if necessary */
2117+     setMask(isr->vector);
2118+   }
2119+   rtems_interrupt_enable(isrLevel);
2120+   return RTEMS_SUCCESSFUL;
2121+ }
2122+
2123+ void bfin_interrupt_enable(bfin_isr_t *isr, bool enable) {
2124+   rtems_interrupt_level isrLevel;
2125+
2126+   rtems_interrupt_disable(isrLevel);
2127+   if ( SIC_ISR0_MAX > isr->source ) {
2128+     isr->mask0 = enable ? (1 << isr->source) : 0;
2129+     *(uint32_t volatile *) SIC_IMASK |= isr->mask0;
2130+   }  else {
2131+     isr->mask1 = enable ? (1 << (isr->source - SIC_ISR0_MAX)) : 0;
2132+     *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH) |= isr->mask1;
2133+   }
2134+
2135+   //setMask(isr->vector);
2136+   rtems_interrupt_enable(isrLevel);
2137+ }
2138+
2139+ void bfin_interrupt_enable_all(int source, bool enable) {
2140+   rtems_interrupt_level isrLevel;
2141+   int vector;
2142+   bfin_isr_t *walk;
2143+
2144+   for (vector = 0; vector < CEC_INTERRUPT_COUNT; vector++)
2145+     if ( (vectors[vector].mask0 & (1 << source) ) || \
2146+         (vectors[vector].mask1 & (1 << (source - SIC_ISR0_MAX)) ))
2147+       break;
2148+   if (vector < CEC_INTERRUPT_COUNT) {
2149+     rtems_interrupt_disable(isrLevel);
2150+     walk = vectors[vector].head;
2151+     while (walk) {
2152+       walk->mask0 = enable ? (1 << source) : 0;
2153+       walk = walk->next;
2154+     }
2155+
2156+     walk = vectors[vector].head;
2157+     while (walk) {
2158+       walk->mask1 = enable ? (1 << (source - SIC_ISR0_MAX)) : 0;
2159+       walk = walk->next;
2160+     }
2161+     setMask(vector);
2162+     rtems_interrupt_enable(isrLevel);
2163+   }
2164+ }
2165+
2166+ void bfin_interrupt_enable_global(int source, bool enable) {
2167+   int vector;
2168+   rtems_interrupt_level isrLevel;
2169+
2170+   for (vector = 0; vector < CEC_INTERRUPT_COUNT; vector++)
2171+     if ( (vectors[vector].mask0 & (1 << source) ) || \
2172+         (vectors[vector].mask1 & (1 << (source - SIC_ISR0_MAX)) ))
2173+       break;
2174+   if (vector < CEC_INTERRUPT_COUNT) {
2175+     rtems_interrupt_disable(isrLevel);
2176+     if ( SIC_ISR0_MAX > source ) {
2177+       if (enable)
2178+         globalMask0 |= 1 << source;
2179+       else
2180+         globalMask0 &= ~(1 << source);
2181+     }else {
2182+       if (enable)
2183+         globalMask1 |= 1 << (source - SIC_ISR0_MAX);
2184+       else
2185+         globalMask1 &= ~(1 << (source - SIC_ISR0_MAX));
2186+     }
2187+     setMask(vector);
2188+     rtems_interrupt_enable(isrLevel);
2189+   }
2190+ }
2191+
2192+ #endif
2193diff -crBN -X exclude rtems_orig/c/src/lib/libcpu/bfin/bf52x/interrupt/interrupt.h rtems/c/src/lib/libcpu/bfin/bf52x/interrupt/interrupt.h
2194*** rtems_orig/c/src/lib/libcpu/bfin/bf52x/interrupt/interrupt.h        1969-12-31 19:00:00.000000000 -0500
2195--- rtems/c/src/lib/libcpu/bfin/bf52x/interrupt/interrupt.h     2011-04-19 11:00:07.000000000 -0400
2196***************
2197*** 0 ****
2198--- 1,146 ----
2199+ /**
2200+  *@file interrupt.h
2201+  *
2202+  *@brief
2203+  *  - This file implements interrupt dispatcher. The init code is taken from
2204+  *  the 533 implementation for blackfin. Since 52X supports 56 line and 2 ISR
2205+  *  registers some portion is written twice.
2206+  *
2207+  * Target:   TLL6527v1-0
2208+  * Compiler:
2209+  *
2210+  * COPYRIGHT (c) 2010 by ECE Northeastern University.
2211+  *
2212+  * The license and distribution terms for this file may be
2213+  * found in the file LICENSE in this distribution or at
2214+  * http://www.rtems.com/license
2215+  *
2216+  * @author Rohan Kangralkar, ECE, Northeastern University
2217+  *         (kangralkar.r@husky.neu.edu)
2218+  *
2219+  * LastChange:
2220+  * $Id: interrupt.h 48 2011-04-19 15:00:07Z rkangral $
2221+  *
2222+  */
2223+
2224+ #ifndef _BFIN_INTERRUPT_H_
2225+ #define _BFIN_INTERRUPT_H_
2226+
2227+
2228+ #ifdef __cplusplus
2229+ extern "C" {
2230+ #endif
2231+
2232+ /** The type of interrupts handled by the SIC
2233+  */
2234+ typedef enum {
2235+     IRQ_PLL_WAKEUP_INTERRUPT,                 /* 0 */
2236+     IRQ_DMA_ERROR_0,                          /* 1 */
2237+     IRQ_DMAR0_BLOCK_INTERRUPT,                /* 2 */
2238+     IRQ_DMAR1_BLOCK_INTERRUPT,                /* 3 */
2239+     IRQ_DMAR0_OVERFLOW_ERROR,                 /* 4 */
2240+     IRQ_DMAR1_OVERFLOW_ERROR,                 /* 5 */
2241+     IRQ_PPI_STATUS,                           /* 6 */
2242+     IRQ_MAC_STATUS,                           /* 7 */
2243+     IRQ_SPORT0_STATUS,                        /* 8 */
2244+     IRQ_SPORT1_STATUS,                        /* 9 */
2245+     IRQ_RESERVED_10,                          /* 10 */
2246+     IRQ_RESERVED_11,                          /* 11 */
2247+     IRQ_UART0_STATUS,                         /* 12 */
2248+     IRQ_UART1_STATUS,                         /* 13 */
2249+     IRQ_REAL_TIME_CLOCK,                      /* 14 */
2250+     IRQ_DMA0_PPI_NFC,                         /* 15 */
2251+     IRQ_DMA3_SPORT0_RX,                       /* 16 */
2252+     IRQ_DMA4_SPORT0_TX,                       /* 17 */
2253+     IRQ_DMA5_SPORT1_RX,                       /* 18 */
2254+     IRQ_DMA6_SPORT1_TX,                       /* 19 */
2255+     IRQ_TWI_INTERRUPT,                        /* 20 */
2256+     IRQ_DMA7_SPI,                             /* 21 */
2257+     IRQ_DMA8_UART0_RX,                        /* 22 */
2258+     IRQ_DMA9_UART0_TX,                        /* 23 */
2259+     IRQ_DMA10_UART1_RX,                       /* 24 */
2260+     IRQ_DMA11_UART1_TX,                       /* 25 */
2261+     IRQ_OTP,                                  /* 26 */
2262+     IRQ_GP_COUNTER,                           /* 27 */
2263+     IRQ_DMA1_MAC_RX_HOSTDP,                   /* 28 */
2264+     IRQ_PORT_H_INTERRUPT_A,                   /* 29 */
2265+     IRQ_DMA2_MAC_TX_NFC,                      /* 30 */
2266+     IRQ_PORT_H_INTERRUPT_B,                   /* 31 */
2267+     SIC_ISR0_MAX,                             /* 32 ***/
2268+     IRQ_TIMER0 = SIC_ISR0_MAX,                /* 32 */
2269+     IRQ_TIMER1,                               /* 33 */
2270+     IRQ_TIMER2,                               /* 34 */
2271+     IRQ_TIMER3,                               /* 35 */
2272+     IRQ_TIMER4,                               /* 36 */
2273+     IRQ_TIMER5,                               /* 37 */
2274+     IRQ_TIMER6,                               /* 38 */
2275+     IRQ_TIMER7,                               /* 39 */
2276+     IRQ_PORT_G_INTERRUPT_A,                   /* 40 */
2277+     IRQ_PORT_G_INTERRUPT_B,                   /* 41 */
2278+     IRQ_MDMA0_STREAM_0_INTERRUPT,             /* 42 */
2279+     IRQ_MDMA1_STREAM_0_INTERRUPT,             /* 43 */
2280+     IRQ_SOFTWARE_WATCHDOG_INTERRUPT,          /* 44 */
2281+     IRQ_PORT_F_INTERRUPT_A,                   /* 45 */
2282+     IRQ_PORT_F_INTERRUPT_B,                   /* 46 */
2283+     IRQ_SPI_STATUS,                           /* 47 */
2284+     IRQ_NFC_STATUS,                           /* 48 */
2285+     IRQ_HOSTDP_STATUS,                        /* 49 */
2286+     IRQ_HOREAD_DONE_INTERRUPT,                /* 50 */
2287+     IRQ_RESERVED_19,                          /* 51 */
2288+     IRQ_USB_INT0_INTERRUPT,                   /* 52 */
2289+     IRQ_USB_INT1_INTERRUPT,                   /* 53 */
2290+     IRQ_USB_INT2_INTERRUPT,                   /* 54 */
2291+     IRQ_USB_DMAINT,                           /* 55 */
2292+     IRQ_MAX,                                  /* 56 */
2293+ } e_isr_t;
2294+
2295+
2296+
2297+
2298+ /* source is the source to the SIC (the bit number in SIC_ISR).  isr is
2299+    the function that will be called when the interrupt is active. */
2300+ typedef struct bfin_isr_s {
2301+ #if INTERRUPT_USE_TABLE
2302+   e_isr_t source;
2303+   void (*pFunc)(void *arg);
2304+   void *pArg;
2305+   int priority; /** not used */
2306+ #else
2307+   int source;
2308+   void (*isr)(void *arg);
2309+   void *_arg;
2310+   /* the following are for internal use only */
2311+   uint32_t mask0;
2312+   uint32_t mask1;
2313+   uint32_t vector;
2314+   struct bfin_isr_s *next;
2315+ #endif
2316+ } bfin_isr_t;
2317+
2318+ /**
2319+  * This routine registers a new ISR. It will write a new entry to the IVT table
2320+  * @param isr contains a callback function and source
2321+  * @return rtems status code
2322+  */
2323+ rtems_status_code bfin_interrupt_register(bfin_isr_t *isr);
2324+
2325+ /**
2326+  * This function unregisters a registered interrupt handler.
2327+  * @param isr
2328+  */
2329+ rtems_status_code bfin_interrupt_unregister(bfin_isr_t *isr);
2330+
2331+ /**
2332+  * blackfin interrupt initialization routine. It initializes the bfin ISR
2333+  * dispatcher. It will also create SIC CEC map which will be used for
2334+  * identifying the ISR.
2335+  */
2336+ void bfin_interrupt_init(void);
2337+
2338+
2339+ #ifdef __cplusplus
2340+ }
2341+ #endif
2342+
2343+ #endif /* _BFIN_INTERRUPT_H_ */
2344+
2345diff -crBN -X exclude rtems_orig/c/src/lib/libcpu/bfin/configure.ac rtems/c/src/lib/libcpu/bfin/configure.ac
2346*** rtems_orig/c/src/lib/libcpu/bfin/configure.ac       2011-04-19 11:04:26.000000000 -0400
2347--- rtems/c/src/lib/libcpu/bfin/configure.ac    2011-02-25 15:46:42.000000000 -0500
2348***************
2349*** 1,6 ****
2350  ## Process this file with autoconf to produce a configure script.
2351  ##
2352! ## $Id: configure.ac,v 1.2.2.1 2011/02/02 15:17:24 ralf Exp $
2353  ##
2354 
2355  AC_PREREQ([2.68])
2356--- 1,6 ----
2357  ## Process this file with autoconf to produce a configure script.
2358  ##
2359! ## $Id: configure.ac 27 2011-02-25 20:46:42Z rkangral $
2360  ##
2361 
2362  AC_PREREQ([2.68])
2363***************
2364*** 24,29 ****
2365--- 24,33 ----
2366  RTEMS_CHECK_NETWORKING
2367  AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
2368 
2369+ # AM_CONDITIONAL(shared, test "$RTEMS_CPU_MODEL" = "bf52x")
2370+ AM_CONDITIONAL(bf52x, test "$RTEMS_CPU_MODEL" = "bf52x")
2371+
2372+
2373  RTEMS_AMPOLISH3
2374 
2375  # Explicitly list all Makefiles here
2376diff -crBN -X exclude rtems_orig/c/src/lib/libcpu/bfin/include/dmaRegs.h rtems/c/src/lib/libcpu/bfin/include/dmaRegs.h
2377*** rtems_orig/c/src/lib/libcpu/bfin/include/dmaRegs.h  2011-04-19 11:04:26.000000000 -0400
2378--- rtems/c/src/lib/libcpu/bfin/include/dmaRegs.h       2011-02-25 15:46:42.000000000 -0500
2379***************
2380*** 7,13 ****
2381   *  found in the file LICENSE in this distribution or at
2382   *  http://www.rtems.com/license/LICENSE.
2383   *
2384!  *  $Id: dmaRegs.h,v 1.1 2008/08/15 20:18:41 joel Exp $
2385   */
2386 
2387  #ifndef _dmaRegs_h_
2388--- 7,13 ----
2389   *  found in the file LICENSE in this distribution or at
2390   *  http://www.rtems.com/license/LICENSE.
2391   *
2392!  *  $Id: dmaRegs.h 27 2011-02-25 20:46:42Z rkangral $
2393   */
2394 
2395  #ifndef _dmaRegs_h_
2396diff -crBN -X exclude rtems_orig/c/src/lib/libcpu/bfin/include/sicRegs.h rtems/c/src/lib/libcpu/bfin/include/sicRegs.h
2397*** rtems_orig/c/src/lib/libcpu/bfin/include/sicRegs.h  2011-04-19 11:04:26.000000000 -0400
2398--- rtems/c/src/lib/libcpu/bfin/include/sicRegs.h       2011-02-25 15:46:42.000000000 -0500
2399***************
2400*** 7,13 ****
2401   *  found in the file LICENSE in this distribution or at
2402   *  http://www.rtems.com/license/LICENSE.
2403   *
2404!  *  $Id: sicRegs.h,v 1.3 2009/11/30 05:03:49 ralf Exp $
2405   */
2406 
2407  #ifndef _sicRegs_h_
2408--- 7,13 ----
2409   *  found in the file LICENSE in this distribution or at
2410   *  http://www.rtems.com/license/LICENSE.
2411   *
2412!  *  $Id: sicRegs.h 27 2011-02-25 20:46:42Z rkangral $
2413   */
2414 
2415  #ifndef _sicRegs_h_
2416***************
2417*** 16,23 ****
2418--- 16,29 ----
2419  /* register addresses */
2420 
2421  #define SIC_IMASK                (SIC_BASE_ADDRESS + 0x000c)
2422+ #define SIC_IMASK_PITCH          (0x40)
2423+
2424+ #define SIC_ISR                  (SIC_BASE_ADDRESS + 0x0020)
2425+ #define SIC_ISR_PITCH            (0x40)
2426+
2427  #define SIC_IAR_BASE_ADDRESS     (SIC_BASE_ADDRESS + 0x0010)
2428  #define SIC_IAR_PITCH                                   0x04
2429+
2430  #define SIC_IAR0                 (SIC_BASE_ADDRESS + 0x0010)
2431  #if SIC_IAR_COUNT > 1
2432  #define SIC_IAR1                 (SIC_BASE_ADDRESS + 0x0014)
2433***************
2434*** 28,34 ****
2435  #if SIC_IAR_COUNT > 3
2436  #define SIC_IAR3                 (SIC_BASE_ADDRESS + 0x001c)
2437  #endif
2438! #define SIC_ISR                  (SIC_BASE_ADDRESS + 0x0020)
2439  #define SIC_IWR                  (SIC_BASE_ADDRESS + 0x0024)
2440 
2441 
2442--- 34,40 ----
2443  #if SIC_IAR_COUNT > 3
2444  #define SIC_IAR3                 (SIC_BASE_ADDRESS + 0x001c)
2445  #endif
2446!
2447  #define SIC_IWR                  (SIC_BASE_ADDRESS + 0x0024)
2448 
2449 
2450diff -crBN -X exclude rtems_orig/c/src/lib/libcpu/bfin/include/uartRegs.h rtems/c/src/lib/libcpu/bfin/include/uartRegs.h
2451*** rtems_orig/c/src/lib/libcpu/bfin/include/uartRegs.h 2011-04-19 11:04:26.000000000 -0400
2452--- rtems/c/src/lib/libcpu/bfin/include/uartRegs.h      2011-02-25 15:46:42.000000000 -0500
2453***************
2454*** 7,13 ****
2455   *  found in the file LICENSE in this distribution or at
2456   *  http://www.rtems.com/license/LICENSE.
2457   *
2458!  *  $Id: uartRegs.h,v 1.1 2008/08/15 20:18:41 joel Exp $
2459   */
2460 
2461  #ifndef _uartRegs_h_
2462--- 7,13 ----
2463   *  found in the file LICENSE in this distribution or at
2464   *  http://www.rtems.com/license/LICENSE.
2465   *
2466!  *  $Id: uartRegs.h 27 2011-02-25 20:46:42Z rkangral $
2467   */
2468 
2469  #ifndef _uartRegs_h_
2470diff -crBN -X exclude rtems_orig/c/src/lib/libcpu/bfin/Makefile.am rtems/c/src/lib/libcpu/bfin/Makefile.am
2471*** rtems_orig/c/src/lib/libcpu/bfin/Makefile.am        2011-04-19 11:04:26.000000000 -0400
2472--- rtems/c/src/lib/libcpu/bfin/Makefile.am     2011-02-25 15:46:42.000000000 -0500
2473***************
2474*** 1,5 ****
2475  ##
2476! ## $Id: Makefile.am,v 1.1 2008/08/15 20:18:40 joel Exp $
2477  ##
2478 
2479  ACLOCAL_AMFLAGS = -I ../../../aclocal
2480--- 1,5 ----
2481  ##
2482! ## $Id: Makefile.am 27 2011-02-25 20:46:42Z rkangral $
2483  ##
2484 
2485  ACLOCAL_AMFLAGS = -I ../../../aclocal
2486***************
2487*** 10,18 ****
2488--- 10,40 ----
2489 
2490  noinst_PROGRAMS =
2491 
2492+ include_bspdir = $(includedir)/bsp
2493  include_libcpudir = $(includedir)/libcpu
2494+
2495+ include_bsp_HEADERS =
2496  include_libcpu_HEADERS =
2497 
2498+
2499+ ############
2500+ # Start of bf52x files
2501+ if bf52x
2502+
2503+ include_HEADERS = bf52x/include/bf52x.h
2504+
2505+ ## INTERRUPT
2506+ include_bsp_HEADERS += bf52x/interrupt/interrupt.h
2507+ noinst_PROGRAMS += bf52x/interrupt.rel
2508+ bf52x_interrupt_rel_SOURCES = bf52x/interrupt/interrupt.c \
2509+                               bf52x/interrupt/interrupt.h
2510+ bf52x_interrupt_rel_CPPFLAGS = $(AM_CPPFLAGS)
2511+ bf52x_interrupt_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
2512+
2513+ endif
2514+ # endof bf52x
2515+ ############
2516+
2517  include_libcpu_HEADERS += include/bf533.h
2518  include_libcpu_HEADERS += include/bf537.h
2519  include_libcpu_HEADERS += include/cecRegs.h
2520***************
2521*** 47,58 ****
2522--- 69,85 ----
2523  mmu_rel_CPPFLAGS = $(AM_CPPFLAGS)
2524  mmu_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
2525 
2526+ if bf52x
2527+
2528+ else
2529  include_libcpu_HEADERS += interrupt/interrupt.h
2530  noinst_PROGRAMS += interrupt.rel
2531  interrupt_rel_SOURCES = interrupt/interrupt.c
2532  interrupt_rel_CPPFLAGS = $(AM_CPPFLAGS)
2533  interrupt_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
2534 
2535+ endif
2536+
2537  noinst_PROGRAMS += clock.rel
2538  clock_rel_SOURCES = clock/clock.c
2539  clock_rel_CPPFLAGS = $(AM_CPPFLAGS)
2540diff -crBN -X exclude rtems_orig/c/src/lib/libcpu/bfin/preinstall.am rtems/c/src/lib/libcpu/bfin/preinstall.am
2541*** rtems_orig/c/src/lib/libcpu/bfin/preinstall.am      2011-04-19 11:04:26.000000000 -0400
2542--- rtems/c/src/lib/libcpu/bfin/preinstall.am   2011-02-17 10:19:06.000000000 -0500
2543***************
2544*** 13,23 ****
2545--- 13,42 ----
2546  PREINSTALL_FILES =
2547  CLEANFILES = $(PREINSTALL_FILES)
2548 
2549+ $(PROJECT_INCLUDE)/$(dirstamp):
2550+       @$(MKDIR_P) $(PROJECT_INCLUDE)
2551+       @: > $(PROJECT_INCLUDE)/$(dirstamp)
2552+ PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
2553+
2554+ $(PROJECT_INCLUDE)/bsp/$(dirstamp):
2555+       @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp
2556+       @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp)
2557+ PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp)
2558+
2559  $(PROJECT_INCLUDE)/libcpu/$(dirstamp):
2560        @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu
2561        @: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
2562  PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
2563 
2564+ if bf52x
2565+ $(PROJECT_INCLUDE)/bf52x.h: bf52x/include/bf52x.h $(PROJECT_INCLUDE)/$(dirstamp)
2566+       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bf52x.h
2567+ PREINSTALL_FILES += $(PROJECT_INCLUDE)/bf52x.h
2568+
2569+ $(PROJECT_INCLUDE)/bsp/interrupt.h: bf52x/interrupt/interrupt.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
2570+       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/interrupt.h
2571+ PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/interrupt.h
2572+ endif
2573  $(PROJECT_INCLUDE)/libcpu/bf533.h: include/bf533.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
2574        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/bf533.h
2575  PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/bf533.h
2576***************
2577*** 102,111 ****
2578        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/mmu.h
2579  PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/mmu.h
2580 
2581  $(PROJECT_INCLUDE)/libcpu/interrupt.h: interrupt/interrupt.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
2582        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/interrupt.h
2583  PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/interrupt.h
2584!
2585  $(PROJECT_INCLUDE)/libcpu/uart.h: serial/uart.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
2586        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/uart.h
2587  PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/uart.h
2588--- 121,132 ----
2589        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/mmu.h
2590  PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/mmu.h
2591 
2592+ if bf52x
2593+ else
2594  $(PROJECT_INCLUDE)/libcpu/interrupt.h: interrupt/interrupt.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
2595        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/interrupt.h
2596  PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/interrupt.h
2597! endif
2598  $(PROJECT_INCLUDE)/libcpu/uart.h: serial/uart.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
2599        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/uart.h
2600  PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/uart.h
2601diff -crBN -X exclude rtems_orig/c/src/lib/libcpu/bfin/serial/uart.c rtems/c/src/lib/libcpu/bfin/serial/uart.c
2602*** rtems_orig/c/src/lib/libcpu/bfin/serial/uart.c      2011-04-19 11:04:26.000000000 -0400
2603--- rtems/c/src/lib/libcpu/bfin/serial/uart.c   2011-04-19 11:38:37.000000000 -0400
2604***************
2605*** 7,13 ****
2606   *  found in the file LICENSE in this distribution or at
2607   *  http://www.rtems.com/license/LICENSE.
2608   *
2609!  *  $Id: uart.c,v 1.3 2009/12/11 04:15:58 ralf Exp $
2610   */
2611 
2612 
2613--- 7,16 ----
2614   *  found in the file LICENSE in this distribution or at
2615   *  http://www.rtems.com/license/LICENSE.
2616   *
2617!  *  Modified:
2618!  *  $ $Author: rkangral $ Added interrupt support and DMA support
2619!  *
2620!  *  $Id: uart.c 49 2011-04-19 15:38:37Z rkangral $
2621   */
2622 
2623 
2624***************
2625*** 18,26 ****
2626  #include <stdlib.h>
2627 
2628  #include <libcpu/uartRegs.h>
2629  #include "uart.h"
2630 
2631-
2632  /* flags */
2633  #define BFIN_UART_XMIT_BUSY 0x01
2634 
2635--- 21,29 ----
2636  #include <stdlib.h>
2637 
2638  #include <libcpu/uartRegs.h>
2639+ #include <libcpu/dmaRegs.h>
2640  #include "uart.h"
2641 
2642  /* flags */
2643  #define BFIN_UART_XMIT_BUSY 0x01
2644 
2645***************
2646*** 28,72 ****
2647  static bfin_uart_config_t *uartsConfig;
2648 
2649 
2650- static void initializeHardware(int minor) {
2651-   uint16_t divisor;
2652-   char *base;
2653-   uint16_t r;
2654-
2655-   base = uartsConfig->channels[minor].base_address;
2656-
2657-   *(uint16_t volatile *) (base + UART_IER_OFFSET) = 0;
2658-
2659-   if (uartsConfig->channels[minor].force_baud)
2660-     divisor = (uint16_t) (uartsConfig->freq /
2661-                           (uartsConfig->channels[minor].force_baud * 16));
2662-   else
2663-     divisor = (uint16_t) (uartsConfig->freq / (9600 * 16));
2664-   *(uint16_t volatile *) (base + UART_LCR_OFFSET) = UART_LCR_DLAB;
2665-   *(uint16_t volatile *) (base + UART_DLL_OFFSET) = (divisor & 0xff);
2666-   *(uint16_t volatile *) (base + UART_DLH_OFFSET) = ((divisor >> 8) & 0xff);
2667-
2668-   *(uint16_t volatile *) (base + UART_LCR_OFFSET) = UART_LCR_WLS_8;
2669-
2670-   *(uint16_t volatile *) (base + UART_GCTL_OFFSET) = UART_GCTL_UCEN;
2671-
2672-   r = *(uint16_t volatile *) (base + UART_LSR_OFFSET);
2673-   r = *(uint16_t volatile *) (base + UART_RBR_OFFSET);
2674-   r = *(uint16_t volatile *) (base + UART_IIR_OFFSET);
2675-
2676-   return;
2677- }
2678-
2679  static int pollRead(int minor) {
2680    int c;
2681!   char *base;
2682 
2683!   base = uartsConfig->channels[minor].base_address;
2684 
2685    /* check to see if driver is using interrupts so this call will be
2686       harmless (though non-functional) in case some debug code tries to
2687       use it */
2688!   if (!uartsConfig->channels[minor].use_interrupts &&
2689        *((uint16_t volatile *) (base + UART_LSR_OFFSET)) & UART_LSR_DR)
2690      c = *((uint16_t volatile *) (base + UART_RBR_OFFSET));
2691    else
2692--- 31,46 ----
2693  static bfin_uart_config_t *uartsConfig;
2694 
2695 
2696  static int pollRead(int minor) {
2697    int c;
2698!   uint32_t base;
2699 
2700!   base = uartsConfig->channels[minor].uart_baseAddress;
2701 
2702    /* check to see if driver is using interrupts so this call will be
2703       harmless (though non-functional) in case some debug code tries to
2704       use it */
2705!   if (!uartsConfig->channels[minor].uart_useInterrupts &&
2706        *((uint16_t volatile *) (base + UART_LSR_OFFSET)) & UART_LSR_DR)
2707      c = *((uint16_t volatile *) (base + UART_RBR_OFFSET));
2708    else
2709***************
2710*** 75,81 ****
2711    return c;
2712  }
2713 
2714! char bfin_uart_poll_read(int minor) {
2715    int c;
2716 
2717    do {
2718--- 49,55 ----
2719    return c;
2720  }
2721 
2722! char bfin_uart_poll_read(rtems_device_minor_number minor) {
2723    int c;
2724 
2725    do {
2726***************
2727*** 86,94 ****
2728  }
2729 
2730  void bfin_uart_poll_write(int minor, char c) {
2731!   char *base;
2732 
2733!   base = uartsConfig->channels[minor].base_address;
2734 
2735    while (!(*((uint16_t volatile *) (base + UART_LSR_OFFSET)) & UART_LSR_THRE))
2736      ;
2737--- 60,68 ----
2738  }
2739 
2740  void bfin_uart_poll_write(int minor, char c) {
2741!   uint32_t base;
2742 
2743!   base = uartsConfig->channels[minor].uart_baseAddress;
2744 
2745    while (!(*((uint16_t volatile *) (base + UART_LSR_OFFSET)) & UART_LSR_THRE))
2746      ;
2747***************
2748*** 157,200 ****
2749    return count;
2750  }
2751 
2752- static void enableInterrupts(int minor) {
2753-   char *base;
2754 
2755!   base = uartsConfig->channels[minor].base_address;
2756 
2757!   *(uint16_t volatile *) (base + UART_IER_OFFSET) = UART_IER_ETBEI |
2758!                                                     UART_IER_ERBFI;
2759! }
2760 
2761- static void disableAllInterrupts(void) {
2762-   int i;
2763-   char *base;
2764 
2765!   for (i = 0; i < uartsConfig->num_channels; i++) {
2766!     base = uartsConfig->channels[i].base_address;
2767!     *(uint16_t volatile *) (base + UART_IER_OFFSET) = 0;
2768    }
2769- }
2770 
2771! static ssize_t interruptWrite(int minor, const char *buf, size_t len) {
2772!   char *base;
2773 
2774!   base = uartsConfig->channels[minor].base_address;
2775 
2776!   uartsConfig->channels[minor].flags |= BFIN_UART_XMIT_BUSY;
2777!   *(uint16_t volatile *) (base + UART_THR_OFFSET) = *buf;
2778 
2779!   /* one byte written */
2780!   return 1;
2781  }
2782 
2783  static int setAttributes(int minor, const struct termios *termios) {
2784!   char *base;
2785    int baud;
2786    uint16_t divisor;
2787    uint16_t lcr;
2788 
2789!   base = uartsConfig->channels[minor].base_address;
2790    switch (termios->c_cflag & CBAUD) {
2791    case B0:
2792      baud = 0;
2793--- 129,214 ----
2794    return count;
2795  }
2796 
2797 
2798! /**
2799!  * Routine to initialize the hardware. It initialize the DMA,
2800!  * interrupt if required.
2801!  * @param channel channel information
2802!  */
2803! static void initializeHardware(bfin_uart_channel_t *channel) {
2804!   uint16_t divisor        = 0;
2805!   uint32_t base           = 0;
2806!   uint32_t tx_dma_base    = 0;
2807!
2808!   if ( NULL == channel ) {
2809!     return;
2810!   }
2811 
2812!   base        = channel->uart_baseAddress;
2813!   tx_dma_base = channel->uart_txDmaBaseAddress;
2814!   /**
2815!    * RX based DMA and interrupt is not supported yet
2816!    * uint32_t tx_dma_base    = 0;
2817!    *
2818!    * rx_dma_base = channel->uart_rxDmaBaseAddress;
2819!    */
2820 
2821 
2822!   *(uint16_t volatile *) (base + UART_IER_OFFSET) = 0;
2823!
2824!   if ( 0 != channel->uart_baud) {
2825!     divisor = (uint16_t) (uartsConfig->freq /
2826!         (channel->uart_baud * 16));
2827!   } else {
2828!     divisor = (uint16_t) (uartsConfig->freq / (9600 * 16));
2829    }
2830 
2831!   *(uint16_t volatile *) (base + UART_LCR_OFFSET) = UART_LCR_DLAB;
2832!   *(uint16_t volatile *) (base + UART_DLL_OFFSET) = (divisor & 0xff);
2833!   *(uint16_t volatile *) (base + UART_DLH_OFFSET) = ((divisor >> 8) & 0xff);
2834 
2835!   *(uint16_t volatile *) (base + UART_LCR_OFFSET) = UART_LCR_WLS_8;
2836 
2837!   *(uint16_t volatile *) (base + UART_GCTL_OFFSET) = UART_GCTL_UCEN;
2838 
2839!   /**
2840!    * To clear previous status
2841!    * divisor is a temp variable here
2842!    */
2843!   divisor = *(uint16_t volatile *) (base + UART_LSR_OFFSET);
2844!   divisor = *(uint16_t volatile *) (base + UART_RBR_OFFSET);
2845!   divisor = *(uint16_t volatile *) (base + UART_IIR_OFFSET);
2846!
2847!   if ( channel->uart_useDma ) {
2848!     *(uint16_t  volatile *)(tx_dma_base + DMA_CONFIG_OFFSET) = 0;
2849!     *(uint16_t  volatile *)(tx_dma_base + DMA_CONFIG_OFFSET) = DMA_CONFIG_DI_EN
2850!         | DMA_CONFIG_SYNC ;
2851!     *(uint16_t  volatile *)(tx_dma_base + DMA_IRQ_STATUS_OFFSET) |=
2852!         DMA_IRQ_STATUS_DMA_DONE | DMA_IRQ_STATUS_DMA_ERR;
2853!
2854!   } else {
2855!     /**
2856!     * We use polling or interrupts only sending one char at a time :(
2857!     */
2858!   }
2859!
2860!   return;
2861  }
2862 
2863+
2864+ /**
2865+  * Set the UART attributes.
2866+  * @param minor
2867+  * @param termios
2868+  * @return
2869+  */
2870  static int setAttributes(int minor, const struct termios *termios) {
2871!   uint32_t base;
2872    int baud;
2873    uint16_t divisor;
2874    uint16_t lcr;
2875 
2876!   base = uartsConfig->channels[minor].uart_baseAddress;
2877    switch (termios->c_cflag & CBAUD) {
2878    case B0:
2879      baud = 0;
2880***************
2881*** 260,267 ****
2882      baud = -1;
2883      break;
2884    }
2885!   if (baud > 0 && uartsConfig->channels[minor].force_baud)
2886!     baud = uartsConfig->channels[minor].force_baud;
2887    switch (termios->c_cflag & CSIZE) {
2888    case CS5:
2889      lcr = UART_LCR_WLS_5;
2890--- 274,281 ----
2891      baud = -1;
2892      break;
2893    }
2894!   if (baud > 0 && uartsConfig->channels[minor].uart_baud)
2895!     baud = uartsConfig->channels[minor].uart_baud;
2896    switch (termios->c_cflag & CSIZE) {
2897    case CS5:
2898      lcr = UART_LCR_WLS_5;
2899***************
2900*** 282,289 ****
2901      lcr |= UART_LCR_PEN | UART_LCR_EPS;
2902      break;
2903    case PARENB | PARODD:
2904!     lcr |= UART_LCR_PEN;
2905!     break;
2906    default:
2907      break;
2908    }
2909--- 296,303 ----
2910      lcr |= UART_LCR_PEN | UART_LCR_EPS;
2911      break;
2912    case PARENB | PARODD:
2913!   lcr |= UART_LCR_PEN;
2914!   break;
2915    default:
2916      break;
2917    }
2918***************
2919*** 301,414 ****
2920    return 0;
2921  }
2922 
2923! void bfin_uart_isr(int source) {
2924!   int i;
2925!   char *base;
2926!   uint16_t uartStat;
2927!   char c;
2928!   uint8_t uartLSR;
2929!
2930!   /* Just use one ISR and check for all UART interrupt sources in it.
2931!      This is less efficient than making use of the vector to narrow down
2932!      the things we need to check, but not all Blackfins separate the
2933!      UART interrupt sources in the same ways.  This way we don't have
2934!      to make this code dependent on the type of Blackfin.  */
2935!   for (i = 0; i < uartsConfig->num_channels; i++) {
2936!     if (uartsConfig->channels[i].use_interrupts) {
2937!       base = uartsConfig->channels[i].base_address;
2938!       uartStat = *(uint16_t volatile *) (base + UART_IIR_OFFSET);
2939!       if ((uartStat & UART_IIR_NINT) == 0) {
2940!         switch (uartStat & UART_IIR_STATUS_MASK) {
2941!         case UART_IIR_STATUS_THRE:
2942!           if (uartsConfig->channels[i].termios &&
2943!               (uartsConfig->channels[i].flags & BFIN_UART_XMIT_BUSY)) {
2944!             uartsConfig->channels[i].flags &= ~BFIN_UART_XMIT_BUSY;
2945!             rtems_termios_dequeue_characters(uartsConfig->channels[i].termios,
2946!                                              1);
2947!           }
2948!           break;
2949!         case UART_IIR_STATUS_RDR:
2950!           c = *(uint16_t volatile *) (base + UART_RBR_OFFSET);
2951!           if (uartsConfig->channels[i].termios)
2952!             rtems_termios_enqueue_raw_characters(
2953!                 uartsConfig->channels[i].termios, &c, 1);
2954!           break;
2955!         case UART_IIR_STATUS_LS:
2956!           uartLSR = *(uint16_t volatile *) (base + UART_LSR_OFFSET);
2957!           /* break, framing error, parity error, or overrun error
2958!              has been detected */
2959!           break;
2960!         default:
2961!           break;
2962!         }
2963!       }
2964!     }
2965    }
2966  }
2967 
2968! rtems_status_code bfin_uart_initialize(rtems_device_major_number major,
2969!                                        bfin_uart_config_t *config) {
2970!   rtems_status_code status;
2971!   int i;
2972 
2973!   status = RTEMS_SUCCESSFUL;
2974 
2975-   rtems_termios_initialize();
2976 
2977!   /*
2978!    *  Register Device Names
2979     */
2980 
2981!   uartsConfig = config;
2982!   for (i = 0; i < config->num_channels; i++) {
2983!     config->channels[i].termios = NULL;
2984!     config->channels[i].flags = 0;
2985!     initializeHardware(i);
2986!     status = rtems_io_register_name(config->channels[i].name, major, i);
2987    }
2988 
2989!    return RTEMS_SUCCESSFUL;
2990  }
2991 
2992  rtems_device_driver bfin_uart_open(rtems_device_major_number major,
2993!                                    rtems_device_minor_number minor,
2994!                                    void *arg) {
2995!   rtems_status_code sc;
2996!   rtems_libio_open_close_args_t *args;
2997    static const rtems_termios_callbacks pollCallbacks = {
2998!     NULL,                        /* firstOpen */
2999!     NULL,                        /* lastClose */
3000!     pollRead,                    /* pollRead */
3001!     pollWrite,                   /* write */
3002!     setAttributes,               /* setAttributes */
3003!     NULL,                        /* stopRemoteTx */
3004!     NULL,                        /* startRemoteTx */
3005!     TERMIOS_POLLED               /* outputUsesInterrupts */
3006    };
3007    static const rtems_termios_callbacks interruptCallbacks = {
3008!     NULL,                        /* firstOpen */
3009!     NULL,                        /* lastClose */
3010!     NULL,                        /* pollRead */
3011!     interruptWrite,              /* write */
3012!     setAttributes,               /* setAttributes */
3013!     NULL,                        /* stopRemoteTx */
3014!     NULL,                        /* startRemoteTx */
3015!     TERMIOS_IRQ_DRIVEN           /* outputUsesInterrupts */
3016    };
3017 
3018!   if (uartsConfig == NULL || minor < 0 || minor >= uartsConfig->num_channels)
3019      return RTEMS_INVALID_NUMBER;
3020 
3021-   sc = rtems_termios_open(major, minor, arg,
3022-                           uartsConfig->channels[minor].use_interrupts ?
3023-                           &interruptCallbacks : &pollCallbacks);
3024    args = arg;
3025    uartsConfig->channels[minor].termios = args->iop->data1;
3026 
3027!   if (uartsConfig->channels[minor].use_interrupts)
3028!     enableInterrupts(minor);
3029!   atexit(disableAllInterrupts);
3030 
3031    return sc;
3032  }
3033 
3034--- 315,640 ----
3035    return 0;
3036  }
3037 
3038! /**
3039!  * Interrupt based uart tx routine. The routine writes one character at a time.
3040!  *
3041!  * @param minor Minor number to indicate uart number
3042!  * @param buf Character buffer which stores characters to be transmitted.
3043!  * @param len Length of buffer to be transmitted.
3044!  * @return
3045!  */
3046! static ssize_t uart_interruptWrite(int minor, const char *buf, size_t len) {
3047!   uint32_t              base      = 0;
3048!   bfin_uart_channel_t*  channel   = NULL;
3049!   rtems_interrupt_level isrLevel;
3050!
3051!   /**
3052!    * Sanity Check
3053!    */
3054!   if (NULL == buf || NULL == channel || NULL == uartsConfig || minor < 0) {
3055!     return 0;
3056!   }
3057!
3058!   channel = &(uartsConfig->channels[minor]);
3059!
3060!   if ( NULL == channel || channel->flags &  BFIN_UART_XMIT_BUSY ) {
3061!     return 0;
3062    }
3063+
3064+   rtems_interrupt_disable(isrLevel);
3065+
3066+   base = channel->uart_baseAddress;
3067+
3068+   channel->flags |= BFIN_UART_XMIT_BUSY;
3069+   channel->length = 1;
3070+   *(uint16_t volatile *) (base + UART_THR_OFFSET) = *buf;
3071+   *(uint16_t volatile *) (base + UART_IER_OFFSET) = UART_IER_ETBEI;
3072+
3073+   rtems_interrupt_enable(isrLevel);
3074+
3075+   return 0;
3076  }
3077 
3078! /**
3079! * This function implements RX ISR
3080! */
3081! void bfinUart_rxIsr(void *_arg)
3082! {
3083!   /**
3084!    * TODO: UART RX ISR implementation.
3085!    */
3086 
3087! }
3088 
3089 
3090! /**
3091!  * This function implements TX ISR. The function gets called when the TX FIFO is
3092!  * empty. It clears the interrupt and dequeues the character. It only tx one
3093!  * character at a time.
3094!  *
3095!  * TODO: error handling.
3096!  * @param _arg gets the channel information.
3097!  */
3098! void bfinUart_txIsr(void *_arg) {
3099!   bfin_uart_channel_t*  channel = NULL;
3100!   uint32_t              base    = 0;
3101!
3102!   /**
3103!    * Sanity check
3104     */
3105+   if (NULL == _arg) {
3106+     /** It should never be NULL */
3107+     return;
3108+   }
3109 
3110!   channel = (bfin_uart_channel_t *) _arg;
3111!
3112!   base = channel->uart_baseAddress;
3113!
3114!   *(uint16_t volatile *) (base + UART_IER_OFFSET) &= ~UART_IER_ETBEI;
3115!   channel->flags &= ~BFIN_UART_XMIT_BUSY;
3116!
3117!   rtems_termios_dequeue_characters(channel->termios, channel->length);
3118!
3119!   return;
3120! }
3121!
3122!
3123!
3124!
3125! /**
3126!  * interrupt based DMA write Routine. It configure the DMA to write len bytes.
3127!  * The DMA supports 64K data only.
3128!  *
3129!  * @param minor Identification number of the UART.
3130!  * @param buf Character buffer pointer
3131!  * @param len length of data items to be written
3132!  * @return data already written
3133!  */
3134! static ssize_t uart_DmaWrite(int minor, const char *buf, size_t len) {
3135!   uint32_t              base        = 0;
3136!   bfin_uart_channel_t*  channel     = NULL;
3137!   uint32_t              tx_dma_base = 0;
3138!   rtems_interrupt_level isrLevel;
3139!
3140!   /**
3141!    * Sanity Check
3142!    */
3143!   if ( NULL == buf || 0 > minor || NULL == uartsConfig ) {
3144!     return 0;
3145!   }
3146!
3147!   channel = &(uartsConfig->channels[minor]);
3148!
3149!   /**
3150!    * Sanity Check and check for transmit busy.
3151!    */
3152!   if ( NULL == channel || BFIN_UART_XMIT_BUSY & channel->flags ) {
3153!     return 0;
3154!   }
3155!
3156!   rtems_interrupt_disable(isrLevel);
3157!
3158!   base        = channel->uart_baseAddress;
3159!   tx_dma_base = channel->uart_txDmaBaseAddress;
3160!
3161!   channel->flags |= BFIN_UART_XMIT_BUSY;
3162!   channel->length = len;
3163!
3164!   *(uint16_t volatile *) (tx_dma_base + DMA_CONFIG_OFFSET) &= ~DMA_CONFIG_DMAEN;
3165!   *(uint32_t volatile *) (tx_dma_base + DMA_START_ADDR_OFFSET) = (uint32_t)buf;
3166!   *(uint16_t volatile *) (tx_dma_base + DMA_X_COUNT_OFFSET) = channel->length;
3167!   *(uint16_t volatile *) (tx_dma_base + DMA_X_MODIFY_OFFSET) = 1;
3168!   *(uint16_t volatile *) (tx_dma_base + DMA_CONFIG_OFFSET) |= DMA_CONFIG_DMAEN;
3169!   *(uint16_t volatile *) (base + UART_IER_OFFSET) = UART_IER_ETBEI;
3170!
3171!   rtems_interrupt_enable(isrLevel);
3172!
3173!   return 0;
3174! }
3175!
3176!
3177! /**
3178!  * RX DMA ISR.
3179!  * The polling route is used for receiving the characters. This is a place
3180!  * holder for future implementation.
3181!  * @param _arg
3182!  */
3183! void bfinUart_rxDmaIsr(void *_arg) {
3184! /**
3185!  * TODO: Implementation of RX DMA
3186!  */
3187! }
3188!
3189! /**
3190!  * This function implements TX dma ISR. It clears the IRQ and dequeues a char
3191!  * The channel argument will have the base address. Since there are two uart
3192!  * and both the uarts can use the same tx dma isr.
3193!  *
3194!  * TODO: 1. Error checking 2. sending correct length ie after looking at the
3195!  * number of elements the uart transmitted.
3196!  *
3197!  * @param _arg argument passed to the interrupt handler. It contains the
3198!  * channel argument.
3199!  */
3200! void bfinUart_txDmaIsr(void *_arg) {
3201!   bfin_uart_channel_t*  channel     = NULL;
3202!   uint32_t              tx_dma_base = 0;
3203!
3204!   /**
3205!    * Sanity check
3206!    */
3207!   if (NULL == _arg) {
3208!     /** It should never be NULL */
3209!     return;
3210!   }
3211!
3212!   channel = (bfin_uart_channel_t *) _arg;
3213!
3214!   tx_dma_base = channel->uart_txDmaBaseAddress;
3215!
3216!   if ((*(uint16_t volatile *) (tx_dma_base + DMA_IRQ_STATUS_OFFSET)
3217!       & DMA_IRQ_STATUS_DMA_DONE)) {
3218!
3219!     *(uint16_t volatile *) (tx_dma_base + DMA_IRQ_STATUS_OFFSET)
3220!                           |= DMA_IRQ_STATUS_DMA_DONE | DMA_IRQ_STATUS_DMA_ERR;
3221!     channel->flags &= ~BFIN_UART_XMIT_BUSY;
3222!     rtems_termios_dequeue_characters(channel->termios, channel->length);
3223!   } else {
3224!     /* UART DMA did not generate interrupt.
3225!      * This routine must not be called.
3226!      */
3227    }
3228 
3229!   return;
3230! }
3231!
3232! /**
3233!  * Function called during exit
3234!  */
3235! void uart_exit(void)
3236! {
3237!   /**
3238!    * TODO: Flushing of quques
3239!    */
3240!
3241  }
3242 
3243+ /**
3244+  * Opens the device in different modes. The supported modes are
3245+  * 1. Polling
3246+  * 2. Interrupt
3247+  * 3. DMA
3248+  * At exit the uart_Exit function will be called to flush the device.
3249+  *
3250+  * @param major Major number of the device
3251+  * @param minor Minor number of the device
3252+  * @param arg
3253+  * @return
3254+  */
3255  rtems_device_driver bfin_uart_open(rtems_device_major_number major,
3256!     rtems_device_minor_number minor, void *arg) {
3257!   rtems_status_code             sc    = RTEMS_NOT_DEFINED;;
3258!   rtems_libio_open_close_args_t *args = NULL;
3259!
3260!   /**
3261!    * Callback function for polling
3262!    */
3263    static const rtems_termios_callbacks pollCallbacks = {
3264!       NULL,                        /* firstOpen */
3265!       NULL,                        /* lastClose */
3266!       pollRead,                    /* pollRead */
3267!       pollWrite,                   /* write */
3268!       setAttributes,               /* setAttributes */
3269!       NULL,                        /* stopRemoteTx */
3270!       NULL,                        /* startRemoteTx */
3271!       TERMIOS_POLLED               /* outputUsesInterrupts */
3272    };
3273+
3274+   /**
3275+    * Callback function for interrupt based transfers without DMA.
3276+    * We use interrupts for writing only. For reading we use polling.
3277+    */
3278    static const rtems_termios_callbacks interruptCallbacks = {
3279!       NULL,                        /* firstOpen */
3280!       NULL,                        /* lastClose */
3281!       pollRead,                    /* pollRead */
3282!       uart_interruptWrite,              /* write */
3283!       setAttributes,               /* setAttributes */
3284!       NULL,                        /* stopRemoteTx */
3285!       NULL,                        /* startRemoteTx */
3286!       TERMIOS_IRQ_DRIVEN           /* outputUsesInterrupts */
3287!   };
3288!
3289!   /**
3290!    * Callback function for interrupt based DMA transfers.
3291!    * We use interrupts for writing only. For reading we use polling.
3292!    */
3293!   static const rtems_termios_callbacks interruptDmaCallbacks = {
3294!       NULL,                        /* firstOpen */
3295!       NULL,                        /* lastClose */
3296!       NULL,                        /* pollRead */
3297!       uart_DmaWrite,              /* write */
3298!       setAttributes,               /* setAttributes */
3299!       NULL,                        /* stopRemoteTx */
3300!       NULL,                        /* startRemoteTx */
3301!       TERMIOS_IRQ_DRIVEN           /* outputUsesInterrupts */
3302    };
3303 
3304!
3305!   if ( NULL == uartsConfig || 0 > minor || minor >= uartsConfig->num_channels) {
3306      return RTEMS_INVALID_NUMBER;
3307+   }
3308+
3309+   /**
3310+    * Opens device for handling uart send request either by
3311+    * 1. interrupt with DMA
3312+    * 2. interrupt based
3313+    * 3. Polling
3314+    */
3315+   if ( uartsConfig->channels[minor].uart_useDma ) {
3316+     sc = rtems_termios_open(major, minor, arg, &interruptDmaCallbacks);
3317+   } else {
3318+     sc = rtems_termios_open(major, minor, arg,
3319+         uartsConfig->channels[minor].uart_useInterrupts ?
3320+             &interruptCallbacks : &pollCallbacks);
3321+   }
3322 
3323    args = arg;
3324    uartsConfig->channels[minor].termios = args->iop->data1;
3325 
3326!   atexit(uart_exit);
3327 
3328    return sc;
3329  }
3330 
3331+
3332+ /**
3333+ * Uart initialization function.
3334+ * @param major major number of the device
3335+ * @param config configuration parameters
3336+ * @return rtems status code
3337+ */
3338+ rtems_status_code bfin_uart_initialize(rtems_device_major_number major,
3339+     bfin_uart_config_t *config) {
3340+   rtems_status_code sc = RTEMS_NOT_DEFINED;
3341+   int               i  = 0;
3342+
3343+   rtems_termios_initialize();
3344+
3345+   /*
3346+    *  Register Device Names
3347+    */
3348+   uartsConfig = config;
3349+   for (i = 0; i < config->num_channels; i++) {
3350+     config->channels[i].termios = NULL;
3351+     config->channels[i].flags = 0;
3352+     initializeHardware(&(config->channels[i]));
3353+     sc = rtems_io_register_name(config->channels[i].name, major, i);
3354+     if (RTEMS_SUCCESSFUL != sc) {
3355+       return sc;
3356+     }
3357+   }
3358+
3359+   return sc;
3360+ }
3361diff -crBN -X exclude rtems_orig/c/src/lib/libcpu/bfin/serial/uart.h rtems/c/src/lib/libcpu/bfin/serial/uart.h
3362*** rtems_orig/c/src/lib/libcpu/bfin/serial/uart.h      2011-04-19 11:04:26.000000000 -0400
3363--- rtems/c/src/lib/libcpu/bfin/serial/uart.h   2011-04-12 18:05:42.000000000 -0400
3364***************
3365*** 8,35 ****
3366   *  found in the file LICENSE in this distribution or at
3367   *  http://www.rtems.com/license/LICENSE.
3368   *
3369!  *  $Id: uart.h,v 1.3 2009/11/30 05:03:49 ralf Exp $
3370   */
3371 
3372! #ifndef _uart_h_
3373! #define _uart_h_
3374 
3375 
3376  #ifdef __cplusplus
3377  extern "C" {
3378  #endif
3379 
3380!
3381  typedef struct {
3382!   const char *name;
3383!   void *base_address;
3384!   bool  use_interrupts;
3385!   int force_baud;
3386!   /* the following are for internal use */
3387!   void *termios;
3388!   uint8_t volatile flags;
3389  } bfin_uart_channel_t;
3390 
3391  typedef struct {
3392    uint32_t freq;
3393    int num_channels;
3394--- 8,45 ----
3395   *  found in the file LICENSE in this distribution or at
3396   *  http://www.rtems.com/license/LICENSE.
3397   *
3398!  *  Modified:
3399!  *  $Author: rkangral $ Added interrupt support and DMA support
3400!  *
3401!  *  $Id: uart.h 47 2011-04-12 22:05:42Z rkangral $
3402   */
3403 
3404!
3405! #ifndef _UART_H_
3406! #define _UART_H_
3407 
3408 
3409  #ifdef __cplusplus
3410  extern "C" {
3411  #endif
3412 
3413! /** bfin_uart_channel object
3414!  */
3415  typedef struct {
3416!   const char        *name;                 /** Holds name of the device */
3417!   uint32_t          uart_baseAddress;           /** UART base address */
3418!   uint32_t          uart_rxDmaBaseAddress;      /** RX DMA base address */
3419!   uint32_t          uart_txDmaBaseAddress;      /** TX DMA base address */
3420!   bool              uart_useInterrupts;         /** are interrupts used */
3421!   bool              uart_useDma;                /** is dma used */
3422!   int               uart_baud;                  /** baud rate, 0 for default */
3423!
3424!   void              *termios;                   /** termios associated */
3425!   uint8_t volatile  flags;                      /** flags for internal use */
3426!   uint16_t          length;                     /** length for internal use */
3427  } bfin_uart_channel_t;
3428 
3429+
3430  typedef struct {
3431    uint32_t freq;
3432    int num_channels;
3433***************
3434*** 36,59 ****
3435    bfin_uart_channel_t *channels;
3436  } bfin_uart_config_t;
3437 
3438 
3439! char bfin_uart_poll_read(int minor);
3440 
3441  void bfin_uart_poll_write(int minor, char c);
3442 
3443  rtems_status_code bfin_uart_initialize(rtems_device_major_number major,
3444!                                        bfin_uart_config_t *config);
3445 
3446  rtems_device_driver bfin_uart_open(rtems_device_major_number major,
3447!                                    rtems_device_minor_number minor,
3448!                                    void *arg);
3449 
3450! void bfin_uart_isr(int source);
3451 
3452 
3453  #ifdef __cplusplus
3454  }
3455  #endif
3456 
3457! #endif /* _uart_h_ */
3458 
3459--- 46,140 ----
3460    bfin_uart_channel_t *channels;
3461  } bfin_uart_config_t;
3462 
3463+ /**
3464+  * @param base_address defines the UART base address
3465+  * @param source defines the source that caused the interrupt. This argument
3466+  * will help us in identifying if Rx or TX caused the interrupt.
3467+  */
3468+ typedef struct {
3469+   uint32_t base_address;
3470+   int source;
3471+ } bfin_uart_arg_t;
3472+
3473 
3474!
3475! char bfin_uart_poll_read(rtems_device_minor_number minor);
3476 
3477  void bfin_uart_poll_write(int minor, char c);
3478 
3479+
3480+ /**
3481+ * Uart initialization function.
3482+ * @param major major number of the device
3483+ * @param config configuration parameters
3484+ * @return rtems status code
3485+ */
3486  rtems_status_code bfin_uart_initialize(rtems_device_major_number major,
3487!     bfin_uart_config_t *config);
3488!
3489!
3490 
3491+ /**
3492+  * Opens the device in different modes. The supported modes are
3493+  * 1. Polling
3494+  * 2. Interrupt
3495+  * 3. DMA
3496+  * At exit the uart_Exit function will be called to flush the device.
3497+  *
3498+  * @param major Major number of the device
3499+  * @param minor Minor number of the device
3500+  * @param arg
3501+  * @return
3502+  */
3503  rtems_device_driver bfin_uart_open(rtems_device_major_number major,
3504!     rtems_device_minor_number minor, void *arg);
3505!
3506!
3507!
3508! /**
3509!  * This function implements TX dma ISR. It clears the IRQ and dequeues a char
3510!  * The channel argument will have the base address. Since there are two uart
3511!  * and both the uarts can use the same tx dma isr.
3512!  *
3513!  * TODO: 1. Error checking 2. sending correct length ie after looking at the
3514!  * number of elements the uart transmitted.
3515!  *
3516!  * @param _arg argument passed to the interrupt handler. It contains the
3517!  * channel argument.
3518!  */
3519! void bfinUart_txDmaIsr(void *_arg);
3520!
3521!
3522!
3523! /**
3524!  * RX DMA ISR.
3525!  * The polling route is used for receiving the characters. This is a place
3526!  * holder for future implementation.
3527!  * @param _arg
3528!  */
3529! void bfinUart_rxDmaIsr(void *_arg);
3530!
3531!
3532! /**
3533!  * This function implements TX ISR. The function gets called when the TX FIFO is
3534!  * empty. It clears the interrupt and dequeues the character. It only tx one
3535!  * character at a time.
3536!  *
3537!  * TODO: error handling.
3538!  * @param _arg gets the channel information.
3539!  */
3540! void bfinUart_txIsr(void *_arg);
3541!
3542 
3543! /**
3544! * This function implements RX ISR
3545! */
3546! void bfinUart_rxIsr(void *_arg);
3547 
3548 
3549  #ifdef __cplusplus
3550  }
3551  #endif
3552 
3553! #endif /* _UART_H_ */
3554 
3555diff -crBN -X exclude rtems_orig/cpukit/score/cpu/bfin/Makefile.am rtems/cpukit/score/cpu/bfin/Makefile.am
3556*** rtems_orig/cpukit/score/cpu/bfin/Makefile.am        2011-04-19 11:04:26.000000000 -0400
3557--- rtems/cpukit/score/cpu/bfin/Makefile.am     2011-02-14 18:39:06.000000000 -0500
3558***************
3559*** 8,14 ****
3560  include_rtems_HEADERS = rtems/asm.h
3561 
3562  include_rtems_bfindir = $(includedir)/rtems/bfin
3563! include_rtems_bfin_HEADERS = rtems/bfin/bfin.h rtems/bfin/bf533.h
3564 
3565  include_rtems_scoredir = $(includedir)/rtems/score
3566  include_rtems_score_HEADERS = rtems/score/cpu.h rtems/score/bfin.h \
3567--- 8,14 ----
3568  include_rtems_HEADERS = rtems/asm.h
3569 
3570  include_rtems_bfindir = $(includedir)/rtems/bfin
3571! include_rtems_bfin_HEADERS = rtems/bfin/bfin.h rtems/bfin/bf533.h rtems/bfin/bf52x.h
3572 
3573  include_rtems_scoredir = $(includedir)/rtems/score
3574  include_rtems_score_HEADERS = rtems/score/cpu.h rtems/score/bfin.h \
3575diff -crBN -X exclude rtems_orig/cpukit/score/cpu/bfin/preinstall.am rtems/cpukit/score/cpu/bfin/preinstall.am
3576*** rtems_orig/cpukit/score/cpu/bfin/preinstall.am      2011-04-19 11:04:26.000000000 -0400
3577--- rtems/cpukit/score/cpu/bfin/preinstall.am   2011-02-14 18:39:06.000000000 -0500
3578***************
3579*** 35,40 ****
3580--- 35,44 ----
3581        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/bfin/bf533.h
3582  PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/bfin/bf533.h
3583 
3584+ $(PROJECT_INCLUDE)/rtems/bfin/bf52x.h: rtems/bfin/bf52x.h $(PROJECT_INCLUDE)/rtems/bfin/$(dirstamp)
3585+       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/bfin/bf52x.h
3586+ PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/bfin/bf52x.h
3587+
3588  $(PROJECT_INCLUDE)/rtems/score/$(dirstamp):
3589        @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score
3590        @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
3591diff -crBN -X exclude rtems_orig/cpukit/score/cpu/bfin/rtems/bfin/bf52x.h rtems/cpukit/score/cpu/bfin/rtems/bfin/bf52x.h
3592*** rtems_orig/cpukit/score/cpu/bfin/rtems/bfin/bf52x.h 1969-12-31 19:00:00.000000000 -0500
3593--- rtems/cpukit/score/cpu/bfin/rtems/bfin/bf52x.h      2011-02-22 17:19:49.000000000 -0500
3594***************
3595*** 0 ****
3596--- 1,431 ----
3597+ /**
3598+  *@file bf52x.h
3599+  *
3600+  *  This file defines basic MMR for the Blackfin 52x CPU.
3601+  *  The MMR have been taken from the ADSP-BF52x Blackfin Processor
3602+  *  Hardware Reference from Analog Devices. Mentioned Chapters
3603+  *  refer to this Documentation.
3604+  *
3605+  *    Based on bf533.h
3606+  *
3607+  *  COPYRIGHT (c) 2006.
3608+  *  Atos Automacao Industrial LTDA.
3609+  *             modified by Alain Schaefer <alain.schaefer@easc.ch>
3610+  *                     and Antonio Giovanini <antonio@atos.com.br>
3611+  *
3612+  *  The license and distribution terms for this file may be
3613+  *  found in the file LICENSE in this distribution or at
3614+  *  http://www.rtems.com/license/LICENSE.
3615+  *
3616+  *
3617+  * @author    Rohan Kangralkar, ECE Department Northeastern University
3618+  * @date        02/15/2011
3619+  *
3620+  * HISTORY:
3621+  * $Id$
3622+  *
3623+  *
3624+  */
3625+
3626+ #ifndef _RTEMS_BFIN_52x_H
3627+ #define _RTEMS_BFIN_52x_H
3628+
3629+ #include <rtems/bfin/bfin.h>
3630+
3631+ #ifdef __cplusplus
3632+ extern "C" {
3633+ #endif
3634+
3635+
3636+ /* Clock and System Control  Chapter 8 */
3637+ #define PLL_CTL                0xFFC00000L
3638+ #define PLL_DIV                0xFFC00004L
3639+ #define VR_CTL                 0xFFC00008L
3640+ #define PLL_STAT               0xFFC0000CL
3641+ #define PLL_LOCKCNT            0xFFC00010L
3642+ #define SWRST                  0xFFC00100L
3643+ #define SYSCR                  0xFFC00104L
3644+
3645+ /* SPI Controller           Chapter 10 */
3646+ #define SPI_CTL                0xFFC00500L
3647+ #define SPI_FLG                0xFFC00504L
3648+ #define SPI_STAT               0xFFC00508L
3649+ #define SPI_TDBR               0xFFC0050CL
3650+ #define SPI_RDBR               0xFFC00510L
3651+ #define SPI_BAUD               0xFFC00514L
3652+ #define SPI_SHADOW             0xFFC00518L
3653+
3654+ /* SPORT0 Controller */
3655+ #define SPORT0_TCR1            0xFFC00800L
3656+ #define SPORT0_TCR2            0xFFC00804L
3657+ #define SPORT0_TCLKDIV         0xFFC00808L
3658+ #define SPORT0_TFSDIV          0xFFC0080CL
3659+ #define SPORT0_TX              0xFFC00810L
3660+ #define SPORT0_RX              0xFFC00818L
3661+ #define SPORT0_RCR1            0xFFC00820L
3662+ #define SPORT0_RCR2            0xFFC00824L
3663+ #define SPORT0_RCLKDIV         0xFFC00828L
3664+ #define SPORT0_RFSDIV          0xFFC0082CL
3665+ #define SPORT0_STAT            0xFFC00830L
3666+ #define SPORT0_CHNL            0xFFC00834L
3667+ #define SPORT0_MCMC1           0xFFC00838L
3668+ #define SPORT0_MCMC2           0xFFC0083CL
3669+ #define SPORT0_MTCS0           0xFFC00840L
3670+ #define SPORT0_MTCS1           0xFFC00844L
3671+ #define SPORT0_MTCS2           0xFFC00848L
3672+ #define SPORT0_MTCS3           0xFFC0084CL
3673+ #define SPORT0_MRCS0           0xFFC00850L
3674+ #define SPORT0_MRCS1           0xFFC00854L
3675+ #define SPORT0_MRCS2           0xFFC00858L
3676+ #define SPORT0_MRCS3           0xFFC0085CL
3677+
3678+ /* Parallel Peripheral Interface (PPI) Chapter 11 */
3679+
3680+ #define PPI_CONTROL            0xFFC01000L
3681+ #define PPI_STATUS             0xFFC01004L
3682+ #define PPI_COUNT              0xFFC01008L
3683+ #define PPI_DELAY              0xFFC0100CL
3684+ #define PPI_FRAME              0xFFC01010L
3685+
3686+ /*********  PPI MASKS ***********/
3687+ /*  PPI_CONTROL Masks */
3688+ #define PORT_EN                0x00000001
3689+ #define PORT_DIR               0x00000002
3690+ #define XFR_TYPE               0x0000000C
3691+ #define PORT_CFG               0x00000030
3692+ #define FLD_SEL                0x00000040
3693+ #define PACK_EN                0x00000080
3694+ #define DMA32                  0x00000100
3695+ #define SKIP_EN                0x00000200
3696+ #define SKIP_EO                0x00000400
3697+ #define DLENGTH                0x00003800
3698+ #define DLEN_8                 0x0
3699+ #define DLEN(x)                (((x-9) & 0x07) << 11)
3700+ #define POL                    0x0000C000
3701+
3702+ /* PPI_STATUS Masks */
3703+ #define FLD                    0x00000400
3704+ #define FT_ERR                 0x00000800
3705+ #define OVR                    0x00001000
3706+ #define UNDR                   0x00002000
3707+ #define ERR_DET                0x00004000
3708+ #define ERR_NCOR               0x00008000
3709+
3710+ /* SPORT1 Controller        Chapter 12 */
3711+ #define SPORT1_TCR1            0xFFC00900L
3712+ #define SPORT1_TCR2            0xFFC00904L
3713+ #define SPORT1_TCLKDIV         0xFFC00908L
3714+ #define SPORT1_TFSDIV          0xFFC0090CL
3715+ #define SPORT1_TX              0xFFC00910L
3716+ #define SPORT1_RX              0xFFC00918L
3717+ #define SPORT1_RCR1            0xFFC00920L
3718+ #define SPORT1_RCR2            0xFFC00924L
3719+ #define SPORT1_RCLKDIV         0xFFC00928L
3720+ #define SPORT1_RFSDIV          0xFFC0092CL
3721+ #define SPORT1_STAT            0xFFC00930L
3722+ #define SPORT1_CHNL            0xFFC00934L
3723+ #define SPORT1_MCMC1           0xFFC00938L
3724+ #define SPORT1_MCMC2           0xFFC0093CL
3725+ #define SPORT1_MTCS0           0xFFC00940L
3726+ #define SPORT1_MTCS1           0xFFC00944L
3727+ #define SPORT1_MTCS2           0xFFC00948L
3728+ #define SPORT1_MTCS3           0xFFC0094CL
3729+ #define SPORT1_MRCS0           0xFFC00950L
3730+ #define SPORT1_MRCS1           0xFFC00954L
3731+ #define SPORT1_MRCS2           0xFFC00958L
3732+ #define SPORT1_MRCS3           0xFFC0095CL
3733+
3734+ /* SPORTx_TCR1 Masks */
3735+ #define TSPEN                  0x0001
3736+ #define ITCLK                  0x0002
3737+ #define TDTYPE                 0x000C
3738+ #define TLSBIT                 0x0010
3739+ #define ITFS                   0x0200
3740+ #define TFSR                   0x0400
3741+ #define DITFS                  0x0800
3742+ #define LTFS                   0x1000
3743+ #define LATFS                  0x2000
3744+ #define TCKFE                  0x4000
3745+
3746+ /* SPORTx_TCR2 Masks */
3747+ #define SLEN                   0x001F
3748+ #define TXSE                   0x0100
3749+ #define TSFSE                  0x0200
3750+ #define TRFST                  0x0400
3751+
3752+ /* SPORTx_RCR1 Masks */
3753+ #define RSPEN                  0x0001
3754+ #define IRCLK                  0x0002
3755+ #define RDTYPE                 0x000C
3756+ #define RULAW                  0x0008
3757+ #define RALAW                  0x000C
3758+ #define RLSBIT                 0x0010
3759+ #define IRFS                   0x0200
3760+ #define RFSR                   0x0400
3761+ #define LRFS                   0x1000
3762+ #define LARFS                  0x2000
3763+ #define RCKFE                  0x4000
3764+
3765+ /* SPORTx_RCR2 Masks */
3766+ #define SLEN                   0x001F
3767+ #define RXSE                   0x0100
3768+ #define RSFSE                  0x0200
3769+ #define RRFST                  0x0400
3770+
3771+ /* SPORTx_STAT Masks */
3772+ #define RXNE                   0x0001
3773+ #define RUVF                   0x0002
3774+ #define ROVF                   0x0004
3775+ #define TXF                    0x0008
3776+ #define TUVF                   0x0010
3777+ #define TOVF                   0x0020
3778+ #define TXHRE                  0x0040
3779+
3780+ /* SPORTx_MCMC1 Masks */
3781+ #define WSIZE                  0x0000F000
3782+ #define WOFF                   0x000003FF
3783+
3784+ /* SPORTx_MCMC2 Masks */
3785+ #define MCCRM                  0x00000003
3786+ #define MCDTXPE                0x00000004
3787+ #define MCDRXPE                0x00000008
3788+ #define MCMEN                  0x00000010
3789+ #define FSDR                   0x00000080
3790+ #define MFD                    0x0000F000
3791+
3792+ /* UART Controller          Chapter 13 */
3793+ #define UART_THR               0xFFC00400L
3794+ #define UART_RBR               0xFFC00400L
3795+ #define UART_DLL               0xFFC00400L
3796+ #define UART_IER               0xFFC00404L
3797+ #define UART_DLH               0xFFC00404L
3798+ #define UART_IIR               0xFFC00408L
3799+ #define UART_LCR               0xFFC0040CL
3800+ #define UART_MCR               0xFFC00410L
3801+ #define UART_LSR               0xFFC00414L
3802+ #define UART_SCR               0xFFC0041CL
3803+ #define UART_GCTL              0xFFC00424L
3804+
3805+ /*
3806+  * UART CONTROLLER MASKS
3807+  */
3808+
3809+ /* UART_LCR */
3810+ #define DLAB                   0x80
3811+ #define SB                     0x40
3812+ #define STP                    0x20
3813+ #define EPS                    0x10
3814+ #define PEN                    0x08
3815+ #define STB                    0x04
3816+ #define WLS(x)                 ((x-5) & 0x03)
3817+
3818+ #define DLAB_P                 0x07
3819+ #define SB_P                   0x06
3820+ #define STP_P                  0x05
3821+ #define EPS_P                  0x04
3822+ #define PEN_P                  0x03
3823+ #define STB_P                  0x02
3824+ #define WLS_P1                 0x01
3825+ #define WLS_P0                 0x00
3826+
3827+ /* UART_MCR */
3828+ #define LOOP_ENA               0x10
3829+ #define LOOP_ENA_P             0x04
3830+
3831+ /* UART_LSR */
3832+ #define TEMT                   0x40
3833+ #define THRE                   0x20
3834+ #define BI                     0x10
3835+ #define FE                     0x08
3836+ #define PE                     0x04
3837+ #define OE                     0x02
3838+ #define DR                     0x01
3839+
3840+ #define TEMP_P                 0x06
3841+ #define THRE_P                 0x05
3842+ #define BI_P                   0x04
3843+ #define FE_P                   0x03
3844+ #define PE_P                   0x02
3845+ #define OE_P                   0x01
3846+ #define DR_P                   0x00
3847+
3848+ /* UART_IER */
3849+ #define ELSI                   0x04
3850+ #define ETBEI                  0x02
3851+ #define ERBFI                  0x01
3852+
3853+ #define ELSI_P                 0x02
3854+ #define ETBEI_P                0x01
3855+ #define ERBFI_P                0x00
3856+
3857+ /* UART_IIR */
3858+ #define STATUS(x)              ((x << 1) & 0x06)
3859+ #define NINT                   0x01
3860+ #define STATUS_P1              0x02
3861+ #define STATUS_P0              0x01
3862+ #define NINT_P                 0x00
3863+
3864+ /* UART_GCTL */
3865+ #define FFE                    0x20
3866+ #define FPE                    0x10
3867+ #define RPOLC                  0x08
3868+ #define TPOLC                  0x04
3869+ #define IREN                   0x02
3870+ #define UCEN                   0x01
3871+
3872+ #define FFE_P                  0x05
3873+ #define FPE_P                  0x04
3874+ #define RPOLC_P                0x03
3875+ #define TPOLC_P                0x02
3876+ #define IREN_P                 0x01
3877+ #define UCEN_P                 0x00
3878+
3879+ /* General Purpose IO        Chapter 14*/
3880+ #define FIO_FLAG_D             0xFFC00700L
3881+ #define FIO_FLAG_C             0xFFC00704L
3882+ #define FIO_FLAG_S             0xFFC00708L
3883+ #define FIO_FLAG_T             0xFFC0070CL
3884+ #define FIO_MASKA_D            0xFFC00710L
3885+ #define FIO_MASKA_C            0xFFC00714L
3886+ #define FIO_MASKA_S            0xFFC00718L
3887+ #define FIO_MASKA_T            0xFFC0071CL
3888+ #define FIO_MASKB_D            0xFFC00720L
3889+ #define FIO_MASKB_C            0xFFC00724L
3890+ #define FIO_MASKB_S            0xFFC00728L
3891+ #define FIO_MASKB_T            0xFFC0072CL
3892+ #define FIO_DIR                0xFFC00730L
3893+ #define FIO_POLAR              0xFFC00734L
3894+ #define FIO_EDGE               0xFFC00738L
3895+ #define FIO_BOTH               0xFFC0073CL
3896+ #define FIO_INEN               0xFFC00740L
3897+
3898+
3899+ /* General Purpose IO        Chapter 9*/
3900+ #define PORTH_FER              0xFFC03208
3901+ #define PORTH_MUX              0xFFC03218
3902+ #define PORTHIO_DIR            0xFFC01730
3903+ #define PORTHIO_INEN           0xFFC01740
3904+ #define PORTHIO                0xFFC01700
3905+ #define PORTHIO_SET            0xFFC01708
3906+ #define PORTHIO_CLEAR          0xFFC01704
3907+ #define PORTHIO_TOGGLE         0xFFC0170C
3908+
3909+
3910+ #define FIO_INEN               0xFFC00740L
3911+ #define FIO_POLAR              0xFFC00734L
3912+ #define FIO_EDGE               0xFFC00738L
3913+ #define FIO_BOTH               0xFFC0073CL
3914+
3915+
3916+
3917+ #define FIO_FLAG_C             0xFFC00704L
3918+ #define FIO_FLAG_S             0xFFC00708L
3919+ #define FIO_FLAG_T             0xFFC0070CL
3920+ #define FIO_MASKA_D            0xFFC00710L
3921+ #define FIO_MASKA_C            0xFFC00714L
3922+ #define FIO_MASKA_S            0xFFC00718L
3923+ #define FIO_MASKA_T            0xFFC0071CL
3924+ #define FIO_MASKB_D            0xFFC00720L
3925+ #define FIO_MASKB_C            0xFFC00724L
3926+ #define FIO_MASKB_S            0xFFC00728L
3927+ #define FIO_MASKB_T            0xFFC0072CL
3928+
3929+
3930+ /*  General Purpose IO Masks */
3931+ #define PF0                    0x0001
3932+ #define PF1                    0x0002
3933+ #define PF2                    0x0004
3934+ #define PF3                    0x0008
3935+ #define PF4                    0x0010
3936+ #define PF5                    0x0020
3937+ #define PF6                    0x0040
3938+ #define PF7                    0x0080
3939+ #define PF8                    0x0100
3940+ #define PF9                    0x0200
3941+ #define PF10                   0x0400
3942+ #define PF11                   0x0800
3943+ #define PF12                   0x1000
3944+ #define PF13                   0x2000
3945+ #define PF14                   0x4000
3946+ #define PF15                   0x8000
3947+
3948+
3949+ /* TIMER 0, 1, 2            Chapter 15 */
3950+ #define TIMER0_CONFIG          0xFFC00600L
3951+ #define TIMER0_COUNTER         0xFFC00604L
3952+ #define TIMER0_PERIOD          0xFFC00608L
3953+ #define TIMER0_WIDTH           0xFFC0060CL
3954+
3955+ #define TIMER1_CONFIG          0xFFC00610L
3956+ #define TIMER1_COUNTER         0xFFC00614L
3957+ #define TIMER1_PERIOD          0xFFC00618L
3958+ #define TIMER1_WIDTH           0xFFC0061CL
3959+
3960+ #define TIMER2_CONFIG          0xFFC00620L
3961+ #define TIMER2_COUNTER         0xFFC00624L
3962+ #define TIMER2_PERIOD          0xFFC00628L
3963+ #define TIMER2_WIDTH           0xFFC0062CL
3964+
3965+ #define TIMER_ENABLE           0xFFC00640L
3966+ #define TIMER_DISABLE          0xFFC00644L
3967+ #define TIMER_STATUS           0xFFC00648L
3968+
3969+ /* Real Time Clock          Chapter 16 */
3970+ #define RTC_STAT               0xFFC00300L
3971+ #define RTC_ICTL               0xFFC00304L
3972+ #define RTC_ISTAT              0xFFC00308L
3973+ #define RTC_SWCNT              0xFFC0030CL
3974+ #define RTC_ALARM              0xFFC00310L
3975+ #define RTC_FAST               0xFFC00314L
3976+ #define RTC_PREN               0xFFC00314L
3977+
3978+ /* RTC_FAST Mask (RTC_PREN Mask) */
3979+ #define ENABLE_PRESCALE        0x00000001
3980+ #define PREN                   0x00000001
3981+
3982+ /* Asynchronous Memory Controller EBUI, Chapter 17*/
3983+ #define EBIU_AMGCTL            0xFFC00A00L
3984+ #define EBIU_AMBCTL0           0xFFC00A04L
3985+ #define EBIU_AMBCTL1           0xFFC00A08L
3986+
3987+ /* SDRAM Controller External Bus Interface Unit */
3988+
3989+ #define EBIU_SDGCTL            0xFFC00A10L
3990+ #define EBIU_SDBCTL            0xFFC00A14L
3991+ #define EBIU_SDRRC             0xFFC00A18L
3992+ #define EBIU_SDSTAT            0xFFC00A1CL
3993+
3994+
3995+
3996+
3997+ /* DCPLB_DATA and ICPLB_DATA Registers */
3998+ /*** Bit Positions */
3999+ #define CPLB_VALID_P            0x00000000  /* 0=invalid entry, 1=valid entry */
4000+ #define CPLB_LOCK_P             0x00000001  /* 0=entry may be replaced, 1=entry locked */
4001+ #define CPLB_USER_RD_P          0x00000002  /* 0=no read access, 1=read access allowed (user mode) */
4002+ /*** Masks */
4003+ #define CPLB_VALID             0x00000001  /* 0=invalid entry, 1=valid entry */
4004+ #define CPLB_LOCK              0x00000002  /* 0=entry may be replaced, 1=entry locked */
4005+ #define CPLB_USER_RD           0x00000004  /* 0=no read access, 1=read access allowed (user mode) */
4006+ #define PAGE_SIZE_1KB          0x00000000  /* 1 KB page size */
4007+ #define PAGE_SIZE_4KB          0x00010000  /* 4 KB page size */
4008+ #define PAGE_SIZE_1MB          0x00020000  /* 1 MB page size */
4009+ #define PAGE_SIZE_4MB          0x00030000  /* 4 MB page size */
4010+ #define CPLB_PORTPRIO             0x00000200  /* 0=low priority port, 1= high priority port */
4011+ #define CPLB_L1_CHBL           0x00001000  /* 0=non-cacheable in L1, 1=cacheable in L1 */
4012+ /*** ICPLB_DATA only */
4013+ #define CPLB_LRUPRIO              0x00000100  /* 0=can be replaced by any line, 1=priority for non-replacement */
4014+ /*** DCPLB_DATA only */
4015+ #define CPLB_USER_WR           0x00000008  /* 0=no write access, 0=write access allowed (user mode) */
4016+ #define CPLB_SUPV_WR           0x00000010  /* 0=no write access, 0=write access allowed (supervisor mode) */
4017+ #define CPLB_DIRTY             0x00000080  /* 1=dirty, 0=clean */
4018+ #define CPLB_L1_AOW                       0x00008000  /* 0=do not allocate cache lines on write-through writes,  */
4019+                                                                                   /* 1= allocate cache lines on write-through writes. */
4020+ #define CPLB_WT                0x00004000  /* 0=write-back, 1=write-through */
4021+
4022+
4023+ #ifdef __cplusplus
4024+ }
4025+ #endif
4026+
4027+ #endif /* _RTEMS_SCORE_BFIN_H */
4028diff -crBN -X exclude rtems_orig/cpukit/score/cpu/bfin/rtems/score/cpu.h rtems/cpukit/score/cpu/bfin/rtems/score/cpu.h
4029*** rtems_orig/cpukit/score/cpu/bfin/rtems/score/cpu.h  2011-04-19 11:04:26.000000000 -0400
4030--- rtems/cpukit/score/cpu/bfin/rtems/score/cpu.h       2011-02-22 17:19:20.000000000 -0500
4031***************
4032*** 625,631 ****
4033   *
4034   *  XXX document implementation including references if appropriate
4035   */
4036! #define CPU_STACK_MINIMUM_SIZE          (1024*4)
4037 
4038  /**
4039   *  CPU's worst alignment requirement for data types on a byte boundary.  This
4040--- 625,631 ----
4041   *
4042   *  XXX document implementation including references if appropriate
4043   */
4044! #define CPU_STACK_MINIMUM_SIZE          (1024*8)
4045 
4046  /**
4047   *  CPU's worst alignment requirement for data types on a byte boundary.  This
4048***************
4049*** 693,699 ****
4050   *
4051   *  XXX document implementation including references if appropriate
4052   */
4053! #define CPU_STACK_ALIGNMENT        0
4054 
4055  /*
4056   *  ISR handler macros
4057--- 693,699 ----
4058   *
4059   *  XXX document implementation including references if appropriate
4060   */
4061! #define CPU_STACK_ALIGNMENT        8
4062 
4063  /*
4064   *  ISR handler macros