Ticket #1781: patch

File patch, 125.1 KB (added by Rohan, on 04/18/11 at 20:23:56)

Patch file for adding support for BF527 and TLL6527M

Line 
1diff -crBN -X exclude rtems-4.10.0/c/src/lib/libbsp/bfin/bf537Stamp/console/console.c rtems/c/src/lib/libbsp/bfin/bf537Stamp/console/console.c
2*** rtems-4.10.0/c/src/lib/libbsp/bfin/bf537Stamp/console/console.c     2009-12-10 23:10:27.000000000 -0500
3--- rtems/c/src/lib/libbsp/bfin/bf537Stamp/console/console.c    2011-03-15 16:59:39.000000000 -0400
4***************
5*** 7,13 ****
6   *  found in the file LICENSE in this distribution or at
7   *  http://www.rtems.com/license/LICENSE.
8   *
9!  *  $Id: console.c,v 1.5 2009/12/11 04:10:27 ralf Exp $
10   */
11 
12 
13--- 7,13 ----
14   *  found in the file LICENSE in this distribution or at
15   *  http://www.rtems.com/license/LICENSE.
16   *
17!  *  $Id: console.c 36 2011-03-15 20:59:39Z rkangral $
18   */
19 
20 
21***************
22*** 26,41 ****
23  */
24 
25  static bfin_uart_channel_t channels[] = {
26!   {"/dev/console",
27!    (char *) UART0_BASE_ADDRESS,
28!    CONSOLE_USE_INTERRUPTS,
29! #ifdef CONSOLE_FORCE_BAUD
30!    CONSOLE_FORCE_BAUD,
31! #else
32!    0,
33! #endif
34!    NULL,
35!    0}
36 
37  #if (!BFIN_ON_SKYEYE)
38  ,
39--- 26,46 ----
40  */
41 
42  static bfin_uart_channel_t channels[] = {
43!     {"/dev/console",
44!      UART0_BASE_ADDRESS,
45!      0,
46!      0,
47!      CONSOLE_USE_INTERRUPTS,
48!      0,
49!   #ifdef CONSOLE_FORCE_BAUD
50!      CONSOLE_FORCE_BAUD,
51!   #else
52!      0,
53!   #endif
54!      NULL,
55!      0,
56!      0}
57!   };
58 
59  #if (!BFIN_ON_SKYEYE)
60  ,
61***************
62*** 56,65 ****
63 
64  #if CONSOLE_USE_INTERRUPTS
65  static bfin_isr_t bfinUARTISRs[] = {
66!   {SIC_DMA8_UART0_RX_VECTOR, bfin_uart_isr, 0, 0, NULL},
67!   {SIC_DMA10_UART1_RX_VECTOR, bfin_uart_isr, 0, 0, NULL},
68!   {SIC_DMA9_UART0_TX_VECTOR, bfin_uart_isr, 0, 0, NULL},
69!   {SIC_DMA11_UART1_TX_VECTOR, bfin_uart_isr, 0, 0, NULL}
70  };
71  #endif
72 
73--- 61,70 ----
74 
75  #if CONSOLE_USE_INTERRUPTS
76  static bfin_isr_t bfinUARTISRs[] = {
77!   {SIC_DMA8_UART0_RX_VECTOR, bfinUart_rxIsr, 0, 0, NULL},
78!   {SIC_DMA10_UART1_RX_VECTOR, bfinUart_rxIsr, 0, 0, NULL},
79!   {SIC_DMA9_UART0_TX_VECTOR, bfinUart_txIsr, 0, 0, NULL},
80!   {SIC_DMA11_UART1_TX_VECTOR, bfinUart_txIsr, 0, 0, NULL}
81  };
82  #endif
83 
84diff -crBN -X exclude rtems-4.10.0/c/src/lib/libbsp/bfin/eZKit533/console/console-io.c rtems/c/src/lib/libbsp/bfin/eZKit533/console/console-io.c
85*** rtems-4.10.0/c/src/lib/libbsp/bfin/eZKit533/console/console-io.c    2009-12-10 23:09:43.000000000 -0500
86--- rtems/c/src/lib/libbsp/bfin/eZKit533/console/console-io.c   2011-03-15 16:59:39.000000000 -0400
87***************
88*** 11,17 ****
89   *  found in the file LICENSE in this distribution or at
90   *  http://www.rtems.com/license/LICENSE.
91   *
92!  *  $Id: console-io.c,v 1.5 2009/12/11 04:09:43 ralf Exp $
93   */
94 
95 
96--- 11,17 ----
97   *  found in the file LICENSE in this distribution or at
98   *  http://www.rtems.com/license/LICENSE.
99   *
100!  *  $Id: console-io.c 36 2011-03-15 20:59:39Z rkangral $
101   */
102 
103 
104***************
105*** 26,39 ****
106 
107  static bfin_uart_channel_t channels[] = {
108    {"/dev/console",
109!    (char *) UART0_BASE_ADDRESS,
110     CONSOLE_USE_INTERRUPTS,
111  #ifdef CONSOLE_FORCE_BAUD
112     CONSOLE_FORCE_BAUD,
113  #else
114     0,
115  #endif
116     NULL,
117     0}
118  };
119 
120--- 26,43 ----
121 
122  static bfin_uart_channel_t channels[] = {
123    {"/dev/console",
124!    UART0_BASE_ADDRESS,
125!    0,
126!    0,
127     CONSOLE_USE_INTERRUPTS,
128+    0,
129  #ifdef CONSOLE_FORCE_BAUD
130     CONSOLE_FORCE_BAUD,
131  #else
132     0,
133  #endif
134     NULL,
135+    0,
136     0}
137  };
138 
139***************
140*** 45,52 ****
141 
142  #if CONSOLE_USE_INTERRUPTS
143  static bfin_isr_t bfinUARTISRs[] = {
144!   {SIC_DMA6_UART0_RX_VECTOR, bfin_uart_isr, 0, 0, NULL},
145!   {SIC_DMA7_UART0_TX_VECTOR, bfin_uart_isr, 0, 0, NULL},
146  };
147  #endif
148 
149--- 49,56 ----
150 
151  #if CONSOLE_USE_INTERRUPTS
152  static bfin_isr_t bfinUARTISRs[] = {
153!   {SIC_DMA6_UART0_RX_VECTOR, bfinUart_rxIsr, 0, 0, NULL},
154!   {SIC_DMA7_UART0_TX_VECTOR, bfinUart_txIsr, 0, 0, NULL},
155  };
156  #endif
157 
158diff -crBN -X exclude rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/bsp_specs rtems/c/src/lib/libbsp/bfin/TLL6527M/bsp_specs
159*** rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/bsp_specs       1969-12-31 19:00:00.000000000 -0500
160--- rtems/c/src/lib/libbsp/bfin/TLL6527M/bsp_specs      2011-02-25 15:53:20.000000000 -0500
161***************
162*** 0 ****
163--- 1,10 ----
164+ %rename endfile old_endfile
165+ %rename startfile old_startfile
166+ %rename link old_link
167+
168+ *startfile:
169+ %{!qrtems: %(old_startfile)} \
170+ %{!nostdlib: %{qrtems: start.o%s -e __start}}
171+
172+ *link:
173+ %{!qrtems: %(old_link)} %{qrtems: -dc -dp -N}
174diff -crBN -X exclude rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/configure.ac rtems/c/src/lib/libbsp/bfin/TLL6527M/configure.ac
175*** rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/configure.ac    1969-12-31 19:00:00.000000000 -0500
176--- rtems/c/src/lib/libbsp/bfin/TLL6527M/configure.ac   2011-03-15 16:59:39.000000000 -0400
177***************
178*** 0 ****
179--- 1,47 ----
180+ ## Process this file with autoconf to produce a configure script.
181+ ##
182+ ## $Id: configure.ac 36 2011-03-15 20:59:39Z rkangral $
183+
184+ AC_PREREQ(2.68)
185+ AC_INIT([rtems-c-src-lib-libbsp-bfin-TLL6527M],[_RTEMS_VERSION],[http://www.rtems.org/bugzilla])
186+ AC_CONFIG_SRCDIR([bsp_specs])
187+ RTEMS_TOP(../../../../../..)
188+
189+ RTEMS_CANONICAL_TARGET_CPU
190+ AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.11.1])
191+ RTEMS_BSP_CONFIGURE
192+
193+ RTEMS_PROG_CC_FOR_TARGET
194+ RTEMS_CANONICALIZE_TOOLS
195+ RTEMS_PROG_CCAS
196+
197+ ## bsp-specific options
198+ RTEMS_BSPOPTS_SET([CONSOLE_USE_INTERRUPTS],[*],[1])
199+ RTEMS_BSPOPTS_HELP([CONSOLE_USE_INTERRUPTS],
200+ [The console driver can operate in either polled or interrupt mode.])
201+
202+ RTEMS_BSPOPTS_SET([UART_USE_DMA],[*],[1])
203+ RTEMS_BSPOPTS_HELP([UART_USE_DMA],
204+ [The uart driver can operate in dma mode with interrupts.
205+ Set to 1 if DMA operation is required ])
206+
207+ RTEMS_BSPOPTS_SET([CONSOLE_BAUDRATE],[*],[9600])
208+ RTEMS_BSPOPTS_HELP([CONSOLE_BAUDRATE],
209+ [The baudrate of the console uart.])
210+
211+ RTEMS_BSPOPTS_SET([INTERRUPT_USE_TABLE],[*],[1])
212+ RTEMS_BSPOPTS_HELP([INTERRUPT_USE_TABLE],
213+ [Select if INTERRUPT use table or link list])
214+
215+
216+
217+ RTEMS_BSPOPTS_SET([BFIN_ON_SKYEYE],[*],[0])
218+ RTEMS_BSPOPTS_HELP([BFIN_ON_SKYEYE],
219+ [(BSP--Skyeye)
220+  If defined, disable features which are not supported on Skyeye.])
221+
222+ RTEMS_BSP_CLEANUP_OPTIONS(0, 0)
223+
224+ # Explicitly list all Makefiles here
225+ AC_CONFIG_FILES([Makefile])
226+ AC_OUTPUT
227diff -crBN -X exclude rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/console/console.c rtems/c/src/lib/libbsp/bfin/TLL6527M/console/console.c
228*** rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/console/console.c       1969-12-31 19:00:00.000000000 -0500
229--- rtems/c/src/lib/libbsp/bfin/TLL6527M/console/console.c      2011-04-12 18:05:09.000000000 -0400
230***************
231*** 0 ****
232--- 1,176 ----
233+ /**
234+  *@file console.c
235+  *
236+  *@brief
237+  *  - This file implements uart console for TLL6527M. TLL6527M has BF527 with
238+  *  second uart (uart-1) connected to the console.
239+  *
240+  * Target:   TLL6527v1-0
241+  * Compiler:
242+  *
243+  * @author Rohan Kangralkar, ECE, Northeastern University
244+  *         (kangralkar.r@husky.neu.edu)
245+  *
246+  * LastChange:
247+  * $Id: console.c 46 2011-04-12 22:05:09Z rkangral $
248+  *
249+  */
250+
251+ #include <rtems.h>
252+ #include <rtems/libio.h>
253+ #include <bsp.h>
254+ #include <rtems/bspIo.h>
255+
256+ #include <bsp/interrupt.h>
257+ #include <libcpu/uart.h>
258+
259+ /***************************************************
260+ LOCAL DEFINES
261+  ***************************************************/
262+
263+
264+ /***************************************************
265+ STATIC GLOBALS
266+  ***************************************************/
267+ /**
268+  * Declaration of UART
269+  */
270+ static bfin_uart_channel_t channels[] = {
271+   {"/dev/console",
272+     UART1_BASE_ADDRESS,
273+     DMA10_BASE_ADDRESS,
274+     DMA11_BASE_ADDRESS,
275+     CONSOLE_USE_INTERRUPTS,
276+     UART_USE_DMA,
277+     CONSOLE_BAUDRATE,
278+     NULL,
279+     0,
280+     0}
281+ };
282+
283+ /**
284+  * Over all configuration
285+  */
286+ static bfin_uart_config_t config = {
287+     SCLK,
288+     sizeof(channels) / sizeof(channels[0]),
289+     channels
290+ };
291+
292+
293+ #if CONSOLE_USE_INTERRUPTS
294+ /**
295+  * The Rx and Tx isr will get the same argument
296+  * The isr will have to find if it was the rx that caused the interrupt or
297+  * the tx
298+  */
299+ static bfin_isr_t bfinUARTISRs[] = {
300+ #if UART_USE_DMA
301+     /* For First uart */
302+     {IRQ_DMA10_UART1_RX, bfinUart_rxDmaIsr, (void *)&channels[0], 0},
303+     {IRQ_DMA11_UART1_TX, bfinUart_txDmaIsr, (void *)&channels[0], 0},
304+     /* For second uart */
305+ #else
306+     /* For First uart */
307+     {IRQ_DMA10_UART1_RX, bfinUart_rxIsr, &channels[0], 0},
308+     {IRQ_DMA11_UART1_TX, bfinUart_txIsr, &channels[0], 0},
309+     /* For second uart */
310+ #endif
311+ };
312+ #endif
313+
314+
315+ static void TLL6527_BSP_output_char(char c) {
316+
317+   bfin_uart_poll_write(0, c);
318+ }
319+
320+ static int TLL6527_BSP_poll_char(void) {
321+
322+   return bfin_uart_poll_read(0);
323+ }
324+
325+ BSP_output_char_function_type     BSP_output_char = TLL6527_BSP_output_char;
326+ BSP_polling_getchar_function_type BSP_poll_char   = TLL6527_BSP_poll_char;
327+
328+
329+
330+ rtems_device_driver console_close(rtems_device_major_number major,
331+     rtems_device_minor_number minor,
332+     void *arg) {
333+
334+   return rtems_termios_close(arg);
335+ }
336+
337+ rtems_device_driver console_read(rtems_device_major_number major,
338+     rtems_device_minor_number minor,
339+     void *arg) {
340+
341+   return rtems_termios_read(arg);
342+ }
343+
344+ rtems_device_driver console_write(rtems_device_major_number major,
345+     rtems_device_minor_number minor,
346+     void *arg) {
347+
348+   return rtems_termios_write(arg);
349+ }
350+
351+ rtems_device_driver console_control(rtems_device_major_number major,
352+     rtems_device_minor_number minor,
353+     void *arg) {
354+
355+   return rtems_termios_ioctl(arg);
356+ }
357+
358+
359+
360+ /*
361+  *  Open entry point
362+  */
363+ rtems_device_driver console_open(rtems_device_major_number major,
364+     rtems_device_minor_number minor,
365+     void *arg) {
366+
367+   return bfin_uart_open(major, minor, arg);
368+ }
369+
370+
371+
372+ /**
373+  *
374+  * This routine initializes the console IO driver.
375+  *
376+  * Parameters
377+  * @param major major number
378+  * @param minor minor number
379+  *
380+  * Output parameters:  NONE
381+  *
382+  * @return void
383+  */
384+ rtems_device_driver console_initialize(rtems_device_major_number major,
385+     rtems_device_minor_number minor,
386+     void *arg) {
387+   rtems_status_code status = RTEMS_NOT_DEFINED;
388+ #if CONSOLE_USE_INTERRUPTS
389+   int               i      = 0;
390+ #endif
391+
392+   status = bfin_uart_initialize(major, &config);
393+   if (status != RTEMS_SUCCESSFUL) {
394+     rtems_fatal_error_occurred(status);
395+   }
396+
397+ #if CONSOLE_USE_INTERRUPTS
398+   for (i = 0; i < sizeof(bfinUARTISRs) / sizeof(bfinUARTISRs[0]); i++) {
399+     bfin_interrupt_register(&bfinUARTISRs[i]);
400+ #if INTERRUPT_USE_TABLE
401+ #else
402+     bfin_interrupt_enable(&bfinUARTISRs[i], 1);
403+ #endif
404+   }
405+ #endif
406+
407+   return RTEMS_SUCCESSFUL;
408+ }
409diff -crBN -X exclude rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/include/bsp.h rtems/c/src/lib/libbsp/bfin/TLL6527M/include/bsp.h
410*** rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/include/bsp.h   1969-12-31 19:00:00.000000000 -0500
411--- rtems/c/src/lib/libbsp/bfin/TLL6527M/include/bsp.h  2011-04-12 18:05:09.000000000 -0400
412***************
413*** 0 ****
414--- 1,77 ----
415+ /**
416+  *@file bsp.h
417+  * 
418+  *  This include file contains all board IO definitions for TLL6527M.
419+  *
420+  *  The license and distribution terms for this file may be
421+  *  found in the file LICENSE in this distribution or at
422+  *  http://www.rtems.com/license/LICENSE.
423+  *
424+  *  $Id: bsp.h 46 2011-04-12 22:05:09Z rkangral $
425+  */
426+ 
427+
428+ #ifndef _BSP_H
429+ #define _BSP_H
430+
431+
432+ #ifdef __cplusplus
433+ extern "C" {
434+ #endif
435+
436+ #include <bspopts.h>
437+
438+ #include <rtems.h>
439+ #include <rtems/console.h>
440+ #include <rtems/clockdrv.h>
441+ #include <rtems/score/bfin.h>
442+ #include <rtems/bfin/bf52x.h>
443+ #include <bf52x.h>
444+
445+
446+ /*
447+  * PLL and clock setup values:
448+  */
449+
450+ /*
451+  *  PLL configuration for TLL6527M
452+  *
453+  *  XTL   =  27 MHz
454+  *  CLKIN =  13 MHz
455+  *  VCO   = 391 MHz
456+  *  CCLK  = 391 MHz
457+  *  SCLK  = 130 MHz
458+  */
459+
460+ #define PLL_CSEL    0x0000      /* CCLK = VCO      */
461+ #define PLL_SSEL    0x0003      /* SCLK = CCLK/3   */
462+ #define PLL_MSEL    0x3A00      /* VCO = 29xCLKIN  */
463+ #define PLL_DF      0x0001      /* CLKIN = XTL/2   */
464+
465+ #define CLKIN             (25000000)  /* Input clock to the PLL */
466+ #define CCLK        (600000000)   /* CORE CLOCK     */
467+ #define SCLK        (100000000)   /* SYSTEM CLOCK   */
468+
469+ /*
470+  * UART setup values
471+  */
472+ #define BAUDRATE    57600       /* Console Baudrate   */
473+ #define WORD_5BITS  0x00        /* 5 bits word        */
474+ #define WORD_6BITS  0x01        /* 6 bits word        */
475+ #define WORD_7BITS  0x02        /* 7 bits word        */
476+ #define WORD_8BITS  0x03        /* 8 bits word        */
477+ #define EVEN_PARITY 0x18        /* Enable EVEN parity */
478+ #define ODD_PARITY  0x08        /* Enable ODD parity  */
479+ #define TWO_STP_BIT 0x04        /* 2 stop bits        */
480+
481+ rtems_isr_entry set_vector(                     /* returns old vector */
482+   rtems_isr_entry     handler,                  /* isr routine        */
483+   rtems_vector_number vector,                   /* vector number      */
484+   int                 type                      /* RTEMS or RAW intr  */
485+ );
486+
487+ #ifdef __cplusplus
488+ }
489+ #endif
490+
491+ #endif
492diff -crBN -X exclude rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/include/cplb.h rtems/c/src/lib/libbsp/bfin/TLL6527M/include/cplb.h
493*** rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/include/cplb.h  1969-12-31 19:00:00.000000000 -0500
494--- rtems/c/src/lib/libbsp/bfin/TLL6527M/include/cplb.h 2011-02-25 15:46:42.000000000 -0500
495***************
496*** 0 ****
497--- 1,34 ----
498+ /*  cplb.h
499+  * 
500+  *  Copyright (c) 2006 by Atos Automacao Industrial Ltda.
501+  *             written by Alain Schaefer <alain.schaefer@easc.ch>
502+  *
503+  *  The license and distribution terms for this file may be
504+  *  found in the file LICENSE in this distribution or at
505+  *  http://www.rtems.com/license/LICENSE.
506+  *
507+  *  $Id: cplb.h 27 2011-02-25 20:46:42Z rkangral $
508+  */
509+ #ifndef _CPLB_H
510+ #define _CPLB_H
511+
512+ /* CPLB configurations */
513+ #define CPLB_DEF_CACHE_WT     CPLB_L1_CHBL | CPLB_WT
514+ #define CPLB_DEF_CACHE_WB     CPLB_L1_CHBL
515+ #define CPLB_CACHE_ENABLED    CPLB_L1_CHBL | CPLB_DIRTY
516+
517+ #define CPLB_DEF_CACHE                CPLB_L1_CHBL | CPLB_WT
518+ #define CPLB_ALL_ACCESS       CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
519+
520+ #define CPLB_I_PAGE_MGMT      CPLB_LOCK | CPLB_VALID
521+ #define CPLB_D_PAGE_MGMT      CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
522+
523+ #define CPLB_DNOCACHE         CPLB_ALL_ACCESS | CPLB_VALID
524+ #define CPLB_DDOCACHE         CPLB_DNOCACHE | CPLB_DEF_CACHE
525+ #define CPLB_INOCACHE         CPLB_USER_RD | CPLB_VALID
526+ #define CPLB_IDOCACHE         CPLB_INOCACHE | CPLB_L1_CHBL
527+
528+ #define CPLB_DDOCACHE_WT      CPLB_DNOCACHE | CPLB_DEF_CACHE_WT
529+ #define CPLB_DDOCACHE_WB      CPLB_DNOCACHE | CPLB_DEF_CACHE_WB
530+
531+ #endif /* _CPLB_H */
532diff -crBN -X exclude rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/include/tm27.h rtems/c/src/lib/libbsp/bfin/TLL6527M/include/tm27.h
533*** rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/include/tm27.h  1969-12-31 19:00:00.000000000 -0500
534--- rtems/c/src/lib/libbsp/bfin/TLL6527M/include/tm27.h 2011-02-25 15:46:42.000000000 -0500
535***************
536*** 0 ****
537--- 1,35 ----
538+ /*
539+  *  tm27.h
540+  *
541+  *  The license and distribution terms for this file may be
542+  *  found in the file LICENSE in this distribution or at
543+  *  http://www.rtems.com/license/LICENSE.
544+  *
545+  *  $Id: tm27.h 27 2011-02-25 20:46:42Z rkangral $
546+  */
547+
548+ #ifndef _RTEMS_TMTEST27
549+ #error "This is an RTEMS internal file you must not include directly."
550+ #endif
551+
552+ #ifndef __tm27_h
553+ #define __tm27_h
554+
555+ /*
556+  *  Define the interrupt mechanism for Time Test 27
557+  */
558+
559+ #define MUST_WAIT_FOR_INTERRUPT 0
560+
561+ #define Install_tm27_vector(handler) \
562+ { \
563+   set_vector( handler, 0x06, 1 ); \
564+ }
565+
566+ #define Cause_tm27_intr() asm volatile("raise 0x06;" : :);
567+
568+ #define Clear_tm27_intr() /* empty */
569+
570+ #define Lower_tm27_intr() /* empty */
571+
572+ #endif
573diff -crBN -X exclude rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/make/custom/TLL6527M.cfg rtems/c/src/lib/libbsp/bfin/TLL6527M/make/custom/TLL6527M.cfg
574*** rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/make/custom/TLL6527M.cfg        1969-12-31 19:00:00.000000000 -0500
575--- rtems/c/src/lib/libbsp/bfin/TLL6527M/make/custom/TLL6527M.cfg       2011-02-25 15:55:50.000000000 -0500
576***************
577*** 0 ****
578--- 1,19 ----
579+ #
580+ #  Config file for Blackfin TLL6527M
581+ #
582+ #  $Id: TLL6527M.cfg 29 2011-02-25 20:55:50Z rkangral $
583+ #
584+
585+ include $(RTEMS_ROOT)/make/custom/default.cfg
586+
587+ RTEMS_CPU=bfin
588+ RTEMS_CPU_MODEL=bf52x
589+
590+ #  This contains the compiler options necessary to select the CPU model
591+ #  and (hopefully) optimize for it.
592+ #
593+ CPU_CFLAGS =-mcpu=bf527
594+
595+ # optimize flag: typically -O2
596+ # gcc-4.2.0 segfaults on -OX > -O0
597+ CFLAGS_OPTIMIZE_V = -O2 -g
598diff -crBN -X exclude rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/Makefile.am rtems/c/src/lib/libbsp/bfin/TLL6527M/Makefile.am
599*** rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/Makefile.am     1969-12-31 19:00:00.000000000 -0500
600--- rtems/c/src/lib/libbsp/bfin/TLL6527M/Makefile.am    2011-02-25 15:46:42.000000000 -0500
601***************
602*** 0 ****
603--- 1,60 ----
604+ ##
605+ ## $Id: Makefile.am 27 2011-02-25 20:46:42Z rkangral $
606+ ##
607+
608+ ACLOCAL_AMFLAGS = -I ../../../../aclocal
609+
610+ include $(top_srcdir)/../../../../automake/compile.am
611+
612+ include_bspdir = $(includedir)/bsp
613+
614+ dist_project_lib_DATA = bsp_specs
615+
616+ include_HEADERS = include/bsp.h
617+ include_HEADERS += include/tm27.h
618+ include_HEADERS += include/cplb.h
619+
620+ nodist_include_HEADERS = include/bspopts.h
621+ nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
622+ DISTCLEANFILES = include/bspopts.h
623+
624+ noinst_PROGRAMS =
625+
626+ include_HEADERS += ../../shared/include/coverhd.h
627+
628+ noinst_LIBRARIES = libbspstart.a
629+ libbspstart_a_SOURCES = ../shared/start/start.S
630+ project_lib_DATA = start.$(OBJEXT)
631+
632+ dist_project_lib_DATA += startup/linkcmds
633+
634+ noinst_LIBRARIES += libbsp.a
635+ libbsp_a_SOURCES =
636+
637+ noinst_PROGRAMS += startup.rel
638+ startup_rel_SOURCES = ../../shared/bsplibc.c ../../shared/bsppost.c \
639+       ../../shared/bsppredriverhook.c startup/bspstart.c \
640+       ../../shared/bspclean.c ../../shared/sbrk.c ../../shared/setvec.c \
641+       ../../shared/bootcard.c ../../shared/gnatinstallhandler.c \
642+       ../../shared/bspgetworkarea.c
643+ startup_rel_CPPFLAGS = $(AM_CPPFLAGS)
644+ startup_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
645+
646+ noinst_PROGRAMS += console.rel
647+ console_rel_SOURCES = console/console.c
648+ console_rel_CPPFLAGS = $(AM_CPPFLAGS)
649+ console_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
650+
651+ libbsp_a_LIBADD = startup.rel console.rel
652+ libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/mmu.rel
653+ libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/interrupt.rel
654+ libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/cache.rel
655+ libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/uart.rel
656+ libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/clock.rel
657+ libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/rtc.rel
658+ libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/timer.rel
659+
660+ EXTRA_DIST = times
661+
662+ include $(srcdir)/preinstall.am
663+ include $(top_srcdir)/../../../../automake/local.am
664diff -crBN -X exclude rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/preinstall.am rtems/c/src/lib/libbsp/bfin/TLL6527M/preinstall.am
665*** rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/preinstall.am   1969-12-31 19:00:00.000000000 -0500
666--- rtems/c/src/lib/libbsp/bfin/TLL6527M/preinstall.am  2011-02-25 15:53:20.000000000 -0500
667***************
668*** 0 ****
669--- 1,71 ----
670+ ## Automatically generated by ampolish3 - Do not edit
671+
672+ if AMPOLISH3
673+ $(srcdir)/preinstall.am: Makefile.am
674+       $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
675+ endif
676+
677+ PREINSTALL_DIRS =
678+ DISTCLEANFILES += $(PREINSTALL_DIRS)
679+
680+ all-local: $(TMPINSTALL_FILES)
681+
682+ TMPINSTALL_FILES =
683+ CLEANFILES = $(TMPINSTALL_FILES)
684+
685+ all-am: $(PREINSTALL_FILES)
686+
687+ PREINSTALL_FILES =
688+ CLEANFILES += $(PREINSTALL_FILES)
689+
690+ $(PROJECT_LIB)/$(dirstamp):
691+       @$(MKDIR_P) $(PROJECT_LIB)
692+       @: > $(PROJECT_LIB)/$(dirstamp)
693+ PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp)
694+
695+ $(PROJECT_INCLUDE)/$(dirstamp):
696+       @$(MKDIR_P) $(PROJECT_INCLUDE)
697+       @: > $(PROJECT_INCLUDE)/$(dirstamp)
698+ PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
699+
700+ $(PROJECT_INCLUDE)/bsp/$(dirstamp):
701+       @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp
702+       @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp)
703+ PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp)
704+
705+ $(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp)
706+       $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs
707+ PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs
708+
709+ $(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp)
710+       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h
711+ PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h
712+
713+ $(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
714+       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
715+ PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
716+
717+ $(PROJECT_INCLUDE)/cplb.h: include/cplb.h $(PROJECT_INCLUDE)/$(dirstamp)
718+       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/cplb.h
719+ PREINSTALL_FILES += $(PROJECT_INCLUDE)/cplb.h
720+
721+ $(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
722+       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
723+ PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h
724+
725+ $(PROJECT_INCLUDE)/bsp/bootcard.h: ../../shared/include/bootcard.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
726+       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bootcard.h
727+ PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bootcard.h
728+
729+ $(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp)
730+       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h
731+ PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h
732+
733+ $(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
734+       $(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT)
735+ TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT)
736+
737+ $(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp)
738+       $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds
739+ PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds
740+
741diff -crBN -X exclude rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/README rtems/c/src/lib/libbsp/bfin/TLL6527M/README
742*** rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/README  1969-12-31 19:00:00.000000000 -0500
743--- rtems/c/src/lib/libbsp/bfin/TLL6527M/README 2011-03-15 16:59:39.000000000 -0400
744***************
745*** 0 ****
746--- 1,96 ----
747+ #
748+ #  $Id: README 36 2011-03-15 20:59:39Z rkangral $
749+ #
750+
751+ BSP NAME:           TLL6527M
752+ BOARD:              TLL6527M
753+ CPU FAMILY:         Blackfin
754+ CPU:                Blackfin 527
755+ MODE:               32 bit mode
756+
757+ DEBUG MONITOR:     
758+ SIMULATOR:         
759+
760+ PERIPHERALS
761+ ===========
762+ TIMERS:             internal
763+   RESOLUTION:         1 milisecond
764+ SERIAL PORTS:       2 internal UART (polled/interrupt/dma)
765+ REAL-TIME CLOCK:    internal
766+ DMA:                internal
767+ VIDEO:              none
768+ SCSI:               none
769+ NETWORKING:         none
770+
771+
772+ DRIVER INFORMATION
773+ ==================
774+ CLOCK DRIVER:       internal
775+ TIMER DRIVER:       internal
776+ I2C:
777+ SPI:
778+ PPI:
779+ SPORT:
780+
781+
782+ STDIO
783+ =====
784+ PORT:               Console port 1
785+ ELECTRICAL:         RS-232
786+ BAUD:               9600
787+ BITS PER CHARACTER: 8
788+ PARITY:             None
789+ STOP BITS:          1
790+
791+ NOTES
792+ =====
793+ The TLL56527M board contains analog devices blackfin 527 processor. In addition
794+ to the peripherals provided by bf527 the board has a temprature sensor,
795+ accelerometer and power module connected via I2C. It also has LCD interface,
796+ Card reader interface.
797+
798+ The analog device bf52X family of processors are different from the bf53x range
799+ of processors. This port supports the additional features that are not
800+ supported by the blackfin 53X family of processors.
801+   
802+ The TLL6527M does not use the interrupt module used by the bfin 53x since it has
803+ an additional system interrupt controller isr registers for additional lines.
804+ On the 53X these line are multiplexed.
805+ The centralized interrupt handler is implemented to use lookup tables for
806+ jumping to the user ISR. For more details look at files implemented under
807+ libcpu/bfin/bf52x/interrupt/*
808+
809+ This port supports only the uart peripheral. The uart is supported via
810+ polling, DMA, interrupt. The uart file is generic and is common between the
811+ ports. Under bsp configure.ac files
812+ * change the CONSOLE_BAUDRATE or to choose among different baudrate.
813+ * Set UART_USE_DMA for UART to use DMA based transfers. In DMA based transfer
814+   chunk of buffer is transmitted at once and then an interrupt is generated.
815+ * Set CONSOLE_USE_INTERRUPTS to use interrupt based transfers. After every
816+   character is transmitted an interrupt is generated.
817+ * If CONSOLE_USE_INTERRUPTS, UART_USE_DMA are both not set then the port uses
818+   polling to transmit data over uart. This call is blocking.
819+
820+ TLL6527 specific file are mentioned below.
821+ =====================================
822+ c/src/lib/libcpu/bfin/bf52x/*
823+ c/src/lib/libbsp/bfin/TLL6527M/*
824+
825+
826+ The port was compiled using
827+ ===========================
828+ 1. bfin-rtems4.11-gcc (GCC) 4.5.2 20101216
829+               (RTEMS gcc-4.5.2-3.el5/newlib-1.19.0-1.el5)
830+ 2. automake (GNU automake) 1.11.1
831+ 3. autoconf (GNU Autoconf) 2.68
832+
833+
834+ The port was configured using the flags
835+ ==========================================
836+ --target=bfin-rtems4.11 --enable-rtemsbsp=TLL6527M --enable-tests=samples
837+ --disable-posix --disable-itron
838+       
839+
840+ ISSUES:
841+ Could not place code in l1code (SRAM) because it was not being loaded by the
842+ gnu loaded.
843\ No newline at end of file
844diff -crBN -X exclude rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/startup/bspstart.c rtems/c/src/lib/libbsp/bfin/TLL6527M/startup/bspstart.c
845*** rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/startup/bspstart.c      1969-12-31 19:00:00.000000000 -0500
846--- rtems/c/src/lib/libbsp/bfin/TLL6527M/startup/bspstart.c     2011-04-12 18:05:09.000000000 -0400
847***************
848*** 0 ****
849--- 1,207 ----
850+ /*  bspstart.c for TLL6527M
851+  *
852+  *  This routine starts the application.  It includes application,
853+  *  board, and monitor specific initialization and configuration.
854+  *  The generic CPU dependent initialization has been performed
855+  *  before this routine is invoked.
856+  * 
857+
858+  *
859+  *  The license and distribution terms for this file may be
860+  *  found in the file LICENSE in this distribution or at
861+  *  http://www.rtems.com/license/LICENSE.
862+  *
863+  *  $Id: bspstart.c 46 2011-04-12 22:05:09Z rkangral $
864+  */
865+
866+
867+ #include <bsp.h>
868+ #include <cplb.h>
869+ #include <bsp/interrupt.h>
870+ #include <libcpu/ebiuRegs.h>
871+
872+ const unsigned int dcplbs_table[16][2] = { 
873+   { 0xFFA00000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },
874+   { 0xFF900000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) }, /* L1 Data B */
875+   { 0xFF800000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) }, /* L1 Data A */
876+   { 0xFFB00000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },
877+
878+   { 0x20300000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },/* Async Memory Bank 3 */
879+   { 0x20200000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },/* Async Memory Bank 2  */
880+   { 0x20100000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },/* Async Memory Bank 1 */
881+   { 0x20000000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) }, /* Async Memory Bank 0 */
882+
883+   { 0x02400000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
884+   { 0x02000000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
885+   { 0x00C00000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
886+   { 0x00800000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
887+   { 0x00400000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
888+   { 0x00000000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
889+
890+   { 0xffffffff, 0xffffffff }/* end of section - termination */
891+ };
892+
893+
894+ const unsigned int _icplbs_table[16][2] = {
895+   { 0xFFA00000, (PAGE_SIZE_1MB | CPLB_I_PAGE_MGMT | CPLB_I_PAGE_MGMT | 0x4) },
896+   /* L1 Code */
897+   { 0xEF000000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, /* AREA DE BOOT */
898+   { 0xFFB00000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },
899+
900+   { 0x20300000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Memory Bank 3 */
901+   { 0x20200000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Memory Bank 2 (Secnd) */
902+   { 0x20100000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Memory Bank 1 (Prim B) */
903+   { 0x20000000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },/* Async Memory Bank 0 (Prim A) */
904+
905+   { 0x02400000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
906+   { 0x02000000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
907+   { 0x00C00000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
908+   { 0x00800000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
909+   { 0x00400000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
910+   { 0x00000000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
911+
912+   { 0xffffffff, 0xffffffff }/* end of section - termination */
913+ };
914+
915+ /*
916+  *  Use the shared implementations of the following routines
917+  */
918+
919+ void bsp_libc_init( void *, uint32_t, int );
920+ void Init_PLL (void);
921+ void Init_EBIU (void);
922+ void Init_Flags(void);
923+ void Init_RTC (void);
924+ void initCPLB(void);
925+
926+
927+ void null_isr(void);
928+
929+ /*
930+  *  Function:   bsp_pretasking_hook
931+  *  Created:    95/03/10
932+  *
933+  *  Description:
934+  *      BSP pretasking hook.  Called just before drivers are initialized.
935+  *      Used to setup libc and install any BSP extensions.
936+  *
937+  *  NOTES:
938+  *      Must not use libc (to do io) from here, since drivers are
939+  *      not yet initialized.
940+  *
941+  */
942+
943+ void bsp_pretasking_hook(void)
944+ {
945+   bfin_interrupt_init();
946+ }
947+
948+ /*
949+  *  bsp_start
950+  *
951+  *  This routine does the bulk of the system initialization.
952+  */
953+
954+ void bsp_start( void )
955+ {
956+   /* BSP Hardware Initialization*/
957+   Init_RTC();   /* Blackfin Real Time Clock initialization */ 
958+   Init_PLL();   /* PLL initialization */
959+   Init_EBIU();  /* EBIU initialization */
960+   Init_Flags(); /* GPIO initialization */
961+
962+   /*
963+    *  Allocate the memory for the RTEMS Work Space.  This can come from
964+    *  a variety of places: hard coded address, malloc'ed from outside
965+    *  RTEMS world (e.g. simulator or primitive memory manager), or (as
966+    *  typically done by stock BSPs) by subtracting the required amount
967+    *  of work space from the last physical address on the CPU board.
968+    */
969+   int i=0;
970+   for (i=5;i<16;i++) {
971+     set_vector((rtems_isr_entry)null_isr, i, 1);
972+   }
973+   
974+ }
975+
976+  /*
977+   * Init_PLL
978+   *
979+   * Routine to initialize the PLL. The TLL6527M uses a 25 Mhz XTAL.
980+   */
981+ void Init_PLL (void)
982+ {
983+   unsigned short msel = 0;
984+   unsigned short ssel = 0;
985+
986+   msel = (unsigned short)( (float)CCLK/(float)CLKIN );
987+   ssel = (unsigned short)( (float)(CLKIN*msel)/(float)SCLK);
988+   
989+   asm("cli r0;");
990+
991+   *((uint32_t*)SIC_IWR) = 0x1;
992+
993+   /* Configure PLL registers */
994+   *((uint16_t*)PLL_DIV) = ssel;;
995+   msel = msel<<9;
996+   *((uint16_t*)PLL_CTL) = msel;
997+
998+   /* Commands to set PLL values */
999+   asm("idle;");
1000+   asm("sti r0;");
1001+ }
1002+
1003+  /*
1004+   * Init_EBIU
1005+   *
1006+   * Configure extern memory
1007+   */
1008+
1009+ void Init_EBIU (void)
1010+ {
1011+   /* Check if SDRAM is already enabled */
1012+   if ( 0 != (*(uint16_t *)EBIU_SDSTAT & EBIU_SDSTAT_SDRS) ){
1013+     asm("ssync;");
1014+     /* RDIV = (100MHz*64ms)/8192-(6+3)=0x406 cycles */
1015+     *(uint16_t *)EBIU_SDRRC  = 0x3F6; /* SHould have been 0x306*/
1016+     *(uint16_t *)EBIU_SDBCTL = EBIU_SDBCTL_EBCAW_10 | EBIU_SDBCTL_EBSZ_64M |
1017+         EBIU_SDBCTL_EBE;
1018+     *(uint32_t *)EBIU_SDGCTL = 0x8491998d;
1019+     asm("ssync;");
1020+   } else {
1021+     /* SDRAm is already programmed */
1022+   }
1023+ }
1024+
1025+  /*
1026+   * Init_Flags
1027+   *
1028+   * Enable LEDs port
1029+   */
1030+ void Init_Flags(void)
1031+ {
1032+   *((uint16_t*)PORTH_FER)    = 0x0;
1033+   *((uint16_t*)PORTH_MUX)    = 0x0;
1034+   *((uint16_t*)PORTHIO_DIR)  = 0x1<<15;
1035+   *((uint16_t*)PORTHIO_SET)  = 0x1<<15;
1036+ }
1037+
1038+
1039+
1040+ void initCPLB(void) {
1041+
1042+        int i = 0;
1043+        unsigned int *addr;
1044+        unsigned int *data;
1045+         
1046+        addr = (unsigned int *)0xffe00100;
1047+        data = (unsigned int *)0xffe00200;
1048+
1049+        while ( dcplbs_table[i][0] != 0xffffffff ) {
1050+                *addr = dcplbs_table[i][0];
1051+                *data = dcplbs_table[i][1];
1052+
1053+                addr++;
1054+                data++;
1055+        }
1056+ }
1057diff -crBN -X exclude rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/startup/linkcmds rtems/c/src/lib/libbsp/bfin/TLL6527M/startup/linkcmds
1058*** rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/startup/linkcmds        1969-12-31 19:00:00.000000000 -0500
1059--- rtems/c/src/lib/libbsp/bfin/TLL6527M/startup/linkcmds       2011-04-12 18:05:09.000000000 -0400
1060***************
1061*** 0 ****
1062--- 1,154 ----
1063+ OUTPUT_FORMAT("elf32-bfin", "elf32-bfin",
1064+             "elf32-bfin")
1065+
1066+ OUTPUT_ARCH(bfin)
1067+ ENTRY(__start)
1068+
1069+ /*
1070+  * Declare some sizes.
1071+  */
1072+ _RamBase    = DEFINED(_RamBase)   ? _RamBase : 0x0;
1073+ _RamSize    = DEFINED(_RamSize)   ? _RamSize : 0x04000000;
1074+ _HeapSize   = DEFINED(_HeapSize)  ? _HeapSize : 0x10000;
1075+ _StackSize  = DEFINED(_StackSize) ? _StackSize : 0x10000;
1076+
1077+ MEMORY
1078+ {
1079+       sdram(rwx)      : ORIGIN = 0x00000100, LENGTH = 0x04000000
1080+       
1081+       l1dataA(rwx)    : ORIGIN = 0xff800000, LENGTH = 0x00004000
1082+       l1dataAC(rwx)   : ORIGIN = 0xff804000, LENGTH = 0x00004000
1083+       l1dataB(rwx)    : ORIGIN = 0xff900000, LENGTH = 0x00004000
1084+       l1dataBC(rwx)   : ORIGIN = 0xff904000, LENGTH = 0x00004000
1085+       
1086+       l1code(rwx)     : ORIGIN = 0xffa00000, LENGTH = 0x0000C000
1087+       l1codeC(rwx)    : ORIGIN = 0xffa10000, LENGTH = 0x00004000
1088+       scratchpad(rwx) : ORIGIN = 0xffb00000, LENGTH = 0x00001000
1089+ }
1090+
1091+ SECTIONS
1092+ {
1093+
1094+     .init          :
1095+     {
1096+       *(.l1code)
1097+         KEEP (*(.init))
1098+     } > sdram   /*=0*/
1099+
1100+     .text :
1101+     {
1102+          CREATE_OBJECT_SYMBOLS
1103+         *(.text)
1104+         *(.rodata*)
1105+         *(.gnu.linkonce.r*)
1106+         
1107+         /*
1108+          * Special FreeBSD sysctl sections.
1109+          */
1110+         . = ALIGN (16);
1111+         ___start_set_sysctl_set = .;
1112+         *(set_sysctl_*);
1113+         ___stop_set_sysctl_set = ABSOLUTE(.);
1114+         *(set_domain_*);
1115+         *(set_pseudo_*);
1116+
1117+          _etext = .;
1118+
1119+         ___CTOR_LIST__ = .;
1120+         LONG((___CTOR_END__ - ___CTOR_LIST__) / 4 - 2)
1121+         *(.ctors)
1122+         LONG(0)
1123+         ___CTOR_END__ = .;
1124+         ___DTOR_LIST__ = .;
1125+         LONG((___DTOR_END__ - ___DTOR_LIST__) / 4 - 2)
1126+         *(.dtors)
1127+         LONG(0)
1128+         ___DTOR_END__ = .;         
1129+     } > sdram
1130+     
1131+     .fini :
1132+     {
1133+         KEEP (*(.fini))
1134+     } > sdram  /*=0*/
1135+     
1136+     .data :
1137+     {
1138+         *(.data)
1139+         *(.jcr)
1140+         *(.gnu.linkonce.d*)
1141+         CONSTRUCTORS
1142+          _edata = .;
1143+     } > sdram
1144+
1145+     .eh_frame : { *(.eh_frame) } > sdram
1146+     .data1   : { *(.data1) } > sdram
1147+     .eh_frame : { *(.eh_frame) } > sdram
1148+     .gcc_except_table : { *(.gcc_except_table*) } > sdram
1149+
1150+     .rodata :
1151+     {
1152+         *(.rodata)
1153+         *(.rodata.*)
1154+         *(.gnu.linkonce.r*)
1155+     } > sdram
1156+
1157+     
1158+     .bss :
1159+     {
1160+          _bss_start = .;
1161+         _clear_start = .;
1162+         *(.bss)
1163+         *(.gnu.linkonce.b.*)
1164+         *(COMMON)
1165+         . = ALIGN (64);
1166+         _stack_init = .;
1167+         . += _StackSize;
1168+         _clear_end = .;
1169+         _WorkAreaBase = .;
1170+          _end = .;
1171+          __end = .;
1172+     } > sdram
1173+     
1174+ /* Debugging stuff follows */
1175+
1176+   /* Stabs debugging sections.  */
1177+   .stab 0 : { *(.stab) }
1178+   .stabstr 0 : { *(.stabstr) }
1179+   .stab.excl 0 : { *(.stab.excl) }
1180+   .stab.exclstr 0 : { *(.stab.exclstr) }
1181+   .stab.index 0 : { *(.stab.index) }
1182+   .stab.indexstr 0 : { *(.stab.indexstr) }
1183+   .comment 0 : { *(.comment) }
1184+   /* DWARF debug sections.
1185+      Symbols in the DWARF debugging sections are relative to the beginning
1186+      of the section so we begin them at 0.  */
1187+   /* DWARF 1 */
1188+   .debug          0 : { *(.debug) }
1189+   .line           0 : { *(.line) }
1190+   /* GNU DWARF 1 extensions */
1191+   .debug_srcinfo  0 : { *(.debug_srcinfo) }
1192+   .debug_sfnames  0 : { *(.debug_sfnames) }
1193+   /* DWARF 1.1 and DWARF 2 */
1194+   .debug_aranges  0 : { *(.debug_aranges) }
1195+   .debug_pubnames 0 : { *(.debug_pubnames) }
1196+   /* DWARF 2 */
1197+   .debug_info     0 : { *(.debug_info) }
1198+   .debug_abbrev   0 : { *(.debug_abbrev) }
1199+   .debug_line     0 : { *(.debug_line) }
1200+   .debug_frame    0 : { *(.debug_frame) }
1201+   .debug_str      0 : { *(.debug_str) }
1202+   .debug_loc      0 : { *(.debug_loc) }
1203+   .debug_macinfo  0 : { *(.debug_macinfo) }
1204+   /* SGI/MIPS DWARF 2 extensions */
1205+   .debug_weaknames 0 : { *(.debug_weaknames) }
1206+   .debug_funcnames 0 : { *(.debug_funcnames) }
1207+   .debug_typenames 0 : { *(.debug_typenames) }
1208+   .debug_varnames  0 : { *(.debug_varnames) }
1209+   /*.stack 0x80000 : { _stack = .; *(.stack) }*/
1210+   /* These must appear regardless of  .  */   
1211+ }
1212+
1213+ __HeapSize = _HeapSize;
1214+ __edata = _edata;
1215+ __etext = _etext;
1216+
1217diff -crBN -X exclude rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/times rtems/c/src/lib/libbsp/bfin/TLL6527M/times
1218*** rtems-4.10.0/c/src/lib/libbsp/bfin/TLL6527M/times   1969-12-31 19:00:00.000000000 -0500
1219--- rtems/c/src/lib/libbsp/bfin/TLL6527M/times  2011-04-12 18:05:09.000000000 -0400
1220***************
1221*** 0 ****
1222--- 1,179 ----
1223+ #
1224+ #  Timing Test Suite Results for TLL6527M
1225+ #
1226+ #
1227+ #  $Id: times 46 2011-04-12 22:05:09Z rkangral $
1228+ #
1229+
1230+ Board: TLL6527M
1231+ CPU: Blackfin 527
1232+ Clock Speed: 600 MHz
1233+ Memory Configuration: SDRAM 100 MHz
1234+
1235+
1236+ *** TIME TEST 1 ***
1237+ rtems_semaphore_create 8
1238+ rtems_semaphore_delete 4
1239+ rtems_semaphore_obtain: available 0
1240+ rtems_semaphore_obtain: not available -- NO_WAIT 0
1241+ rtems_semaphore_release: no waiting tasks 1
1242+ *** END OF TEST 1 ***
1243+
1244+
1245+ *** TIME TEST 2 ***
1246+ rtems_semaphore_obtain: not available -- caller blocks 8
1247+ *** END OF TEST 2 ***
1248+
1249+
1250+ *** TIME TEST 3 ***
1251+
1252+ *** TIME TEST 4 ***
1253+
1254+ *** TIME TEST 5 ***
1255+
1256+ *** TIME TEST 6 ***
1257+ rtems_task_restart: calling task 3
1258+ rtems_task_suspend: returns to caller 1
1259+ rtems_task_resume: task readied -- returns to caller 1
1260+ rtems_task_delete: ready task 15
1261+ *** END OF TEST 6 ***
1262+
1263+ *** TIME TEST 7 ***
1264+
1265+
1266+ *** TIME TEST 8 ***
1267+ rtems_task_set_priority: obtain current priorityrtems_task_mode: reschedule -- preempts caller 0   
1268+ rtems_task_set_priority: returns to caller  2
1269+ rtems_task_mode: obtain current mode101 0
1270+ rtems_task_mode: no reschedule 0
1271+ rtems_task_mode: reschedule -- returns to caller
1272+  2
1273+ rtems_task_set_note 1
1274+ rtems_task_get_note 0
1275+ rtems_clock_set 2
1276+ rtems_clock_get_tod 12
1277+ *** END OF TEST 8 ***
1278+
1279+
1280+ *** TIME TEST 9 ***
1281+ rtems_message_queue_create 43
1282+ rtems_message_queue_send: no waiting tasks 2
1283+ rtems_message_queue_urgent: no waiting tasks 2
1284+ rtems_message_queue_receive: available 2
1285+ rtems_message_queue_flush: no messages flushed 0
1286+ rtems_message_queue_flush: messages flushed 1
1287+ rtems_message_queue_delete 8
1288+ *** END OF TEST 9 ***
1289+
1290+ *** TIME TEST 10 ***
1291+ rtems_message_queue_receive: not available -- NO_WAITrtems_message_queue_receive: not available -- caller blocks 1
1292+  8
1293+ *** END OF TEST 10 ***
1294+
1295+ *** TIME TEST 11 ***
1296+
1297+ *** TIME TEST 12 ***
1298+
1299+ *** TIME TEST 13 ***
1300+
1301+ *** TIME TEST 14 ***
1302+
1303+ *** TIME TEST 15 ***
1304+ rtems_event_receive: obtain current eventsrtems_event_receive: not available -- caller blocks  07 
1305+
1306+ rtems_event_receive: not available -- NO_WAITrtems_event_send: n
1307+
1308+
1309+
1310+ *** TIME TEST 16 ***
1311+
1312+ *** TIME TEST 17 ***
1313+     
1314+     
1315+ *** TIME TEST 18 ***
1316+ rtems_task_delete: calling task 22
1317+ *** END OF TEST 18 ***
1318+
1319+
1320+ *** TIME TEST 19 ***
1321+ rtems_signal_catch 1
1322+ rtems_signal_send: returns to caller 2
1323+ rtems_signal_send: signal to self 8
1324+ exi
1325+
1326+
1327+
1328+ *** TIME TEST 20 ***                                                                               
1329+ rtems_partition_create 12                                                                         
1330+ rtems_region_creatertems_region_get_segment: not available -- caller blocks 15
1331+ rtems_partition_get_buffer: available 3
1332+ rtems_partition_get_buffer: not available15 1
1333+ rtems_partition_return_buffer 2
1334+
1335+ rtems_partition_delete 2
1336+ rtems_region_get_segment: available 5rtems_region_return_segment: task readied -- returns to caller
1337+  rtems_region_get_segment: not available -- NO_WAIT 5
1338+ rtems_region_return_segment: no waiting tasks3 4
1339+
1340+ Ack! Something bad happened to the Blackfin!
1341+
1342+ SEQUENCER STATUS:
1343+  SEQSTAT: 0000c021  IPEND: 8068  SYSCFG: 0006
1344+   HWERRCAUSE: 0x3: external memory addressing error
1345+   EXCAUSE   : 0x21: undef inst
1346+   physical IVG6 asserted : <0x00009542> /* unknown address */
1347+   physical IVG15 asserted : <0x00009690> /* unknown address */
1348+  RETE: <0x00000100> /* unknown address */
1349+  RETN: <0x92a330ab> { ___smulsi3_highpart + 0x8ead486f }
1350+  RETX: <0x12001940> { ___smulsi3_highpart + 0xe0a3104 }
1351+  RETS: <0x000095fa> /* unknown address */
1352+  RETI: <0x0d48338c> { ___smulsi3_highpart + 0x9524b50 }
1353+ DCPLB_FAULT_ADDR: <0x000318f0> /* unknown address */
1354+ ICPLB_FAULT_ADDR: <0x12001940> { ___smulsi3_highpart + 0xe0a3104 }
1355+ 
1356+ 
1357+
1358+ *** TIME TEST 21 ***                                                                               
1359+
1360+ rtems_region_create FAILED -- expected (successful completion) got (address specified is invalid)
1361+
1362+ *** TIME TEST 22 ***
1363+
1364+ *** TIME TEST 23 ***
1365+
1366+
1367+ *** TIME TEST 24 ***
1368+     
1369+     
1370+ *** TIME TEST 25 ***
1371+ rtems_clock_tick 5
1372+ *** END OF TEST 25 ***
1373+
1374+
1375+ *** TIME TEST 26 ***
1376+
1377+ *** TIME TEST 27 ***
1378+ interrupt entry overhead: returns to interrupted taskinterrupt entry overhead: returns to preempting task  22
1379+
1380+ interrupt exit overhead: returns to interrupted task
1381+
1382+
1383+ *** TIME TEST 28 ***
1384+ rtems_port_create 1
1385+ rtems_port_external_to_internal 0
1386+ rtems_port_internal_to_external 0
1387+ rtems_port_delete 1
1388+ *** END OF TEST 28 ***
1389+
1390+
1391+ *** TIME TEST 29 ***
1392+ rtems_rate_monotonic_create 6
1393+ rtems_rate_monotonic_period: initiate period -- returns to caller 10
1394+ rtems_rate_monotonic_period: obtain status 2
1395+ rtems_rate_monotonic_cancel 3
1396+ rtems_rate_monotonic_delete: inactive 6
1397+ rtems_rate_monotonic_delete: active 3
1398+ rtems_rate_monotonic_period: conclude periods -- caller blocks 9
1399+ *** END OF TEST 29 ***
1400+
1401+         
1402\ No newline at end of file
1403diff -crBN -X exclude rtems-4.10.0/c/src/lib/libcpu/bfin/bf52x/include/bf52x.h rtems/c/src/lib/libcpu/bfin/bf52x/include/bf52x.h
1404*** rtems-4.10.0/c/src/lib/libcpu/bfin/bf52x/include/bf52x.h    1969-12-31 19:00:00.000000000 -0500
1405--- rtems/c/src/lib/libcpu/bfin/bf52x/include/bf52x.h   2011-04-12 18:05:42.000000000 -0400
1406***************
1407*** 0 ****
1408--- 1,127 ----
1409+ /**
1410+  *@file bf52x.h
1411+  *
1412+  *@brief
1413+  *  - This file provides the register address for the 52X model. The file is
1414+  *  based on the 533 implementation with some addition to support 52X range of
1415+  *  processors.
1416+  *
1417+  * Target:   TLL6527v1-0
1418+  * Compiler:
1419+  *
1420+  * @author Rohan Kangralkar, ECE, Northeastern University
1421+  *         (kangralkar.r@husky.neu.edu)
1422+  *
1423+  * LastChange:
1424+  * $Id: bf52x.h 47 2011-04-12 22:05:42Z rkangral $
1425+  *
1426+  */
1427+
1428+ #ifndef _BF52X_H_
1429+ #define _BF52X_H_
1430+
1431+ /* register (or register block) addresses */
1432+
1433+ #define SIC_BASE_ADDRESS                          0xffc00100
1434+ #define WDOG_BASE_ADDRESS                         0xffc00200
1435+ #define RTC_BASE_ADDRESS                          0xffc00300
1436+ #define UART0_BASE_ADDRESS                        0xffc00400
1437+ #define UART1_BASE_ADDRESS                        0xffc02000
1438+ #define SPI_BASE_ADDRESS                          0xffc00500
1439+ #define TIMER_BASE_ADDRESS                        0xffc00600
1440+ #define TIMER_CHANNELS                                     3
1441+ #define TIMER_PITCH                                     0x10
1442+ #define TIMER0_BASE_ADDRESS                       0xffc00600
1443+ #define TIMER1_BASE_ADDRESS                       0xffc00610
1444+ #define TIMER2_BASE_ADDRESS                       0xffc00620
1445+ #define TIMER_ENABLE                              0xffc00640
1446+ #define TIMER_DISABLE                             0xffc00644
1447+ #define TIMER_STATUS                              0xffc00648
1448+ #define PORTFIO_BASE_ADDRESS                      0xffc00700
1449+ #define SPORT0_BASE_ADDRESS                       0xffc00800
1450+ #define SPORT1_BASE_ADDRESS                       0xffc00900
1451+ #define EBIU_BASE_ADDRESS                         0xffc00a00
1452+ #define DMA_TC_PER                                0xffc00b0c
1453+ #define DMA_TC_CNT                                0xffc00b10
1454+ #define DMA_BASE_ADDRESS                          0xffc00c00
1455+ #define DMA_CHANNELS                                       8
1456+ #define DMA_PITCH                                       0x40
1457+ #define DMA0_BASE_ADDRESS                         0xffc00c00
1458+ #define DMA1_BASE_ADDRESS                         0xffc00c40
1459+ #define DMA2_BASE_ADDRESS                         0xffc00c80
1460+ #define DMA3_BASE_ADDRESS                         0xffc00cc0
1461+ #define DMA4_BASE_ADDRESS                         0xffc00d00
1462+ #define DMA5_BASE_ADDRESS                         0xffc00d40
1463+ #define DMA6_BASE_ADDRESS                         0xffc00d80
1464+ #define DMA7_BASE_ADDRESS                         0xffc00dc0
1465+ #define DMA8_BASE_ADDRESS                         0xffc00e00
1466+ #define DMA9_BASE_ADDRESS                         0xffc00e40
1467+ #define DMA10_BASE_ADDRESS                        0xffc00e80
1468+ #define DMA11_BASE_ADDRESS                        0xffc00ec0
1469+ #define MDMA_BASE_ADDRESS                         0xffc00e00
1470+ #define MDMA_CHANNELS                                      2
1471+ #define MDMA_D_S                                        0x40
1472+ #define MDMA_PITCH                                      0x80
1473+ #define MDMA0D_BASE_ADDRESS                       0xffc00e00
1474+ #define MDMA0S_BASE_ADDRESS                       0xffc00e40
1475+ #define MDMA1D_BASE_ADDRESS                       0xffc00e80
1476+ #define MDMA1S_BASE_ADDRESS                       0xffc00ec0
1477+ #define PPI_BASE_ADDRESS                          0xffc01000
1478+
1479+
1480+ /* register fields */
1481+
1482+ #define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_MASK       0xf800
1483+ #define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_SHIFT          11
1484+ #define DMA_TC_PER_DAB_TRAFFIC_PERIOD_MASK            0x0700
1485+ #define DMA_TC_PER_DAB_TRAFFIC_PERIOD_SHIFT                8
1486+ #define DMA_TC_PER_DEB_TRAFFIC_PERIOD_MASK            0x00f0
1487+ #define DMA_TC_PER_DEB_TRAFFIC_PERIOD_SHIFT                4
1488+ #define DMA_TC_PER_DCB_TRAFFIC_PERIOD_MASK            0x000f
1489+ #define DMA_TC_PER_DCB_TRAFFIC_PERIOD_SHIFT                0
1490+
1491+ #define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_MASK        0xf800
1492+ #define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_SHIFT           11
1493+ #define DMA_TC_CNT_DAB_TRAFFIC_COUNT_MASK             0x0700
1494+ #define DMA_TC_CNT_DAB_TRAFFIC_COUNT_SHIFT                 8
1495+ #define DMA_TC_CNT_DEB_TRAFFIC_COUNT_MASK             0x00f0
1496+ #define DMA_TC_CNT_DEB_TRAFFIC_COUNT_SHIFT                 4
1497+ #define DMA_TC_CNT_DCB_TRAFFIC_COUNT_MASK             0x000f
1498+ #define DMA_TC_CNT_DCB_TRAFFIC_COUNT_SHIFT                 0
1499+
1500+ #define TIMER_ENABLE_TIMEN2                           0x0004
1501+ #define TIMER_ENABLE_TIMEN1                           0x0002
1502+ #define TIMER_ENABLE_TIMEN0                           0x0001
1503+
1504+ #define TIMER_DISABLE_TIMDIS2                         0x0004
1505+ #define TIMER_DISABLE_TIMDIS1                         0x0002
1506+ #define TIMER_DISABLE_TIMDIS0                         0x0001
1507+
1508+ #define TIMER_STATUS_TRUN2                        0x00004000
1509+ #define TIMER_STATUS_TRUN1                        0x00002000
1510+ #define TIMER_STATUS_TRUN0                        0x00001000
1511+ #define TIMER_STATUS_TOVF_ERR2                    0x00000040
1512+ #define TIMER_STATUS_TOVF_ERR1                    0x00000020
1513+ #define TIMER_STATUS_TOVF_ERR0                    0x00000010
1514+ #define TIMER_STATUS_TIMIL2                       0x00000004
1515+ #define TIMER_STATUS_TIMIL1                       0x00000002
1516+ #define TIMER_STATUS_TIMIL0                       0x00000001
1517+
1518+ /* Core Event Controller vectors */
1519+
1520+ #define CEC_EMULATION_VECTOR                               0
1521+ #define CEC_RESET_VECTOR                                   1
1522+ #define CEC_NMI_VECTOR                                     2
1523+ #define CEC_EXCEPTIONS_VECTOR                              3
1524+ #define CEC_HARDWARE_ERROR_VECTOR                          5
1525+ #define CEC_CORE_TIMER_VECTOR                              6
1526+ #define CEC_INTERRUPT_BASE_VECTOR                          7
1527+ #define CEC_INTERRUPT_COUNT                                9
1528+
1529+
1530+ /* System Interrupt Controller vectors */
1531+
1532+ #define SIC_IAR_COUNT                                      8
1533+
1534+ #endif /* _BF52X_H_ */
1535+
1536diff -crBN -X exclude rtems-4.10.0/c/src/lib/libcpu/bfin/bf52x/interrupt/interrupt.c rtems/c/src/lib/libcpu/bfin/bf52x/interrupt/interrupt.c
1537*** rtems-4.10.0/c/src/lib/libcpu/bfin/bf52x/interrupt/interrupt.c      1969-12-31 19:00:00.000000000 -0500
1538--- rtems/c/src/lib/libcpu/bfin/bf52x/interrupt/interrupt.c     2011-04-12 18:05:42.000000000 -0400
1539***************
1540*** 0 ****
1541--- 1,632 ----
1542+ /**
1543+  *@file interrupt.c
1544+  *
1545+  *@brief
1546+  *  - This file implements interrupt dispatcher. Most of the code is taken from
1547+  *  the 533 implementation for blackfin. Since 52X supports 56 line and 2 ISR
1548+  *  registers some portion is written twice.
1549+  *
1550+  * Target:   TLL6527v1-0
1551+  * Compiler:
1552+  *
1553+  * @author Rohan Kangralkar, ECE, Northeastern University
1554+  *         (kangralkar.r@husky.neu.edu)
1555+  *
1556+  * LastChange:
1557+  * $Id: interrupt.c 47 2011-04-12 22:05:42Z rkangral $
1558+  *
1559+  */
1560+
1561+ #include <rtems.h>
1562+ #include <rtems/libio.h>
1563+
1564+ #include <bsp.h>
1565+ #include <libcpu/cecRegs.h>
1566+ #include <libcpu/sicRegs.h>
1567+ #include "interrupt.h"
1568+
1569+ #define SIC_IAR_COUNT_SET0              4
1570+ #define SIC_IAR_BASE_ADDRESS_0  0xFFC00150
1571+
1572+ /**
1573+  * There are two implementations for the interrupt handler.
1574+  * 1. INTERRUPT_USE_TABLE: uses tables for finding the right ISR.
1575+  * 2. Uses link list to find the user ISR.
1576+  *
1577+  *
1578+  * 1. INTERRUPT_USE_TABLE
1579+  * Space requirement:
1580+  *    * Array to hold CEC masks size: CEC_INTERRUPT_COUNT(9)*(2*int).9*2*4= 72B
1581+  *    * Array to hold isr function pointers IRQ_MAX(56)*sizeof(bfin_isr_t)= 896B
1582+  *    * Array for bit twidlling 32 bytes.
1583+  *    * Global Mask 8 bytes.
1584+  *    Total = 1008 Bytes Aprox
1585+  *
1586+  * Time requirements
1587+  *    The worst case time is about the same for jumping to the user ISR. With a
1588+  *    variance of one conditional statement.
1589+  *
1590+  * 2. Using link list.
1591+  * Space requirement:
1592+  *    * Array to hold CEC mask CEC_INTERRUPT_COUNT(9)*(sizeof(vectors)).
1593+  *                                                                  9*3*4= 108B
1594+  *    * Array to hold isr IRQ_MAX(56)*sizeof(bfin_isr_t) The structure has
1595+  *       additional pointers                                        56*7*4=1568B
1596+  *    * Global Mask 8 bytes.
1597+  *    Total = 1684.
1598+  * Time requirements
1599+  *    In the worst case all the lines can be on one CEC line to 56 entries have
1600+  *    to be traversed to find the right user ISR.
1601+  *    But this implementation has benefit of being flexible, Providing
1602+  *    additional user assigned priority. and may consume less space
1603+  *    if all devices are not supported.
1604+  */
1605+
1606+ /**
1607+  * TODO: To place code in L1.
1608+  */
1609+
1610+ #if INTERRUPT_USE_TABLE
1611+
1612+
1613+ /******************************************************************************
1614+  * Static variables
1615+  ******************************************************************************/
1616+ /**
1617+  * @var sic_isr0_mask
1618+  * @brief copy of the mask of SIC ISR. The SIC ISR is cleared by the device
1619+  * the relevant SIC_ISRx bit is not cleared unless the interrupt
1620+  * service routine clears the mechanism that generated interrupt
1621+  */
1622+ static uint32_t sic_isr0_mask = 0;
1623+
1624+ /**
1625+  * @var sic_isr0_mask
1626+  * @brief copy of the mask of SIC ISR. The SIC ISR is cleared by the device
1627+  * the relevant SIC_ISRx bit is not cleared unless the interrupt
1628+  * service routine clears the mechanism that generated interrupt
1629+  */
1630+ static uint32_t sic_isr1_mask = 0;
1631+
1632+
1633+ /**
1634+  * @var sic_isr
1635+  * @brief An array of sic register mask for each of the 16 core interrupt lines
1636+  */
1637+ static struct {
1638+   uint32_t mask0;
1639+   uint32_t mask1;
1640+ } vectors[CEC_INTERRUPT_COUNT];
1641+
1642+ /**
1643+  * @var ivt
1644+  * @brief Contains a table of ISR and arguments. The ISR jumps directly to these
1645+  * ISR.
1646+  */
1647+ static bfin_isr_t ivt[IRQ_MAX];
1648+
1649+ /**
1650+  * http://graphics.stanford.edu/~seander/bithacks.html for more details
1651+  */
1652+ static const char clz_table[32] =
1653+ {
1654+     0, 31, 9, 30, 3, 8, 18, 29, 2, 5, 7, 14, 12, 17,
1655+     22, 28, 1, 10, 4, 19, 6, 15, 13, 23, 11, 20, 16,
1656+     24, 21, 25, 26, 27
1657+ };
1658+
1659+ /**
1660+  * finds the first bit set from the left. look at
1661+  * http://graphics.stanford.edu/~seander/bithacks.html for more details
1662+  * @param n
1663+  * @return
1664+  */
1665+ static unsigned long clz(unsigned long n)
1666+ {
1667+   unsigned long c = 0x7dcd629;       /* magic constant... */
1668+
1669+   n |= (n >> 1);
1670+   n |= (n >> 2);
1671+   n |= (n >> 4);
1672+   n |= (n >> 8);
1673+   n |= (n >> 16);
1674+   if (n == 0) return 32;
1675+   n = c + (c * n);
1676+   return 31 - clz_table[n >> 27];       /* For little endian    */
1677+ }
1678+
1679+
1680+
1681+ /**
1682+  * Centralized Interrupt dispatcher routine. This routine dispatches interrupts
1683+  * to the user ISR. The priority is according to the blackfin SIC.
1684+  * The first level of priority is handled in the hardware at the core event
1685+  * controller. The second level of interrupt is handled according to the line
1686+  * number that goes in to the SIC.
1687+  * * SIC_0 has higher priority than SIC 1.
1688+  * * Inside the SIC the priority is assigned according to the line number.
1689+  *   Lower the line number higher the priority.
1690+  *
1691+  *   In order to change the interrupt priority we may
1692+  *   1. change the SIC IAR registers or
1693+  *   2. Assign priority and extract it inside this function and call the ISR
1694+  *   according tot the priority.
1695+  *
1696+  * @param vector IVG number.
1697+  * @return
1698+  */
1699+ static rtems_isr interruptHandler(rtems_vector_number vector) {
1700+   uint32_t mask = 0;
1701+   int id = 0;
1702+   static volatile uint32_t spurious_sic0    = 0;
1703+   static volatile uint32_t spurious_source  = 0;
1704+   static volatile uint32_t spurious_sic1    = 0;
1705+
1706+   /**
1707+    * Extract the vector number relative to the SIC start line
1708+    */
1709+   vector -= CEC_INTERRUPT_BASE_VECTOR;
1710+
1711+   /**
1712+    * Check for bounds
1713+    */
1714+   if (vector >= 0 && vector < CEC_INTERRUPT_COUNT) {
1715+
1716+     /**
1717+      * Extract information and execute ISR from SIC 0
1718+      */
1719+     mask = *(uint32_t volatile *) SIC_ISR &
1720+         *(uint32_t volatile *) SIC_IMASK & vectors[vector].mask0;
1721+     id      = clz(mask);
1722+     if ( SIC_ISR0_MAX > id ) {
1723+       /** Parameter check */
1724+       if( NULL != ivt[id].pFunc) {
1725+         /** Call the relevant function with argument */
1726+         ivt[id].pFunc( ivt[id].pArg );
1727+       } else {
1728+         /**
1729+          * spurious interrupt we should not be getting this
1730+          */
1731+         spurious_sic0++;
1732+         spurious_source = id;
1733+       }
1734+     } else {
1735+       /**
1736+        * we look at SIC 1
1737+        */
1738+     }
1739+
1740+
1741+     /**
1742+      * Extract information and execute ISR from SIC 1
1743+      */
1744+     mask    = *(uint32_t volatile *) (SIC_ISR + SIC_ISR_PITCH) &
1745+         *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH) &
1746+         vectors[vector].mask1;
1747+     id      = clz(mask)+SIC_ISR0_MAX;
1748+     if ( IRQ_MAX > id ) {
1749+       /** Parameter Check */
1750+       if( NULL != ivt[id].pFunc ) {
1751+         /** Call the relevant function with argument */
1752+         ivt[id].pFunc( ivt[id].pArg );
1753+       } else {
1754+         /**
1755+          * spurious interrupt we should not be getting this
1756+          */
1757+         spurious_sic1++;
1758+         spurious_source = id;
1759+       }
1760+     } else {
1761+       /**
1762+        * we continue
1763+        */
1764+     }
1765+
1766+   }
1767+ }
1768+
1769+
1770+
1771+ /**
1772+  * This function registers a new ISR. It will write a new entry to the IVT table
1773+  * @param isr contains a callback function and source
1774+  * @return rtems status code
1775+  */
1776+ rtems_status_code bfin_interrupt_register(bfin_isr_t *isr) {
1777+   rtems_interrupt_level isrLevel;
1778+   int               id        = 0;
1779+   int               position  = 0;
1780+
1781+   /**
1782+    * Sanity Check
1783+    */
1784+   if ( NULL == isr ){
1785+     return RTEMS_UNSATISFIED;
1786+   }
1787+
1788+   /**
1789+    * Sanity check. The register function should at least provide callback func
1790+    */
1791+   if ( NULL == isr->pFunc ) {
1792+     return RTEMS_UNSATISFIED;
1793+   }
1794+
1795+   id = isr->source;
1796+
1797+   /**
1798+    * Parameter Check. We already have a function registered here. First
1799+    * unregister and then a new function can be allocated.
1800+    */
1801+   if ( NULL != ivt[id].pFunc ) {
1802+     return RTEMS_UNSATISFIED;
1803+   }
1804+
1805+   rtems_interrupt_disable(isrLevel);
1806+   /**
1807+    * Assign the new function pointer to the ISR Dispatcher
1808+    * */
1809+   ivt[id].pFunc    = isr->pFunc;
1810+   ivt[id].pArg     = isr->pArg;
1811+
1812+
1813+   /** find out which isr mask has to be set to enable the interrupt */
1814+   if ( SIC_ISR0_MAX > id ) {
1815+     sic_isr0_mask |= 0x1<<id;
1816+     *(uint32_t volatile *) SIC_IMASK  |= 0x1<<id;
1817+   } else {
1818+     position = id - SIC_ISR0_MAX;
1819+     sic_isr1_mask |= 0x1<<position;
1820+     *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH)  |= 0x1<<position;
1821+   }
1822+
1823+   rtems_interrupt_enable(isrLevel);
1824+
1825+   return RTEMS_SUCCESSFUL;
1826+ }
1827+
1828+
1829+ /**
1830+  * This function unregisters a registered interrupt handler.
1831+  * @param isr
1832+  */
1833+ rtems_status_code bfin_interrupt_unregister(bfin_isr_t *isr) {
1834+   rtems_interrupt_level isrLevel;
1835+   int               id        = 0;
1836+   int               position  = 0;
1837+
1838+   /**
1839+    * Sanity Check
1840+    */
1841+   if ( NULL == isr ){
1842+     return RTEMS_UNSATISFIED;
1843+   }
1844+
1845+   id = isr->source;
1846+
1847+   rtems_interrupt_disable(isrLevel);
1848+   /**
1849+    * Assign the new function pointer to the ISR Dispatcher
1850+    * */
1851+   ivt[id].pFunc    = NULL;
1852+   ivt[id].pArg     = NULL;
1853+
1854+
1855+   /** find out which isr mask has to be set to enable the interrupt */
1856+   if ( SIC_ISR0_MAX > id ) {
1857+     sic_isr0_mask &= ~(0x1<<id);
1858+     *(uint32_t volatile *) SIC_IMASK  &= ~(0x1<<id);
1859+   } else {
1860+     position = id - SIC_ISR0_MAX;
1861+     sic_isr1_mask &= ~(0x1<<position);
1862+     *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH)  &= ~(0x1<<position);
1863+   }
1864+
1865+   rtems_interrupt_enable(isrLevel);
1866+
1867+   return RTEMS_SUCCESSFUL;
1868+ }
1869+
1870+
1871+
1872+
1873+ /**
1874+  * blackfin interrupt initialization routine. It initializes the bfin ISR
1875+  * dispatcher. It will also create SIC CEC map which will be used for
1876+  * identifying the ISR.
1877+  */
1878+ void bfin_interrupt_init(void) {
1879+   int source;
1880+   int vector;
1881+   uint32_t r;
1882+   int i;
1883+   int j;
1884+
1885+   *(uint32_t volatile *) SIC_IMASK = 0;
1886+   *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH) = 0;
1887+
1888+   memset(vectors, 0, sizeof(vectors));
1889+   /* build mask0 showing what SIC sources drive each CEC vector */
1890+   source = 0;
1891+
1892+   /**
1893+    * The bf52x has 8 IAR registers but they do not have a constant pitch.
1894+    *
1895+    */
1896+   for (i = 0; i < SIC_IAR_COUNT; i++) {
1897+     if ( SIC_IAR_COUNT_SET0 > i ) {
1898+       r = *(uint32_t volatile *) (SIC_IAR_BASE_ADDRESS + i * SIC_IAR_PITCH);
1899+     } else {
1900+       r = *(uint32_t volatile *) (SIC_IAR_BASE_ADDRESS_0 +
1901+           ((i-SIC_IAR_COUNT_SET0) * SIC_IAR_PITCH));
1902+     }
1903+
1904+     for (j = 0; j < 8; j++) {
1905+       vector = r & 0x0f;
1906+       if (vector >= 0 && vector < CEC_INTERRUPT_COUNT) {
1907+         /* install our local handler */
1908+         if (vectors[vector].mask0 == 0 && vectors[vector].mask1 == 0){
1909+           set_vector(interruptHandler, vector + CEC_INTERRUPT_BASE_VECTOR, 1);
1910+         }
1911+         if ( SIC_ISR0_MAX > source ) {
1912+           vectors[vector].mask0 |= (1 << source);
1913+         } else {
1914+           vectors[vector].mask1 |= (1 << (source - SIC_ISR0_MAX));
1915+         }
1916+       }
1917+       r >>= 4;
1918+       source++;
1919+     }
1920+   }
1921+ }
1922+
1923+
1924+
1925+
1926+
1927+ #else
1928+
1929+ static struct {
1930+   uint32_t mask0;
1931+   uint32_t mask1;
1932+   bfin_isr_t *head;
1933+ } vectors[CEC_INTERRUPT_COUNT];
1934+
1935+ static uint32_t globalMask0;
1936+ static uint32_t globalMask1;
1937+
1938+ static rtems_isr interruptHandler(rtems_vector_number vector) {
1939+   bfin_isr_t *isr = NULL;
1940+   uint32_t sourceMask0 = 0;
1941+   uint32_t sourceMask1 = 0;
1942+   rtems_interrupt_level isrLevel;
1943+
1944+   rtems_interrupt_disable(isrLevel);
1945+   vector -= CEC_INTERRUPT_BASE_VECTOR;
1946+   if (vector >= 0 && vector < CEC_INTERRUPT_COUNT) {
1947+     isr = vectors[vector].head;
1948+     sourceMask0 = *(uint32_t volatile *) SIC_ISR &
1949+         *(uint32_t volatile *) SIC_IMASK;
1950+     sourceMask1 = *(uint32_t volatile *) (SIC_ISR + SIC_ISR_PITCH) &
1951+         *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH);
1952+     while (isr) {
1953+       if ((sourceMask0 & isr->mask0) || (sourceMask1 & isr->mask1)) {
1954+         isr->isr(isr->_arg);
1955+         sourceMask0 = *(uint32_t volatile *) SIC_ISR &
1956+             *(uint32_t volatile *) SIC_IMASK;
1957+         sourceMask1 = *(uint32_t volatile *) (SIC_ISR + SIC_ISR_PITCH) &
1958+             *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH);
1959+       }
1960+       isr = isr->next;
1961+     }
1962+   }
1963+   rtems_interrupt_enable(isrLevel);
1964+ }
1965+
1966+ /**
1967+  * Initializes the interrupt module
1968+  */
1969+ void bfin_interrupt_init(void) {
1970+   int source;
1971+   int vector;
1972+   uint32_t r;
1973+   int i;
1974+   int j;
1975+
1976+   globalMask0 = ~(uint32_t) 0;
1977+   globalMask1 = ~(uint32_t) 0;
1978+   *(uint32_t volatile *) SIC_IMASK = 0;
1979+   *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH) = 0;
1980+
1981+   memset(vectors, 0, sizeof(vectors));
1982+   /* build mask0 showing what SIC sources drive each CEC vector */
1983+   source = 0;
1984+
1985+   /**
1986+    * The bf52x has 8 IAR registers but they do not have a constant pitch.
1987+    *
1988+    */
1989+   for (i = 0; i < SIC_IAR_COUNT; i++) {
1990+     if ( SIC_IAR_COUNT_SET0 > i ) {
1991+       r = *(uint32_t volatile *) (SIC_IAR_BASE_ADDRESS + i * SIC_IAR_PITCH);
1992+     } else {
1993+       r = *(uint32_t volatile *) (SIC_IAR_BASE_ADDRESS_0 +
1994+           ((i-SIC_IAR_COUNT_SET0) * SIC_IAR_PITCH));
1995+     }
1996+     for (j = 0; j < 8; j++) {
1997+       vector = r & 0x0f;
1998+       if (vector >= 0 && vector < CEC_INTERRUPT_COUNT) {
1999+         /* install our local handler */
2000+         if (vectors[vector].mask0 == 0 && vectors[vector].mask1 == 0){
2001+           set_vector(interruptHandler, vector + CEC_INTERRUPT_BASE_VECTOR, 1);
2002+         }
2003+         if ( SIC_ISR0_MAX > source ) {
2004+           vectors[vector].mask0 |= (1 << source);
2005+         } else {
2006+           vectors[vector].mask1 |= (1 << (source - SIC_ISR0_MAX));
2007+         }
2008+       }
2009+       r >>= 4;
2010+       source++;
2011+     }
2012+   }
2013+ }
2014+
2015+ /* modify SIC_IMASK based on ISR list for a particular CEC vector */
2016+ static void setMask(uint32_t vector) {
2017+   bfin_isr_t *isr = NULL;
2018+   uint32_t mask = 0;
2019+   uint32_t r    = 0;
2020+
2021+   mask = 0;
2022+   isr = vectors[vector].head;
2023+   while (isr) {
2024+     mask |= isr->mask0;
2025+     isr = isr->next;
2026+   }
2027+   r = *(uint32_t volatile *) SIC_IMASK;
2028+   r &= ~vectors[vector].mask0;
2029+   r |= mask;
2030+   r &= globalMask0;
2031+   *(uint32_t volatile *) SIC_IMASK = r;
2032+
2033+
2034+   mask = 0;
2035+   isr = vectors[vector].head;
2036+   while (isr) {
2037+     mask |= isr->mask1;
2038+     isr = isr->next;
2039+   }
2040+   r = *(uint32_t volatile *) (SIC_IMASK+ SIC_IMASK_PITCH);
2041+   r &= ~vectors[vector].mask1;
2042+   r |= mask;
2043+   r &= globalMask1;
2044+   *(uint32_t volatile *) (SIC_IMASK+ SIC_IMASK_PITCH) = r;
2045+ }
2046+
2047+ /* add an ISR to the list for whichever vector it belongs to */
2048+ rtems_status_code bfin_interrupt_register(bfin_isr_t *isr) {
2049+   bfin_isr_t *walk;
2050+   rtems_interrupt_level isrLevel;
2051+
2052+   /* find the appropriate vector */
2053+   for (isr->vector = 0; isr->vector < CEC_INTERRUPT_COUNT; isr->vector++)
2054+     if ( (vectors[isr->vector].mask0 & (1 << isr->source) ) || \
2055+         (vectors[isr->vector].mask1 & (1 << (isr->source - SIC_ISR0_MAX)) ))
2056+       break;
2057+   if (isr->vector < CEC_INTERRUPT_COUNT) {
2058+     isr->next = NULL;
2059+     isr->mask0 = 0;
2060+     isr->mask1 = 0;
2061+     rtems_interrupt_disable(isrLevel);
2062+     /* find the current end of the list */
2063+     walk = vectors[isr->vector].head;
2064+     while (walk && walk->next)
2065+       walk = walk->next;
2066+     /* append new isr to list */
2067+     if (walk)
2068+       walk->next = isr;
2069+     else
2070+       vectors[isr->vector].head = isr;
2071+     rtems_interrupt_enable(isrLevel);
2072+   } else
2073+     /* we failed, but make vector a legal value so other calls into
2074+              this module with this isr descriptor won't do anything bad */
2075+     isr->vector = 0;
2076+   return RTEMS_SUCCESSFUL;
2077+ }
2078+
2079+ rtems_status_code bfin_interrupt_unregister(bfin_isr_t *isr) {
2080+   bfin_isr_t *walk, *prev;
2081+   rtems_interrupt_level isrLevel;
2082+
2083+   rtems_interrupt_disable(isrLevel);
2084+   walk = vectors[isr->vector].head;
2085+   prev = NULL;
2086+   /* find this isr in our list */
2087+   while (walk && walk != isr) {
2088+     prev = walk;
2089+     walk = walk->next;
2090+   }
2091+   if (walk) {
2092+     /* if found, remove it */
2093+     if (prev)
2094+       prev->next = walk->next;
2095+     else
2096+       vectors[isr->vector].head = walk->next;
2097+     /* fix up SIC_IMASK if necessary */
2098+     setMask(isr->vector);
2099+   }
2100+   rtems_interrupt_enable(isrLevel);
2101+   return RTEMS_SUCCESSFUL;
2102+ }
2103+
2104+ void bfin_interrupt_enable(bfin_isr_t *isr, bool enable) {
2105+   rtems_interrupt_level isrLevel;
2106+
2107+   rtems_interrupt_disable(isrLevel);
2108+   if ( SIC_ISR0_MAX > isr->source ) {
2109+     isr->mask0 = enable ? (1 << isr->source) : 0;
2110+     *(uint32_t volatile *) SIC_IMASK |= isr->mask0;
2111+   }  else {
2112+     isr->mask1 = enable ? (1 << (isr->source - SIC_ISR0_MAX)) : 0;
2113+     *(uint32_t volatile *) (SIC_IMASK + SIC_IMASK_PITCH) |= isr->mask1;
2114+   }
2115+
2116+   //setMask(isr->vector);
2117+   rtems_interrupt_enable(isrLevel);
2118+ }
2119+
2120+ void bfin_interrupt_enable_all(int source, bool enable) {
2121+   rtems_interrupt_level isrLevel;
2122+   int vector;
2123+   bfin_isr_t *walk;
2124+
2125+   for (vector = 0; vector < CEC_INTERRUPT_COUNT; vector++)
2126+     if ( (vectors[vector].mask0 & (1 << source) ) || \
2127+         (vectors[vector].mask1 & (1 << (source - SIC_ISR0_MAX)) ))
2128+       break;
2129+   if (vector < CEC_INTERRUPT_COUNT) {
2130+     rtems_interrupt_disable(isrLevel);
2131+     walk = vectors[vector].head;
2132+     while (walk) {
2133+       walk->mask0 = enable ? (1 << source) : 0;
2134+       walk = walk->next;
2135+     }
2136+
2137+     walk = vectors[vector].head;
2138+     while (walk) {
2139+       walk->mask1 = enable ? (1 << (source - SIC_ISR0_MAX)) : 0;
2140+       walk = walk->next;
2141+     }
2142+     setMask(vector);
2143+     rtems_interrupt_enable(isrLevel);
2144+   }
2145+ }
2146+
2147+ void bfin_interrupt_enable_global(int source, bool enable) {
2148+   int vector;
2149+   rtems_interrupt_level isrLevel;
2150+
2151+   for (vector = 0; vector < CEC_INTERRUPT_COUNT; vector++)
2152+     if ( (vectors[vector].mask0 & (1 << source) ) || \
2153+         (vectors[vector].mask1 & (1 << (source - SIC_ISR0_MAX)) ))
2154+       break;
2155+   if (vector < CEC_INTERRUPT_COUNT) {
2156+     rtems_interrupt_disable(isrLevel);
2157+     if ( SIC_ISR0_MAX > source ) {
2158+       if (enable)
2159+         globalMask0 |= 1 << source;
2160+       else
2161+         globalMask0 &= ~(1 << source);
2162+     }else {
2163+       if (enable)
2164+         globalMask1 |= 1 << (source - SIC_ISR0_MAX);
2165+       else
2166+         globalMask1 &= ~(1 << (source - SIC_ISR0_MAX));
2167+     }
2168+     setMask(vector);
2169+     rtems_interrupt_enable(isrLevel);
2170+   }
2171+ }
2172+
2173+ #endif
2174diff -crBN -X exclude rtems-4.10.0/c/src/lib/libcpu/bfin/bf52x/interrupt/interrupt.h rtems/c/src/lib/libcpu/bfin/bf52x/interrupt/interrupt.h
2175*** rtems-4.10.0/c/src/lib/libcpu/bfin/bf52x/interrupt/interrupt.h      1969-12-31 19:00:00.000000000 -0500
2176--- rtems/c/src/lib/libcpu/bfin/bf52x/interrupt/interrupt.h     2011-04-12 18:05:42.000000000 -0400
2177***************
2178*** 0 ****
2179--- 1,140 ----
2180+ /**
2181+  *@file interrupt.h
2182+  *
2183+  *@brief
2184+  *  - This file implements interrupt dispatcher. The init code is taken from
2185+  *  the 533 implementation for blackfin. Since 52X supports 56 line and 2 ISR
2186+  *  registers some portion is written twice.
2187+  *
2188+  * Target:   TLL6527v1-0
2189+  * Compiler:
2190+  *
2191+  * @author Rohan Kangralkar, ECE, Northeastern University
2192+  *         (kangralkar.r@husky.neu.edu)
2193+  *
2194+  * LastChange:
2195+  * $Id: interrupt.h 47 2011-04-12 22:05:42Z rkangral $
2196+  *
2197+  */
2198+
2199+ #ifndef _BFIN_INTERRUPT_H_
2200+ #define _BFIN_INTERRUPT_H_
2201+
2202+
2203+ #ifdef __cplusplus
2204+ extern "C" {
2205+ #endif
2206+
2207+ /** The type of interrupts handled by the SIC
2208+  */
2209+ typedef enum {
2210+     IRQ_PLL_WAKEUP_INTERRUPT,                 /* 0 */
2211+     IRQ_DMA_ERROR_0,                          /* 1 */
2212+     IRQ_DMAR0_BLOCK_INTERRUPT,                /* 2 */
2213+     IRQ_DMAR1_BLOCK_INTERRUPT,                /* 3 */
2214+     IRQ_DMAR0_OVERFLOW_ERROR,                 /* 4 */
2215+     IRQ_DMAR1_OVERFLOW_ERROR,                 /* 5 */
2216+     IRQ_PPI_STATUS,                           /* 6 */
2217+     IRQ_MAC_STATUS,                           /* 7 */
2218+     IRQ_SPORT0_STATUS,                        /* 8 */
2219+     IRQ_SPORT1_STATUS,                        /* 9 */
2220+     IRQ_RESERVED_10,                          /* 10 */
2221+     IRQ_RESERVED_11,                          /* 11 */
2222+     IRQ_UART0_STATUS,                         /* 12 */
2223+     IRQ_UART1_STATUS,                         /* 13 */
2224+     IRQ_REAL_TIME_CLOCK,                      /* 14 */
2225+     IRQ_DMA0_PPI_NFC,                         /* 15 */
2226+     IRQ_DMA3_SPORT0_RX,                       /* 16 */
2227+     IRQ_DMA4_SPORT0_TX,                       /* 17 */
2228+     IRQ_DMA5_SPORT1_RX,                       /* 18 */
2229+     IRQ_DMA6_SPORT1_TX,                       /* 19 */
2230+     IRQ_TWI_INTERRUPT,                        /* 20 */
2231+     IRQ_DMA7_SPI,                             /* 21 */
2232+     IRQ_DMA8_UART0_RX,                        /* 22 */
2233+     IRQ_DMA9_UART0_TX,                        /* 23 */
2234+     IRQ_DMA10_UART1_RX,                       /* 24 */
2235+     IRQ_DMA11_UART1_TX,                       /* 25 */
2236+     IRQ_OTP,                                  /* 26 */
2237+     IRQ_GP_COUNTER,                           /* 27 */
2238+     IRQ_DMA1_MAC_RX_HOSTDP,                   /* 28 */
2239+     IRQ_PORT_H_INTERRUPT_A,                   /* 29 */
2240+     IRQ_DMA2_MAC_TX_NFC,                      /* 30 */
2241+     IRQ_PORT_H_INTERRUPT_B,                   /* 31 */
2242+     SIC_ISR0_MAX,                             /* 32 ***/
2243+     IRQ_TIMER0 = SIC_ISR0_MAX,                /* 32 */
2244+     IRQ_TIMER1,                               /* 33 */
2245+     IRQ_TIMER2,                               /* 34 */
2246+     IRQ_TIMER3,                               /* 35 */
2247+     IRQ_TIMER4,                               /* 36 */
2248+     IRQ_TIMER5,                               /* 37 */
2249+     IRQ_TIMER6,                               /* 38 */
2250+     IRQ_TIMER7,                               /* 39 */
2251+     IRQ_PORT_G_INTERRUPT_A,                   /* 40 */
2252+     IRQ_PORT_G_INTERRUPT_B,                   /* 41 */
2253+     IRQ_MDMA0_STREAM_0_INTERRUPT,             /* 42 */
2254+     IRQ_MDMA1_STREAM_0_INTERRUPT,             /* 43 */
2255+     IRQ_SOFTWARE_WATCHDOG_INTERRUPT,          /* 44 */
2256+     IRQ_PORT_F_INTERRUPT_A,                   /* 45 */
2257+     IRQ_PORT_F_INTERRUPT_B,                   /* 46 */
2258+     IRQ_SPI_STATUS,                           /* 47 */
2259+     IRQ_NFC_STATUS,                           /* 48 */
2260+     IRQ_HOSTDP_STATUS,                        /* 49 */
2261+     IRQ_HOREAD_DONE_INTERRUPT,                /* 50 */
2262+     IRQ_RESERVED_19,                          /* 51 */
2263+     IRQ_USB_INT0_INTERRUPT,                   /* 52 */
2264+     IRQ_USB_INT1_INTERRUPT,                   /* 53 */
2265+     IRQ_USB_INT2_INTERRUPT,                   /* 54 */
2266+     IRQ_USB_DMAINT,                           /* 55 */
2267+     IRQ_MAX,                                  /* 56 */
2268+ } e_isr_t;
2269+
2270+
2271+
2272+
2273+ /* source is the source to the SIC (the bit number in SIC_ISR).  isr is
2274+    the function that will be called when the interrupt is active. */
2275+ typedef struct bfin_isr_s {
2276+ #if INTERRUPT_USE_TABLE
2277+   e_isr_t source;
2278+   void (*pFunc)(void *arg);
2279+   void *pArg;
2280+   int priority; /** not used */
2281+ #else
2282+   int source;
2283+   void (*isr)(void *arg);
2284+   void *_arg;
2285+   /* the following are for internal use only */
2286+   uint32_t mask0;
2287+   uint32_t mask1;
2288+   uint32_t vector;
2289+   struct bfin_isr_s *next;
2290+ #endif
2291+ } bfin_isr_t;
2292+
2293+ /**
2294+  * This function registers a new ISR. It will write a new entry to the IVT table
2295+  * @param isr contains a callback function and source
2296+  * @return rtems status code
2297+  */
2298+ rtems_status_code bfin_interrupt_register(bfin_isr_t *isr);
2299+
2300+ /**
2301+  * This function unregisters a registered interrupt handler.
2302+  * @param isr
2303+  */
2304+ rtems_status_code bfin_interrupt_unregister(bfin_isr_t *isr);
2305+
2306+ /**
2307+  * blackfin interrupt initialization routine. It initializes the bfin ISR
2308+  * dispatcher. It will also create SIC CEC map which will be used for
2309+  * identifying the ISR.
2310+  */
2311+ void bfin_interrupt_init(void);
2312+
2313+
2314+ #ifdef __cplusplus
2315+ }
2316+ #endif
2317+
2318+ #endif /* _BFIN_INTERRUPT_H_ */
2319+
2320diff -crBN -X exclude rtems-4.10.0/c/src/lib/libcpu/bfin/configure.ac rtems/c/src/lib/libcpu/bfin/configure.ac
2321*** rtems-4.10.0/c/src/lib/libcpu/bfin/configure.ac     2011-02-02 10:17:24.000000000 -0500
2322--- rtems/c/src/lib/libcpu/bfin/configure.ac    2011-02-25 15:46:42.000000000 -0500
2323***************
2324*** 1,6 ****
2325  ## Process this file with autoconf to produce a configure script.
2326  ##
2327! ## $Id: configure.ac,v 1.2.2.1 2011/02/02 15:17:24 ralf Exp $
2328  ##
2329 
2330  AC_PREREQ([2.68])
2331--- 1,6 ----
2332  ## Process this file with autoconf to produce a configure script.
2333  ##
2334! ## $Id: configure.ac 27 2011-02-25 20:46:42Z rkangral $
2335  ##
2336 
2337  AC_PREREQ([2.68])
2338***************
2339*** 24,29 ****
2340--- 24,33 ----
2341  RTEMS_CHECK_NETWORKING
2342  AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
2343 
2344+ # AM_CONDITIONAL(shared, test "$RTEMS_CPU_MODEL" = "bf52x")
2345+ AM_CONDITIONAL(bf52x, test "$RTEMS_CPU_MODEL" = "bf52x")
2346+
2347+
2348  RTEMS_AMPOLISH3
2349 
2350  # Explicitly list all Makefiles here
2351diff -crBN -X exclude rtems-4.10.0/c/src/lib/libcpu/bfin/include/dmaRegs.h rtems/c/src/lib/libcpu/bfin/include/dmaRegs.h
2352*** rtems-4.10.0/c/src/lib/libcpu/bfin/include/dmaRegs.h        2008-08-15 16:18:41.000000000 -0400
2353--- rtems/c/src/lib/libcpu/bfin/include/dmaRegs.h       2011-02-25 15:46:42.000000000 -0500
2354***************
2355*** 7,13 ****
2356   *  found in the file LICENSE in this distribution or at
2357   *  http://www.rtems.com/license/LICENSE.
2358   *
2359!  *  $Id: dmaRegs.h,v 1.1 2008/08/15 20:18:41 joel Exp $
2360   */
2361 
2362  #ifndef _dmaRegs_h_
2363--- 7,13 ----
2364   *  found in the file LICENSE in this distribution or at
2365   *  http://www.rtems.com/license/LICENSE.
2366   *
2367!  *  $Id: dmaRegs.h 27 2011-02-25 20:46:42Z rkangral $
2368   */
2369 
2370  #ifndef _dmaRegs_h_
2371diff -crBN -X exclude rtems-4.10.0/c/src/lib/libcpu/bfin/include/sicRegs.h rtems/c/src/lib/libcpu/bfin/include/sicRegs.h
2372*** rtems-4.10.0/c/src/lib/libcpu/bfin/include/sicRegs.h        2009-11-30 00:03:49.000000000 -0500
2373--- rtems/c/src/lib/libcpu/bfin/include/sicRegs.h       2011-02-25 15:46:42.000000000 -0500
2374***************
2375*** 7,13 ****
2376   *  found in the file LICENSE in this distribution or at
2377   *  http://www.rtems.com/license/LICENSE.
2378   *
2379!  *  $Id: sicRegs.h,v 1.3 2009/11/30 05:03:49 ralf Exp $
2380   */
2381 
2382  #ifndef _sicRegs_h_
2383--- 7,13 ----
2384   *  found in the file LICENSE in this distribution or at
2385   *  http://www.rtems.com/license/LICENSE.
2386   *
2387!  *  $Id: sicRegs.h 27 2011-02-25 20:46:42Z rkangral $
2388   */
2389 
2390  #ifndef _sicRegs_h_
2391***************
2392*** 16,23 ****
2393--- 16,29 ----
2394  /* register addresses */
2395 
2396  #define SIC_IMASK                (SIC_BASE_ADDRESS + 0x000c)
2397+ #define SIC_IMASK_PITCH          (0x40)
2398+
2399+ #define SIC_ISR                  (SIC_BASE_ADDRESS + 0x0020)
2400+ #define SIC_ISR_PITCH            (0x40)
2401+
2402  #define SIC_IAR_BASE_ADDRESS     (SIC_BASE_ADDRESS + 0x0010)
2403  #define SIC_IAR_PITCH                                   0x04
2404+
2405  #define SIC_IAR0                 (SIC_BASE_ADDRESS + 0x0010)
2406  #if SIC_IAR_COUNT > 1
2407  #define SIC_IAR1                 (SIC_BASE_ADDRESS + 0x0014)
2408***************
2409*** 28,34 ****
2410  #if SIC_IAR_COUNT > 3
2411  #define SIC_IAR3                 (SIC_BASE_ADDRESS + 0x001c)
2412  #endif
2413! #define SIC_ISR                  (SIC_BASE_ADDRESS + 0x0020)
2414  #define SIC_IWR                  (SIC_BASE_ADDRESS + 0x0024)
2415 
2416 
2417--- 34,40 ----
2418  #if SIC_IAR_COUNT > 3
2419  #define SIC_IAR3                 (SIC_BASE_ADDRESS + 0x001c)
2420  #endif
2421!
2422  #define SIC_IWR                  (SIC_BASE_ADDRESS + 0x0024)
2423 
2424 
2425diff -crBN -X exclude rtems-4.10.0/c/src/lib/libcpu/bfin/include/uartRegs.h rtems/c/src/lib/libcpu/bfin/include/uartRegs.h
2426*** rtems-4.10.0/c/src/lib/libcpu/bfin/include/uartRegs.h       2008-08-15 16:18:41.000000000 -0400
2427--- rtems/c/src/lib/libcpu/bfin/include/uartRegs.h      2011-02-25 15:46:42.000000000 -0500
2428***************
2429*** 7,13 ****
2430   *  found in the file LICENSE in this distribution or at
2431   *  http://www.rtems.com/license/LICENSE.
2432   *
2433!  *  $Id: uartRegs.h,v 1.1 2008/08/15 20:18:41 joel Exp $
2434   */
2435 
2436  #ifndef _uartRegs_h_
2437--- 7,13 ----
2438   *  found in the file LICENSE in this distribution or at
2439   *  http://www.rtems.com/license/LICENSE.
2440   *
2441!  *  $Id: uartRegs.h 27 2011-02-25 20:46:42Z rkangral $
2442   */
2443 
2444  #ifndef _uartRegs_h_
2445diff -crBN -X exclude rtems-4.10.0/c/src/lib/libcpu/bfin/Makefile.am rtems/c/src/lib/libcpu/bfin/Makefile.am
2446*** rtems-4.10.0/c/src/lib/libcpu/bfin/Makefile.am      2008-08-15 16:18:40.000000000 -0400
2447--- rtems/c/src/lib/libcpu/bfin/Makefile.am     2011-02-25 15:46:42.000000000 -0500
2448***************
2449*** 1,5 ****
2450  ##
2451! ## $Id: Makefile.am,v 1.1 2008/08/15 20:18:40 joel Exp $
2452  ##
2453 
2454  ACLOCAL_AMFLAGS = -I ../../../aclocal
2455--- 1,5 ----
2456  ##
2457! ## $Id: Makefile.am 27 2011-02-25 20:46:42Z rkangral $
2458  ##
2459 
2460  ACLOCAL_AMFLAGS = -I ../../../aclocal
2461***************
2462*** 10,18 ****
2463--- 10,40 ----
2464 
2465  noinst_PROGRAMS =
2466 
2467+ include_bspdir = $(includedir)/bsp
2468  include_libcpudir = $(includedir)/libcpu
2469+
2470+ include_bsp_HEADERS =
2471  include_libcpu_HEADERS =
2472 
2473+
2474+ ############
2475+ # Start of bf52x files
2476+ if bf52x
2477+
2478+ include_HEADERS = bf52x/include/bf52x.h
2479+
2480+ ## INTERRUPT
2481+ include_bsp_HEADERS += bf52x/interrupt/interrupt.h
2482+ noinst_PROGRAMS += bf52x/interrupt.rel
2483+ bf52x_interrupt_rel_SOURCES = bf52x/interrupt/interrupt.c \
2484+                               bf52x/interrupt/interrupt.h
2485+ bf52x_interrupt_rel_CPPFLAGS = $(AM_CPPFLAGS)
2486+ bf52x_interrupt_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
2487+
2488+ endif
2489+ # endof bf52x
2490+ ############
2491+
2492  include_libcpu_HEADERS += include/bf533.h
2493  include_libcpu_HEADERS += include/bf537.h
2494  include_libcpu_HEADERS += include/cecRegs.h
2495***************
2496*** 47,58 ****
2497--- 69,85 ----
2498  mmu_rel_CPPFLAGS = $(AM_CPPFLAGS)
2499  mmu_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
2500 
2501+ if bf52x
2502+
2503+ else
2504  include_libcpu_HEADERS += interrupt/interrupt.h
2505  noinst_PROGRAMS += interrupt.rel
2506  interrupt_rel_SOURCES = interrupt/interrupt.c
2507  interrupt_rel_CPPFLAGS = $(AM_CPPFLAGS)
2508  interrupt_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
2509 
2510+ endif
2511+
2512  noinst_PROGRAMS += clock.rel
2513  clock_rel_SOURCES = clock/clock.c
2514  clock_rel_CPPFLAGS = $(AM_CPPFLAGS)
2515diff -crBN -X exclude rtems-4.10.0/c/src/lib/libcpu/bfin/preinstall.am rtems/c/src/lib/libcpu/bfin/preinstall.am
2516*** rtems-4.10.0/c/src/lib/libcpu/bfin/preinstall.am    2011-02-08 11:13:15.000000000 -0500
2517--- rtems/c/src/lib/libcpu/bfin/preinstall.am   2011-02-17 10:19:06.000000000 -0500
2518***************
2519*** 13,23 ****
2520--- 13,42 ----
2521  PREINSTALL_FILES =
2522  CLEANFILES = $(PREINSTALL_FILES)
2523 
2524+ $(PROJECT_INCLUDE)/$(dirstamp):
2525+       @$(MKDIR_P) $(PROJECT_INCLUDE)
2526+       @: > $(PROJECT_INCLUDE)/$(dirstamp)
2527+ PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
2528+
2529+ $(PROJECT_INCLUDE)/bsp/$(dirstamp):
2530+       @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp
2531+       @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp)
2532+ PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp)
2533+
2534  $(PROJECT_INCLUDE)/libcpu/$(dirstamp):
2535        @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu
2536        @: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
2537  PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
2538 
2539+ if bf52x
2540+ $(PROJECT_INCLUDE)/bf52x.h: bf52x/include/bf52x.h $(PROJECT_INCLUDE)/$(dirstamp)
2541+       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bf52x.h
2542+ PREINSTALL_FILES += $(PROJECT_INCLUDE)/bf52x.h
2543+
2544+ $(PROJECT_INCLUDE)/bsp/interrupt.h: bf52x/interrupt/interrupt.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
2545+       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/interrupt.h
2546+ PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/interrupt.h
2547+ endif
2548  $(PROJECT_INCLUDE)/libcpu/bf533.h: include/bf533.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
2549        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/bf533.h
2550  PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/bf533.h
2551***************
2552*** 102,111 ****
2553        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/mmu.h
2554  PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/mmu.h
2555 
2556  $(PROJECT_INCLUDE)/libcpu/interrupt.h: interrupt/interrupt.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
2557        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/interrupt.h
2558  PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/interrupt.h
2559!
2560  $(PROJECT_INCLUDE)/libcpu/uart.h: serial/uart.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
2561        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/uart.h
2562  PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/uart.h
2563--- 121,132 ----
2564        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/mmu.h
2565  PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/mmu.h
2566 
2567+ if bf52x
2568+ else
2569  $(PROJECT_INCLUDE)/libcpu/interrupt.h: interrupt/interrupt.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
2570        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/interrupt.h
2571  PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/interrupt.h
2572! endif
2573  $(PROJECT_INCLUDE)/libcpu/uart.h: serial/uart.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
2574        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/uart.h
2575  PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/uart.h
2576diff -crBN -X exclude rtems-4.10.0/c/src/lib/libcpu/bfin/serial/uart.c rtems/c/src/lib/libcpu/bfin/serial/uart.c
2577*** rtems-4.10.0/c/src/lib/libcpu/bfin/serial/uart.c    2009-12-10 23:15:58.000000000 -0500
2578--- rtems/c/src/lib/libcpu/bfin/serial/uart.c   2011-04-12 18:05:42.000000000 -0400
2579***************
2580*** 7,13 ****
2581   *  found in the file LICENSE in this distribution or at
2582   *  http://www.rtems.com/license/LICENSE.
2583   *
2584!  *  $Id: uart.c,v 1.3 2009/12/11 04:15:58 ralf Exp $
2585   */
2586 
2587 
2588--- 7,16 ----
2589   *  found in the file LICENSE in this distribution or at
2590   *  http://www.rtems.com/license/LICENSE.
2591   *
2592!  *  Modified:
2593!  *  $ $Author: rkangral $ Added interrupt support and DMA support
2594!  *
2595!  *  $Id: uart.c 47 2011-04-12 22:05:42Z rkangral $
2596   */
2597 
2598 
2599***************
2600*** 18,26 ****
2601  #include <stdlib.h>
2602 
2603  #include <libcpu/uartRegs.h>
2604  #include "uart.h"
2605 
2606-
2607  /* flags */
2608  #define BFIN_UART_XMIT_BUSY 0x01
2609 
2610--- 21,29 ----
2611  #include <stdlib.h>
2612 
2613  #include <libcpu/uartRegs.h>
2614+ #include <libcpu/dmaRegs.h>
2615  #include "uart.h"
2616 
2617  /* flags */
2618  #define BFIN_UART_XMIT_BUSY 0x01
2619 
2620***************
2621*** 28,72 ****
2622  static bfin_uart_config_t *uartsConfig;
2623 
2624 
2625- static void initializeHardware(int minor) {
2626-   uint16_t divisor;
2627-   char *base;
2628-   uint16_t r;
2629-
2630-   base = uartsConfig->channels[minor].base_address;
2631-
2632-   *(uint16_t volatile *) (base + UART_IER_OFFSET) = 0;
2633-
2634-   if (uartsConfig->channels[minor].force_baud)
2635-     divisor = (uint16_t) (uartsConfig->freq /
2636-                           (uartsConfig->channels[minor].force_baud * 16));
2637-   else
2638-     divisor = (uint16_t) (uartsConfig->freq / (9600 * 16));
2639-   *(uint16_t volatile *) (base + UART_LCR_OFFSET) = UART_LCR_DLAB;
2640-   *(uint16_t volatile *) (base + UART_DLL_OFFSET) = (divisor & 0xff);
2641-   *(uint16_t volatile *) (base + UART_DLH_OFFSET) = ((divisor >> 8) & 0xff);
2642-
2643-   *(uint16_t volatile *) (base + UART_LCR_OFFSET) = UART_LCR_WLS_8;
2644-
2645-   *(uint16_t volatile *) (base + UART_GCTL_OFFSET) = UART_GCTL_UCEN;
2646-
2647-   r = *(uint16_t volatile *) (base + UART_LSR_OFFSET);
2648-   r = *(uint16_t volatile *) (base + UART_RBR_OFFSET);
2649-   r = *(uint16_t volatile *) (base + UART_IIR_OFFSET);
2650-
2651-   return;
2652- }
2653-
2654  static int pollRead(int minor) {
2655    int c;
2656!   char *base;
2657 
2658!   base = uartsConfig->channels[minor].base_address;
2659 
2660    /* check to see if driver is using interrupts so this call will be
2661       harmless (though non-functional) in case some debug code tries to
2662       use it */
2663!   if (!uartsConfig->channels[minor].use_interrupts &&
2664        *((uint16_t volatile *) (base + UART_LSR_OFFSET)) & UART_LSR_DR)
2665      c = *((uint16_t volatile *) (base + UART_RBR_OFFSET));
2666    else
2667--- 31,46 ----
2668  static bfin_uart_config_t *uartsConfig;
2669 
2670 
2671  static int pollRead(int minor) {
2672    int c;
2673!   uint32_t base;
2674 
2675!   base = uartsConfig->channels[minor].uart_baseAddress;
2676 
2677    /* check to see if driver is using interrupts so this call will be
2678       harmless (though non-functional) in case some debug code tries to
2679       use it */
2680!   if (!uartsConfig->channels[minor].uart_useInterrupts &&
2681        *((uint16_t volatile *) (base + UART_LSR_OFFSET)) & UART_LSR_DR)
2682      c = *((uint16_t volatile *) (base + UART_RBR_OFFSET));
2683    else
2684***************
2685*** 75,81 ****
2686    return c;
2687  }
2688 
2689! char bfin_uart_poll_read(int minor) {
2690    int c;
2691 
2692    do {
2693--- 49,55 ----
2694    return c;
2695  }
2696 
2697! char bfin_uart_poll_read(rtems_device_minor_number minor) {
2698    int c;
2699 
2700    do {
2701***************
2702*** 86,94 ****
2703  }
2704 
2705  void bfin_uart_poll_write(int minor, char c) {
2706!   char *base;
2707 
2708!   base = uartsConfig->channels[minor].base_address;
2709 
2710    while (!(*((uint16_t volatile *) (base + UART_LSR_OFFSET)) & UART_LSR_THRE))
2711      ;
2712--- 60,68 ----
2713  }
2714 
2715  void bfin_uart_poll_write(int minor, char c) {
2716!   uint32_t base;
2717 
2718!   base = uartsConfig->channels[minor].uart_baseAddress;
2719 
2720    while (!(*((uint16_t volatile *) (base + UART_LSR_OFFSET)) & UART_LSR_THRE))
2721      ;
2722***************
2723*** 157,200 ****
2724    return count;
2725  }
2726 
2727- static void enableInterrupts(int minor) {
2728-   char *base;
2729 
2730!   base = uartsConfig->channels[minor].base_address;
2731 
2732!   *(uint16_t volatile *) (base + UART_IER_OFFSET) = UART_IER_ETBEI |
2733!                                                     UART_IER_ERBFI;
2734! }
2735 
2736! static void disableAllInterrupts(void) {
2737!   int i;
2738!   char *base;
2739 
2740!   for (i = 0; i < uartsConfig->num_channels; i++) {
2741!     base = uartsConfig->channels[i].base_address;
2742!     *(uint16_t volatile *) (base + UART_IER_OFFSET) = 0;
2743    }
2744- }
2745 
2746! static ssize_t interruptWrite(int minor, const char *buf, size_t len) {
2747!   char *base;
2748 
2749!   base = uartsConfig->channels[minor].base_address;
2750 
2751!   uartsConfig->channels[minor].flags |= BFIN_UART_XMIT_BUSY;
2752!   *(uint16_t volatile *) (base + UART_THR_OFFSET) = *buf;
2753 
2754!   /* one byte written */
2755!   return 1;
2756  }
2757 
2758  static int setAttributes(int minor, const struct termios *termios) {
2759!   char *base;
2760    int baud;
2761    uint16_t divisor;
2762    uint16_t lcr;
2763 
2764!   base = uartsConfig->channels[minor].base_address;
2765    switch (termios->c_cflag & CBAUD) {
2766    case B0:
2767      baud = 0;
2768--- 129,206 ----
2769    return count;
2770  }
2771 
2772 
2773! /**
2774!  * Routine to initialize the hardware. It initialize the DMA,
2775!  * interrupt if required.
2776!  * @param channel channel information
2777!  */
2778! static void initializeHardware(bfin_uart_channel_t *channel) {
2779!   uint16_t divisor        = 0;
2780!   uint32_t base           = 0;
2781!   uint32_t rx_dma_base    = 0;
2782!   uint32_t tx_dma_base    = 0;
2783!   uint16_t r              = 0;
2784 
2785!   if ( NULL == channel ) {
2786!     return;
2787!   }
2788 
2789!   base        = channel->uart_baseAddress;
2790!   rx_dma_base = channel->uart_rxDmaBaseAddress;
2791!   tx_dma_base = channel->uart_txDmaBaseAddress;
2792 
2793!   *(uint16_t volatile *) (base + UART_IER_OFFSET) = 0;
2794!
2795!   if ( 0 != channel->uart_baud) {
2796!     divisor = (uint16_t) (uartsConfig->freq /
2797!         (channel->uart_baud * 16));
2798!   } else {
2799!     divisor = (uint16_t) (uartsConfig->freq / (9600 * 16));
2800    }
2801 
2802!   *(uint16_t volatile *) (base + UART_LCR_OFFSET) = UART_LCR_DLAB;
2803!   *(uint16_t volatile *) (base + UART_DLL_OFFSET) = (divisor & 0xff);
2804!   *(uint16_t volatile *) (base + UART_DLH_OFFSET) = ((divisor >> 8) & 0xff);
2805 
2806!   *(uint16_t volatile *) (base + UART_LCR_OFFSET) = UART_LCR_WLS_8;
2807 
2808!   *(uint16_t volatile *) (base + UART_GCTL_OFFSET) = UART_GCTL_UCEN;
2809!
2810!   r = *(uint16_t volatile *) (base + UART_LSR_OFFSET);
2811!   r = *(uint16_t volatile *) (base + UART_RBR_OFFSET);
2812!   r = *(uint16_t volatile *) (base + UART_IIR_OFFSET);
2813 
2814!   if ( channel->uart_useDma ) {
2815!     *(uint16_t  volatile *)(tx_dma_base + DMA_CONFIG_OFFSET) = 0;
2816!     *(uint16_t  volatile *)(tx_dma_base + DMA_CONFIG_OFFSET) = DMA_CONFIG_DI_EN
2817!         | DMA_CONFIG_SYNC ;
2818!     *(uint16_t  volatile *)(tx_dma_base + DMA_IRQ_STATUS_OFFSET) |=
2819!         DMA_IRQ_STATUS_DMA_DONE | DMA_IRQ_STATUS_DMA_ERR;
2820!
2821!   } else {
2822!     /**
2823!     * We use polling or interrupts only sending one char at a time :(
2824!     */
2825!   }
2826!
2827!   return;
2828  }
2829 
2830+
2831+ /**
2832+  * Set the UART attributes.
2833+  * @param minor
2834+  * @param termios
2835+  * @return
2836+  */
2837  static int setAttributes(int minor, const struct termios *termios) {
2838!   uint32_t base;
2839    int baud;
2840    uint16_t divisor;
2841    uint16_t lcr;
2842 
2843!   base = uartsConfig->channels[minor].uart_baseAddress;
2844    switch (termios->c_cflag & CBAUD) {
2845    case B0:
2846      baud = 0;
2847***************
2848*** 260,267 ****
2849      baud = -1;
2850      break;
2851    }
2852!   if (baud > 0 && uartsConfig->channels[minor].force_baud)
2853!     baud = uartsConfig->channels[minor].force_baud;
2854    switch (termios->c_cflag & CSIZE) {
2855    case CS5:
2856      lcr = UART_LCR_WLS_5;
2857--- 266,273 ----
2858      baud = -1;
2859      break;
2860    }
2861!   if (baud > 0 && uartsConfig->channels[minor].uart_baud)
2862!     baud = uartsConfig->channels[minor].uart_baud;
2863    switch (termios->c_cflag & CSIZE) {
2864    case CS5:
2865      lcr = UART_LCR_WLS_5;
2866***************
2867*** 282,289 ****
2868      lcr |= UART_LCR_PEN | UART_LCR_EPS;
2869      break;
2870    case PARENB | PARODD:
2871!     lcr |= UART_LCR_PEN;
2872!     break;
2873    default:
2874      break;
2875    }
2876--- 288,295 ----
2877      lcr |= UART_LCR_PEN | UART_LCR_EPS;
2878      break;
2879    case PARENB | PARODD:
2880!   lcr |= UART_LCR_PEN;
2881!   break;
2882    default:
2883      break;
2884    }
2885***************
2886*** 301,414 ****
2887    return 0;
2888  }
2889 
2890! void bfin_uart_isr(int source) {
2891!   int i;
2892!   char *base;
2893!   uint16_t uartStat;
2894!   char c;
2895!   uint8_t uartLSR;
2896!
2897!   /* Just use one ISR and check for all UART interrupt sources in it.
2898!      This is less efficient than making use of the vector to narrow down
2899!      the things we need to check, but not all Blackfins separate the
2900!      UART interrupt sources in the same ways.  This way we don't have
2901!      to make this code dependent on the type of Blackfin.  */
2902!   for (i = 0; i < uartsConfig->num_channels; i++) {
2903!     if (uartsConfig->channels[i].use_interrupts) {
2904!       base = uartsConfig->channels[i].base_address;
2905!       uartStat = *(uint16_t volatile *) (base + UART_IIR_OFFSET);
2906!       if ((uartStat & UART_IIR_NINT) == 0) {
2907!         switch (uartStat & UART_IIR_STATUS_MASK) {
2908!         case UART_IIR_STATUS_THRE:
2909!           if (uartsConfig->channels[i].termios &&
2910!               (uartsConfig->channels[i].flags & BFIN_UART_XMIT_BUSY)) {
2911!             uartsConfig->channels[i].flags &= ~BFIN_UART_XMIT_BUSY;
2912!             rtems_termios_dequeue_characters(uartsConfig->channels[i].termios,
2913!                                              1);
2914!           }
2915!           break;
2916!         case UART_IIR_STATUS_RDR:
2917!           c = *(uint16_t volatile *) (base + UART_RBR_OFFSET);
2918!           if (uartsConfig->channels[i].termios)
2919!             rtems_termios_enqueue_raw_characters(
2920!                 uartsConfig->channels[i].termios, &c, 1);
2921!           break;
2922!         case UART_IIR_STATUS_LS:
2923!           uartLSR = *(uint16_t volatile *) (base + UART_LSR_OFFSET);
2924!           /* break, framing error, parity error, or overrun error
2925!              has been detected */
2926!           break;
2927!         default:
2928!           break;
2929!         }
2930!       }
2931!     }
2932    }
2933  }
2934 
2935! rtems_status_code bfin_uart_initialize(rtems_device_major_number major,
2936!                                        bfin_uart_config_t *config) {
2937!   rtems_status_code status;
2938!   int i;
2939 
2940!   status = RTEMS_SUCCESSFUL;
2941 
2942-   rtems_termios_initialize();
2943 
2944!   /*
2945!    *  Register Device Names
2946     */
2947 
2948!   uartsConfig = config;
2949!   for (i = 0; i < config->num_channels; i++) {
2950!     config->channels[i].termios = NULL;
2951!     config->channels[i].flags = 0;
2952!     initializeHardware(i);
2953!     status = rtems_io_register_name(config->channels[i].name, major, i);
2954    }
2955 
2956!    return RTEMS_SUCCESSFUL;
2957  }
2958 
2959  rtems_device_driver bfin_uart_open(rtems_device_major_number major,
2960!                                    rtems_device_minor_number minor,
2961!                                    void *arg) {
2962!   rtems_status_code sc;
2963!   rtems_libio_open_close_args_t *args;
2964    static const rtems_termios_callbacks pollCallbacks = {
2965!     NULL,                        /* firstOpen */
2966!     NULL,                        /* lastClose */
2967!     pollRead,                    /* pollRead */
2968!     pollWrite,                   /* write */
2969!     setAttributes,               /* setAttributes */
2970!     NULL,                        /* stopRemoteTx */
2971!     NULL,                        /* startRemoteTx */
2972!     TERMIOS_POLLED               /* outputUsesInterrupts */
2973    };
2974    static const rtems_termios_callbacks interruptCallbacks = {
2975!     NULL,                        /* firstOpen */
2976!     NULL,                        /* lastClose */
2977!     NULL,                        /* pollRead */
2978!     interruptWrite,              /* write */
2979!     setAttributes,               /* setAttributes */
2980!     NULL,                        /* stopRemoteTx */
2981!     NULL,                        /* startRemoteTx */
2982!     TERMIOS_IRQ_DRIVEN           /* outputUsesInterrupts */
2983    };
2984 
2985!   if (uartsConfig == NULL || minor < 0 || minor >= uartsConfig->num_channels)
2986      return RTEMS_INVALID_NUMBER;
2987 
2988-   sc = rtems_termios_open(major, minor, arg,
2989-                           uartsConfig->channels[minor].use_interrupts ?
2990-                           &interruptCallbacks : &pollCallbacks);
2991    args = arg;
2992    uartsConfig->channels[minor].termios = args->iop->data1;
2993 
2994!   if (uartsConfig->channels[minor].use_interrupts)
2995!     enableInterrupts(minor);
2996!   atexit(disableAllInterrupts);
2997 
2998    return sc;
2999  }
3000 
3001--- 307,634 ----
3002    return 0;
3003  }
3004 
3005! /**
3006!  * Interrupt based uart tx routine. The routine writes one character at a time.
3007!  *
3008!  * @param minor Minor number to indicate uart number
3009!  * @param buf Character buffer which stores characters to be transmitted.
3010!  * @param len Length of buffer to be transmitted.
3011!  * @return
3012!  */
3013! static ssize_t uart_interruptWrite(int minor, const char *buf, size_t len) {
3014!   uint32_t              base      = 0;
3015!   bfin_uart_channel_t*  channel   = NULL;
3016!   rtems_interrupt_level isrLevel;
3017!
3018!   /**
3019!    * Sanity Check
3020!    */
3021!   if (NULL == buf || NULL == channel || NULL == uartsConfig || minor < 0) {
3022!     return 0;
3023    }
3024+
3025+   channel = &(uartsConfig->channels[minor]);
3026+
3027+   if ( NULL == channel || channel->flags &  BFIN_UART_XMIT_BUSY ) {
3028+     return 0;
3029+   }
3030+
3031+   rtems_interrupt_disable(isrLevel);
3032+
3033+   base = channel->uart_baseAddress;
3034+
3035+   channel->flags |= BFIN_UART_XMIT_BUSY;
3036+   channel->length = 1;
3037+   *(uint16_t volatile *) (base + UART_THR_OFFSET) = *buf;
3038+   *(uint16_t volatile *) (base + UART_IER_OFFSET) = UART_IER_ETBEI;
3039+
3040+   rtems_interrupt_enable(isrLevel);
3041+
3042+   return 0;
3043  }
3044 
3045! /**
3046! * This function implements RX ISR
3047! */
3048! void bfinUart_rxIsr(void *_arg)
3049! {
3050!   /**
3051!    * TODO: UART RX ISR implementation.
3052!    */
3053 
3054! }
3055 
3056 
3057! /**
3058!  * This function implements TX ISR. The function gets called when the TX FIFO is
3059!  * empty. It clears the interrupt and dequeues the character. It only tx one
3060!  * character at a time.
3061!  *
3062!  * TODO: error handling.
3063!  * @param _arg gets the channel information.
3064!  */
3065! void bfinUart_txIsr(void *_arg) {
3066!   bfin_uart_channel_t*  channel = NULL;
3067!   uint32_t              base    = 0;
3068!
3069!   /**
3070!    * Sanity check
3071     */
3072+   if (NULL == _arg) {
3073+     /** It should never be NULL */
3074+     return;
3075+   }
3076 
3077!   channel = (bfin_uart_channel_t *) _arg;
3078!
3079!   base = channel->uart_baseAddress;
3080!
3081!   *(uint16_t volatile *) (base + UART_IER_OFFSET) &= ~UART_IER_ETBEI;
3082!   channel->flags &= ~BFIN_UART_XMIT_BUSY;
3083!
3084!   rtems_termios_dequeue_characters(channel->termios, channel->length);
3085!
3086!   return;
3087! }
3088!
3089!
3090!
3091!
3092! /**
3093!  * interrupt based DMA write Routine. It configure the DMA to write len bytes.
3094!  * The DMA supports 64K data only.
3095!  *
3096!  * @param minor Identification number of the UART.
3097!  * @param buf Character buffer pointer
3098!  * @param len length of data items to be written
3099!  * @return data already written
3100!  */
3101! static ssize_t uart_DmaWrite(int minor, const char *buf, size_t len) {
3102!   uint32_t              base        = 0;
3103!   bfin_uart_channel_t*  channel     = NULL;
3104!   uint32_t              tx_dma_base = 0;
3105!   rtems_interrupt_level isrLevel;
3106!
3107!   /**
3108!    * Sanity Check
3109!    */
3110!   if ( NULL == buf || 0 > minor || NULL == uartsConfig ) {
3111!     return 0;
3112!   }
3113!
3114!   channel = &(uartsConfig->channels[minor]);
3115!
3116!   /**
3117!    * Sanity Check and check for transmit busy.
3118!    */
3119!   if ( NULL == channel || BFIN_UART_XMIT_BUSY & channel->flags ) {
3120!     return 0;
3121!   }
3122!
3123!   rtems_interrupt_disable(isrLevel);
3124!
3125!   base        = channel->uart_baseAddress;
3126!   tx_dma_base = channel->uart_txDmaBaseAddress;
3127!
3128!   channel->flags |= BFIN_UART_XMIT_BUSY;
3129!   channel->length = len;
3130!
3131!   *(uint16_t volatile *) (tx_dma_base + DMA_CONFIG_OFFSET) &= ~DMA_CONFIG_DMAEN;
3132!   *(uint32_t volatile *) (tx_dma_base + DMA_START_ADDR_OFFSET) = (uint32_t)buf;
3133!   *(uint16_t volatile *) (tx_dma_base + DMA_X_COUNT_OFFSET) = channel->length;
3134!   *(uint16_t volatile *) (tx_dma_base + DMA_X_MODIFY_OFFSET) = 1;
3135!   *(uint16_t volatile *) (tx_dma_base + DMA_CONFIG_OFFSET) |= DMA_CONFIG_DMAEN;
3136!   *(uint16_t volatile *) (base + UART_IER_OFFSET) = UART_IER_ETBEI;
3137!
3138!   rtems_interrupt_enable(isrLevel);
3139!
3140!   return 0;
3141! }
3142!
3143!
3144! /**
3145!  * RX DMA ISR.
3146!  * The polling route is used for receiving the characters. This is a place
3147!  * holder for future implementation.
3148!  * @param _arg
3149!  */
3150! void bfinUart_rxDmaIsr(void *_arg) {
3151! /**
3152!  * TODO: Implementation of RX DMA
3153!  */
3154! }
3155!
3156! /**
3157!  * This function implements TX dma ISR. It clears the IRQ and dequeues a char
3158!  * The channel argument will have the base address. Since there are two uart
3159!  * and both the uarts can use the same tx dma isr.
3160!  *
3161!  * TODO: 1. Error checking 2. sending correct length ie after looking at the
3162!  * number of elements the uart transmitted.
3163!  *
3164!  * @param _arg argument passed to the interrupt handler. It contains the
3165!  * channel argument.
3166!  */
3167! void bfinUart_txDmaIsr(void *_arg) {
3168!   bfin_uart_channel_t*  channel     = NULL;
3169!   uint32_t              base        = 0;
3170!   uint32_t              tx_dma_base = 0;
3171!
3172!   /**
3173!    * Sanity check
3174!    */
3175!   if (NULL == _arg) {
3176!     /** It should never be NULL */
3177!     return;
3178!   }
3179!
3180!   channel = (bfin_uart_channel_t *) _arg;
3181!
3182!   base        = channel->uart_baseAddress;
3183!   tx_dma_base = channel->uart_txDmaBaseAddress;
3184!
3185!   if ((*(uint16_t volatile *) (tx_dma_base + DMA_IRQ_STATUS_OFFSET)
3186!       & DMA_IRQ_STATUS_DMA_DONE)) {
3187!
3188!     *(uint16_t volatile *) (tx_dma_base + DMA_IRQ_STATUS_OFFSET)
3189!                           |= DMA_IRQ_STATUS_DMA_DONE | DMA_IRQ_STATUS_DMA_ERR;
3190!     channel->flags &= ~BFIN_UART_XMIT_BUSY;
3191!     rtems_termios_dequeue_characters(channel->termios, channel->length);
3192!   } else {
3193!     /* UART DMA did not generate interrupt.
3194!      * This routine must not be called.
3195!      */
3196    }
3197 
3198!   return;
3199! }
3200!
3201! /**
3202!  * Function called during exit
3203!  */
3204! void uart_exit(void)
3205! {
3206!   /**
3207!    * TODO: Flushing of quques
3208!    */
3209!
3210  }
3211 
3212+ /**
3213+  * Opens the device in different modes. The supported modes are
3214+  * 1. Polling
3215+  * 2. Interrupt
3216+  * 3. DMA
3217+  * At exit the uart_Exit function will be called to flush the device.
3218+  *
3219+  * @param major Major number of the device
3220+  * @param minor Minor number of the device
3221+  * @param arg
3222+  * @return
3223+  */
3224  rtems_device_driver bfin_uart_open(rtems_device_major_number major,
3225!     rtems_device_minor_number minor, void *arg) {
3226!   rtems_status_code             sc    = RTEMS_NOT_DEFINED;;
3227!   rtems_libio_open_close_args_t *args = NULL;
3228!
3229!   /**
3230!    * Callback function for polling
3231!    */
3232    static const rtems_termios_callbacks pollCallbacks = {
3233!       NULL,                        /* firstOpen */
3234!       NULL,                        /* lastClose */
3235!       pollRead,                    /* pollRead */
3236!       pollWrite,                   /* write */
3237!       setAttributes,               /* setAttributes */
3238!       NULL,                        /* stopRemoteTx */
3239!       NULL,                        /* startRemoteTx */
3240!       TERMIOS_POLLED               /* outputUsesInterrupts */
3241    };
3242+
3243+   /**
3244+    * Callback function for interrupt based transfers without DMA.
3245+    * We use interrupts for writing only. For reading we use polling.
3246+    */
3247    static const rtems_termios_callbacks interruptCallbacks = {
3248!       NULL,                        /* firstOpen */
3249!       NULL,                        /* lastClose */
3250!       pollRead,                    /* pollRead */
3251!       uart_interruptWrite,              /* write */
3252!       setAttributes,               /* setAttributes */
3253!       NULL,                        /* stopRemoteTx */
3254!       NULL,                        /* startRemoteTx */
3255!       TERMIOS_IRQ_DRIVEN           /* outputUsesInterrupts */
3256    };
3257 
3258!   /**
3259!    * Callback function for interrupt based DMA transfers.
3260!    * We use interrupts for writing only. For reading we use polling.
3261!    */
3262!   static const rtems_termios_callbacks interruptDmaCallbacks = {
3263!       NULL,                        /* firstOpen */
3264!       NULL,                        /* lastClose */
3265!       NULL,                        /* pollRead */
3266!       uart_DmaWrite,              /* write */
3267!       setAttributes,               /* setAttributes */
3268!       NULL,                        /* stopRemoteTx */
3269!       NULL,                        /* startRemoteTx */
3270!       TERMIOS_IRQ_DRIVEN           /* outputUsesInterrupts */
3271!   };
3272!
3273!
3274!   if ( NULL == uartsConfig || 0 > minor || minor >= uartsConfig->num_channels) {
3275      return RTEMS_INVALID_NUMBER;
3276+   }
3277+
3278+   /**
3279+    * Opens device for handling uart send request either by
3280+    * 1. interrupt with DMA
3281+    * 2. interrupt based
3282+    * 3. Polling
3283+    */
3284+   if ( uartsConfig->channels[minor].uart_useDma ) {
3285+     sc = rtems_termios_open(major, minor, arg, &interruptDmaCallbacks);
3286+   } else {
3287+     sc = rtems_termios_open(major, minor, arg,
3288+         uartsConfig->channels[minor].uart_useInterrupts ?
3289+             &interruptCallbacks : &pollCallbacks);
3290+   }
3291 
3292    args = arg;
3293    uartsConfig->channels[minor].termios = args->iop->data1;
3294 
3295!   atexit(uart_exit);
3296 
3297    return sc;
3298  }
3299 
3300+
3301+ /**
3302+ * Uart initialization function.
3303+ * @param major major number of the device
3304+ * @param config configuration parameters
3305+ * @return rtems status code
3306+ */
3307+ rtems_status_code bfin_uart_initialize(rtems_device_major_number major,
3308+     bfin_uart_config_t *config) {
3309+   rtems_status_code sc = RTEMS_NOT_DEFINED;
3310+   int               i  = 0;
3311+
3312+   rtems_termios_initialize();
3313+
3314+   /*
3315+    *  Register Device Names
3316+    */
3317+   uartsConfig = config;
3318+   for (i = 0; i < config->num_channels; i++) {
3319+     config->channels[i].termios = NULL;
3320+     config->channels[i].flags = 0;
3321+     initializeHardware(&(config->channels[i]));
3322+     sc = rtems_io_register_name(config->channels[i].name, major, i);
3323+     if (RTEMS_SUCCESSFUL != sc) {
3324+       return sc;
3325+     }
3326+   }
3327+
3328+   return sc;
3329+ }
3330diff -crBN -X exclude rtems-4.10.0/c/src/lib/libcpu/bfin/serial/uart.h rtems/c/src/lib/libcpu/bfin/serial/uart.h
3331*** rtems-4.10.0/c/src/lib/libcpu/bfin/serial/uart.h    2009-11-30 00:03:49.000000000 -0500
3332--- rtems/c/src/lib/libcpu/bfin/serial/uart.h   2011-04-12 18:05:42.000000000 -0400
3333***************
3334*** 8,35 ****
3335   *  found in the file LICENSE in this distribution or at
3336   *  http://www.rtems.com/license/LICENSE.
3337   *
3338!  *  $Id: uart.h,v 1.3 2009/11/30 05:03:49 ralf Exp $
3339   */
3340 
3341! #ifndef _uart_h_
3342! #define _uart_h_
3343 
3344 
3345  #ifdef __cplusplus
3346  extern "C" {
3347  #endif
3348 
3349!
3350  typedef struct {
3351!   const char *name;
3352!   void *base_address;
3353!   bool  use_interrupts;
3354!   int force_baud;
3355!   /* the following are for internal use */
3356!   void *termios;
3357!   uint8_t volatile flags;
3358  } bfin_uart_channel_t;
3359 
3360  typedef struct {
3361    uint32_t freq;
3362    int num_channels;
3363--- 8,45 ----
3364   *  found in the file LICENSE in this distribution or at
3365   *  http://www.rtems.com/license/LICENSE.
3366   *
3367!  *  Modified:
3368!  *  $Author: rkangral $ Added interrupt support and DMA support
3369!  *
3370!  *  $Id: uart.h 47 2011-04-12 22:05:42Z rkangral $
3371   */
3372 
3373!
3374! #ifndef _UART_H_
3375! #define _UART_H_
3376 
3377 
3378  #ifdef __cplusplus
3379  extern "C" {
3380  #endif
3381 
3382! /** bfin_uart_channel object
3383!  */
3384  typedef struct {
3385!   const char        *name;                 /** Holds name of the device */
3386!   uint32_t          uart_baseAddress;           /** UART base address */
3387!   uint32_t          uart_rxDmaBaseAddress;      /** RX DMA base address */
3388!   uint32_t          uart_txDmaBaseAddress;      /** TX DMA base address */
3389!   bool              uart_useInterrupts;         /** are interrupts used */
3390!   bool              uart_useDma;                /** is dma used */
3391!   int               uart_baud;                  /** baud rate, 0 for default */
3392!
3393!   void              *termios;                   /** termios associated */
3394!   uint8_t volatile  flags;                      /** flags for internal use */
3395!   uint16_t          length;                     /** length for internal use */
3396  } bfin_uart_channel_t;
3397 
3398+
3399  typedef struct {
3400    uint32_t freq;
3401    int num_channels;
3402***************
3403*** 36,59 ****
3404    bfin_uart_channel_t *channels;
3405  } bfin_uart_config_t;
3406 
3407 
3408! char bfin_uart_poll_read(int minor);
3409 
3410  void bfin_uart_poll_write(int minor, char c);
3411 
3412  rtems_status_code bfin_uart_initialize(rtems_device_major_number major,
3413!                                        bfin_uart_config_t *config);
3414 
3415  rtems_device_driver bfin_uart_open(rtems_device_major_number major,
3416!                                    rtems_device_minor_number minor,
3417!                                    void *arg);
3418 
3419! void bfin_uart_isr(int source);
3420 
3421 
3422  #ifdef __cplusplus
3423  }
3424  #endif
3425 
3426! #endif /* _uart_h_ */
3427 
3428--- 46,140 ----
3429    bfin_uart_channel_t *channels;
3430  } bfin_uart_config_t;
3431 
3432+ /**
3433+  * @param base_address defines the UART base address
3434+  * @param source defines the source that caused the interrupt. This argument
3435+  * will help us in identifying if Rx or TX caused the interrupt.
3436+  */
3437+ typedef struct {
3438+   uint32_t base_address;
3439+   int source;
3440+ } bfin_uart_arg_t;
3441+
3442 
3443!
3444! char bfin_uart_poll_read(rtems_device_minor_number minor);
3445 
3446  void bfin_uart_poll_write(int minor, char c);
3447 
3448+
3449+ /**
3450+ * Uart initialization function.
3451+ * @param major major number of the device
3452+ * @param config configuration parameters
3453+ * @return rtems status code
3454+ */
3455  rtems_status_code bfin_uart_initialize(rtems_device_major_number major,
3456!     bfin_uart_config_t *config);
3457!
3458!
3459 
3460+ /**
3461+  * Opens the device in different modes. The supported modes are
3462+  * 1. Polling
3463+  * 2. Interrupt
3464+  * 3. DMA
3465+  * At exit the uart_Exit function will be called to flush the device.
3466+  *
3467+  * @param major Major number of the device
3468+  * @param minor Minor number of the device
3469+  * @param arg
3470+  * @return
3471+  */
3472  rtems_device_driver bfin_uart_open(rtems_device_major_number major,
3473!     rtems_device_minor_number minor, void *arg);
3474!
3475!
3476!
3477! /**
3478!  * This function implements TX dma ISR. It clears the IRQ and dequeues a char
3479!  * The channel argument will have the base address. Since there are two uart
3480!  * and both the uarts can use the same tx dma isr.
3481!  *
3482!  * TODO: 1. Error checking 2. sending correct length ie after looking at the
3483!  * number of elements the uart transmitted.
3484!  *
3485!  * @param _arg argument passed to the interrupt handler. It contains the
3486!  * channel argument.
3487!  */
3488! void bfinUart_txDmaIsr(void *_arg);
3489!
3490!
3491!
3492! /**
3493!  * RX DMA ISR.
3494!  * The polling route is used for receiving the characters. This is a place
3495!  * holder for future implementation.
3496!  * @param _arg
3497!  */
3498! void bfinUart_rxDmaIsr(void *_arg);
3499!
3500!
3501! /**
3502!  * This function implements TX ISR. The function gets called when the TX FIFO is
3503!  * empty. It clears the interrupt and dequeues the character. It only tx one
3504!  * character at a time.
3505!  *
3506!  * TODO: error handling.
3507!  * @param _arg gets the channel information.
3508!  */
3509! void bfinUart_txIsr(void *_arg);
3510!
3511 
3512! /**
3513! * This function implements RX ISR
3514! */
3515! void bfinUart_rxIsr(void *_arg);
3516 
3517 
3518  #ifdef __cplusplus
3519  }
3520  #endif
3521 
3522! #endif /* _UART_H_ */
3523 
3524diff -crBN -X exclude rtems-4.10.0/cpukit/score/cpu/bfin/Makefile.am rtems/cpukit/score/cpu/bfin/Makefile.am
3525*** rtems-4.10.0/cpukit/score/cpu/bfin/Makefile.am      2010-03-27 10:59:26.000000000 -0400
3526--- rtems/cpukit/score/cpu/bfin/Makefile.am     2011-02-14 18:39:06.000000000 -0500
3527***************
3528*** 8,14 ****
3529  include_rtems_HEADERS = rtems/asm.h
3530 
3531  include_rtems_bfindir = $(includedir)/rtems/bfin
3532! include_rtems_bfin_HEADERS = rtems/bfin/bfin.h rtems/bfin/bf533.h
3533 
3534  include_rtems_scoredir = $(includedir)/rtems/score
3535  include_rtems_score_HEADERS = rtems/score/cpu.h rtems/score/bfin.h \
3536--- 8,14 ----
3537  include_rtems_HEADERS = rtems/asm.h
3538 
3539  include_rtems_bfindir = $(includedir)/rtems/bfin
3540! include_rtems_bfin_HEADERS = rtems/bfin/bfin.h rtems/bfin/bf533.h rtems/bfin/bf52x.h
3541 
3542  include_rtems_scoredir = $(includedir)/rtems/score
3543  include_rtems_score_HEADERS = rtems/score/cpu.h rtems/score/bfin.h \
3544diff -crBN -X exclude rtems-4.10.0/cpukit/score/cpu/bfin/preinstall.am rtems/cpukit/score/cpu/bfin/preinstall.am
3545*** rtems-4.10.0/cpukit/score/cpu/bfin/preinstall.am    2011-02-08 11:13:15.000000000 -0500
3546--- rtems/cpukit/score/cpu/bfin/preinstall.am   2011-02-14 18:39:06.000000000 -0500
3547***************
3548*** 35,40 ****
3549--- 35,44 ----
3550        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/bfin/bf533.h
3551  PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/bfin/bf533.h
3552 
3553+ $(PROJECT_INCLUDE)/rtems/bfin/bf52x.h: rtems/bfin/bf52x.h $(PROJECT_INCLUDE)/rtems/bfin/$(dirstamp)
3554+       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/bfin/bf52x.h
3555+ PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/bfin/bf52x.h
3556+
3557  $(PROJECT_INCLUDE)/rtems/score/$(dirstamp):
3558        @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score
3559        @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
3560diff -crBN -X exclude rtems-4.10.0/cpukit/score/cpu/bfin/rtems/bfin/bf52x.h rtems/cpukit/score/cpu/bfin/rtems/bfin/bf52x.h
3561*** rtems-4.10.0/cpukit/score/cpu/bfin/rtems/bfin/bf52x.h       1969-12-31 19:00:00.000000000 -0500
3562--- rtems/cpukit/score/cpu/bfin/rtems/bfin/bf52x.h      2011-02-22 17:19:49.000000000 -0500
3563***************
3564*** 0 ****
3565--- 1,431 ----
3566+ /**
3567+  *@file bf52x.h
3568+  *
3569+  *  This file defines basic MMR for the Blackfin 52x CPU.
3570+  *  The MMR have been taken from the ADSP-BF52x Blackfin Processor
3571+  *  Hardware Reference from Analog Devices. Mentioned Chapters
3572+  *  refer to this Documentation.
3573+  *
3574+  *    Based on bf533.h
3575+  *
3576+  *  COPYRIGHT (c) 2006.
3577+  *  Atos Automacao Industrial LTDA.
3578+  *             modified by Alain Schaefer <alain.schaefer@easc.ch>
3579+  *                     and Antonio Giovanini <antonio@atos.com.br>
3580+  *
3581+  *  The license and distribution terms for this file may be
3582+  *  found in the file LICENSE in this distribution or at
3583+  *  http://www.rtems.com/license/LICENSE.
3584+  *
3585+  *
3586+  * @author    Rohan Kangralkar, ECE Department Northeastern University
3587+  * @date        02/15/2011
3588+  *
3589+  * HISTORY:
3590+  * $Id$
3591+  *
3592+  *
3593+  */
3594+
3595+ #ifndef _RTEMS_BFIN_52x_H
3596+ #define _RTEMS_BFIN_52x_H
3597+
3598+ #include <rtems/bfin/bfin.h>
3599+
3600+ #ifdef __cplusplus
3601+ extern "C" {
3602+ #endif
3603+
3604+
3605+ /* Clock and System Control  Chapter 8 */
3606+ #define PLL_CTL                0xFFC00000L
3607+ #define PLL_DIV                0xFFC00004L
3608+ #define VR_CTL                 0xFFC00008L
3609+ #define PLL_STAT               0xFFC0000CL
3610+ #define PLL_LOCKCNT            0xFFC00010L
3611+ #define SWRST                  0xFFC00100L
3612+ #define SYSCR                  0xFFC00104L
3613+
3614+ /* SPI Controller           Chapter 10 */
3615+ #define SPI_CTL                0xFFC00500L
3616+ #define SPI_FLG                0xFFC00504L
3617+ #define SPI_STAT               0xFFC00508L
3618+ #define SPI_TDBR               0xFFC0050CL
3619+ #define SPI_RDBR               0xFFC00510L
3620+ #define SPI_BAUD               0xFFC00514L
3621+ #define SPI_SHADOW             0xFFC00518L
3622+
3623+ /* SPORT0 Controller */
3624+ #define SPORT0_TCR1            0xFFC00800L
3625+ #define SPORT0_TCR2            0xFFC00804L
3626+ #define SPORT0_TCLKDIV         0xFFC00808L
3627+ #define SPORT0_TFSDIV          0xFFC0080CL
3628+ #define SPORT0_TX              0xFFC00810L
3629+ #define SPORT0_RX              0xFFC00818L
3630+ #define SPORT0_RCR1            0xFFC00820L
3631+ #define SPORT0_RCR2            0xFFC00824L
3632+ #define SPORT0_RCLKDIV         0xFFC00828L
3633+ #define SPORT0_RFSDIV          0xFFC0082CL
3634+ #define SPORT0_STAT            0xFFC00830L
3635+ #define SPORT0_CHNL            0xFFC00834L
3636+ #define SPORT0_MCMC1           0xFFC00838L
3637+ #define SPORT0_MCMC2           0xFFC0083CL
3638+ #define SPORT0_MTCS0           0xFFC00840L
3639+ #define SPORT0_MTCS1           0xFFC00844L
3640+ #define SPORT0_MTCS2           0xFFC00848L
3641+ #define SPORT0_MTCS3           0xFFC0084CL
3642+ #define SPORT0_MRCS0           0xFFC00850L
3643+ #define SPORT0_MRCS1           0xFFC00854L
3644+ #define SPORT0_MRCS2           0xFFC00858L
3645+ #define SPORT0_MRCS3           0xFFC0085CL
3646+
3647+ /* Parallel Peripheral Interface (PPI) Chapter 11 */
3648+
3649+ #define PPI_CONTROL            0xFFC01000L
3650+ #define PPI_STATUS             0xFFC01004L
3651+ #define PPI_COUNT              0xFFC01008L
3652+ #define PPI_DELAY              0xFFC0100CL
3653+ #define PPI_FRAME              0xFFC01010L
3654+
3655+ /*********  PPI MASKS ***********/
3656+ /*  PPI_CONTROL Masks */
3657+ #define PORT_EN                0x00000001
3658+ #define PORT_DIR               0x00000002
3659+ #define XFR_TYPE               0x0000000C
3660+ #define PORT_CFG               0x00000030
3661+ #define FLD_SEL                0x00000040
3662+ #define PACK_EN                0x00000080
3663+ #define DMA32                  0x00000100
3664+ #define SKIP_EN                0x00000200
3665+ #define SKIP_EO                0x00000400
3666+ #define DLENGTH                0x00003800
3667+ #define DLEN_8                 0x0
3668+ #define DLEN(x)                (((x-9) & 0x07) << 11)
3669+ #define POL                    0x0000C000
3670+
3671+ /* PPI_STATUS Masks */
3672+ #define FLD                    0x00000400
3673+ #define FT_ERR                 0x00000800
3674+ #define OVR                    0x00001000
3675+ #define UNDR                   0x00002000
3676+ #define ERR_DET                0x00004000
3677+ #define ERR_NCOR               0x00008000
3678+
3679+ /* SPORT1 Controller        Chapter 12 */
3680+ #define SPORT1_TCR1            0xFFC00900L
3681+ #define SPORT1_TCR2            0xFFC00904L
3682+ #define SPORT1_TCLKDIV         0xFFC00908L
3683+ #define SPORT1_TFSDIV          0xFFC0090CL
3684+ #define SPORT1_TX              0xFFC00910L
3685+ #define SPORT1_RX              0xFFC00918L
3686+ #define SPORT1_RCR1            0xFFC00920L
3687+ #define SPORT1_RCR2            0xFFC00924L
3688+ #define SPORT1_RCLKDIV         0xFFC00928L
3689+ #define SPORT1_RFSDIV          0xFFC0092CL
3690+ #define SPORT1_STAT            0xFFC00930L
3691+ #define SPORT1_CHNL            0xFFC00934L
3692+ #define SPORT1_MCMC1           0xFFC00938L
3693+ #define SPORT1_MCMC2           0xFFC0093CL
3694+ #define SPORT1_MTCS0           0xFFC00940L
3695+ #define SPORT1_MTCS1           0xFFC00944L
3696+ #define SPORT1_MTCS2           0xFFC00948L
3697+ #define SPORT1_MTCS3           0xFFC0094CL
3698+ #define SPORT1_MRCS0           0xFFC00950L
3699+ #define SPORT1_MRCS1           0xFFC00954L
3700+ #define SPORT1_MRCS2           0xFFC00958L
3701+ #define SPORT1_MRCS3           0xFFC0095CL
3702+
3703+ /* SPORTx_TCR1 Masks */
3704+ #define TSPEN                  0x0001
3705+ #define ITCLK                  0x0002
3706+ #define TDTYPE                 0x000C
3707+ #define TLSBIT                 0x0010
3708+ #define ITFS                   0x0200
3709+ #define TFSR                   0x0400
3710+ #define DITFS                  0x0800
3711+ #define LTFS                   0x1000
3712+ #define LATFS                  0x2000
3713+ #define TCKFE                  0x4000
3714+
3715+ /* SPORTx_TCR2 Masks */
3716+ #define SLEN                   0x001F
3717+ #define TXSE                   0x0100
3718+ #define TSFSE                  0x0200
3719+ #define TRFST                  0x0400
3720+
3721+ /* SPORTx_RCR1 Masks */
3722+ #define RSPEN                  0x0001
3723+ #define IRCLK                  0x0002
3724+ #define RDTYPE                 0x000C
3725+ #define RULAW                  0x0008
3726+ #define RALAW                  0x000C
3727+ #define RLSBIT                 0x0010
3728+ #define IRFS                   0x0200
3729+ #define RFSR                   0x0400
3730+ #define LRFS                   0x1000
3731+ #define LARFS                  0x2000
3732+ #define RCKFE                  0x4000
3733+
3734+ /* SPORTx_RCR2 Masks */
3735+ #define SLEN                   0x001F
3736+ #define RXSE                   0x0100
3737+ #define RSFSE                  0x0200
3738+ #define RRFST                  0x0400
3739+
3740+ /* SPORTx_STAT Masks */
3741+ #define RXNE                   0x0001
3742+ #define RUVF                   0x0002
3743+ #define ROVF                   0x0004
3744+ #define TXF                    0x0008
3745+ #define TUVF                   0x0010
3746+ #define TOVF                   0x0020
3747+ #define TXHRE                  0x0040
3748+
3749+ /* SPORTx_MCMC1 Masks */
3750+ #define WSIZE                  0x0000F000
3751+ #define WOFF                   0x000003FF
3752+
3753+ /* SPORTx_MCMC2 Masks */
3754+ #define MCCRM                  0x00000003
3755+ #define MCDTXPE                0x00000004
3756+ #define MCDRXPE                0x00000008
3757+ #define MCMEN                  0x00000010
3758+ #define FSDR                   0x00000080
3759+ #define MFD                    0x0000F000
3760+
3761+ /* UART Controller          Chapter 13 */
3762+ #define UART_THR               0xFFC00400L
3763+ #define UART_RBR               0xFFC00400L
3764+ #define UART_DLL               0xFFC00400L
3765+ #define UART_IER               0xFFC00404L
3766+ #define UART_DLH               0xFFC00404L
3767+ #define UART_IIR               0xFFC00408L
3768+ #define UART_LCR               0xFFC0040CL
3769+ #define UART_MCR               0xFFC00410L
3770+ #define UART_LSR               0xFFC00414L
3771+ #define UART_SCR               0xFFC0041CL
3772+ #define UART_GCTL              0xFFC00424L
3773+
3774+ /*
3775+  * UART CONTROLLER MASKS
3776+  */
3777+
3778+ /* UART_LCR */
3779+ #define DLAB                   0x80
3780+ #define SB                     0x40
3781+ #define STP                    0x20
3782+ #define EPS                    0x10
3783+ #define PEN                    0x08
3784+ #define STB                    0x04
3785+ #define WLS(x)                 ((x-5) & 0x03)
3786+
3787+ #define DLAB_P                 0x07
3788+ #define SB_P                   0x06
3789+ #define STP_P                  0x05
3790+ #define EPS_P                  0x04
3791+ #define PEN_P                  0x03
3792+ #define STB_P                  0x02
3793+ #define WLS_P1                 0x01
3794+ #define WLS_P0                 0x00
3795+
3796+ /* UART_MCR */
3797+ #define LOOP_ENA               0x10
3798+ #define LOOP_ENA_P             0x04
3799+
3800+ /* UART_LSR */
3801+ #define TEMT                   0x40
3802+ #define THRE                   0x20
3803+ #define BI                     0x10
3804+ #define FE                     0x08
3805+ #define PE                     0x04
3806+ #define OE                     0x02
3807+ #define DR                     0x01
3808+
3809+ #define TEMP_P                 0x06
3810+ #define THRE_P                 0x05
3811+ #define BI_P                   0x04
3812+ #define FE_P                   0x03
3813+ #define PE_P                   0x02
3814+ #define OE_P                   0x01
3815+ #define DR_P                   0x00
3816+
3817+ /* UART_IER */
3818+ #define ELSI                   0x04
3819+ #define ETBEI                  0x02
3820+ #define ERBFI                  0x01
3821+
3822+ #define ELSI_P                 0x02
3823+ #define ETBEI_P                0x01
3824+ #define ERBFI_P                0x00
3825+
3826+ /* UART_IIR */
3827+ #define STATUS(x)              ((x << 1) & 0x06)
3828+ #define NINT                   0x01
3829+ #define STATUS_P1              0x02
3830+ #define STATUS_P0              0x01
3831+ #define NINT_P                 0x00
3832+
3833+ /* UART_GCTL */
3834+ #define FFE                    0x20
3835+ #define FPE                    0x10
3836+ #define RPOLC                  0x08
3837+ #define TPOLC                  0x04
3838+ #define IREN                   0x02
3839+ #define UCEN                   0x01
3840+
3841+ #define FFE_P                  0x05
3842+ #define FPE_P                  0x04
3843+ #define RPOLC_P                0x03
3844+ #define TPOLC_P                0x02
3845+ #define IREN_P                 0x01
3846+ #define UCEN_P                 0x00
3847+
3848+ /* General Purpose IO        Chapter 14*/
3849+ #define FIO_FLAG_D             0xFFC00700L
3850+ #define FIO_FLAG_C             0xFFC00704L
3851+ #define FIO_FLAG_S             0xFFC00708L
3852+ #define FIO_FLAG_T             0xFFC0070CL
3853+ #define FIO_MASKA_D            0xFFC00710L
3854+ #define FIO_MASKA_C            0xFFC00714L
3855+ #define FIO_MASKA_S            0xFFC00718L
3856+ #define FIO_MASKA_T            0xFFC0071CL
3857+ #define FIO_MASKB_D            0xFFC00720L
3858+ #define FIO_MASKB_C            0xFFC00724L
3859+ #define FIO_MASKB_S            0xFFC00728L
3860+ #define FIO_MASKB_T            0xFFC0072CL
3861+ #define FIO_DIR                0xFFC00730L
3862+ #define FIO_POLAR              0xFFC00734L
3863+ #define FIO_EDGE               0xFFC00738L
3864+ #define FIO_BOTH               0xFFC0073CL
3865+ #define FIO_INEN               0xFFC00740L
3866+
3867+
3868+ /* General Purpose IO        Chapter 9*/
3869+ #define PORTH_FER              0xFFC03208
3870+ #define PORTH_MUX              0xFFC03218
3871+ #define PORTHIO_DIR            0xFFC01730
3872+ #define PORTHIO_INEN           0xFFC01740
3873+ #define PORTHIO                0xFFC01700
3874+ #define PORTHIO_SET            0xFFC01708
3875+ #define PORTHIO_CLEAR          0xFFC01704
3876+ #define PORTHIO_TOGGLE         0xFFC0170C
3877+
3878+
3879+ #define FIO_INEN               0xFFC00740L
3880+ #define FIO_POLAR              0xFFC00734L
3881+ #define FIO_EDGE               0xFFC00738L
3882+ #define FIO_BOTH               0xFFC0073CL
3883+
3884+
3885+
3886+ #define FIO_FLAG_C             0xFFC00704L
3887+ #define FIO_FLAG_S             0xFFC00708L
3888+ #define FIO_FLAG_T             0xFFC0070CL
3889+ #define FIO_MASKA_D            0xFFC00710L
3890+ #define FIO_MASKA_C            0xFFC00714L
3891+ #define FIO_MASKA_S            0xFFC00718L
3892+ #define FIO_MASKA_T            0xFFC0071CL
3893+ #define FIO_MASKB_D            0xFFC00720L
3894+ #define FIO_MASKB_C            0xFFC00724L
3895+ #define FIO_MASKB_S            0xFFC00728L
3896+ #define FIO_MASKB_T            0xFFC0072CL
3897+
3898+
3899+ /*  General Purpose IO Masks */
3900+ #define PF0                    0x0001
3901+ #define PF1                    0x0002
3902+ #define PF2                    0x0004
3903+ #define PF3                    0x0008
3904+ #define PF4                    0x0010
3905+ #define PF5                    0x0020
3906+ #define PF6                    0x0040
3907+ #define PF7                    0x0080
3908+ #define PF8                    0x0100
3909+ #define PF9                    0x0200
3910+ #define PF10                   0x0400
3911+ #define PF11                   0x0800
3912+ #define PF12                   0x1000
3913+ #define PF13                   0x2000
3914+ #define PF14                   0x4000
3915+ #define PF15                   0x8000
3916+
3917+
3918+ /* TIMER 0, 1, 2            Chapter 15 */
3919+ #define TIMER0_CONFIG          0xFFC00600L
3920+ #define TIMER0_COUNTER         0xFFC00604L
3921+ #define TIMER0_PERIOD          0xFFC00608L
3922+ #define TIMER0_WIDTH           0xFFC0060CL
3923+
3924+ #define TIMER1_CONFIG          0xFFC00610L
3925+ #define TIMER1_COUNTER         0xFFC00614L
3926+ #define TIMER1_PERIOD          0xFFC00618L
3927+ #define TIMER1_WIDTH           0xFFC0061CL
3928+
3929+ #define TIMER2_CONFIG          0xFFC00620L
3930+ #define TIMER2_COUNTER         0xFFC00624L
3931+ #define TIMER2_PERIOD          0xFFC00628L
3932+ #define TIMER2_WIDTH           0xFFC0062CL
3933+
3934+ #define TIMER_ENABLE           0xFFC00640L
3935+ #define TIMER_DISABLE          0xFFC00644L
3936+ #define TIMER_STATUS           0xFFC00648L
3937+
3938+ /* Real Time Clock          Chapter 16 */
3939+ #define RTC_STAT               0xFFC00300L
3940+ #define RTC_ICTL               0xFFC00304L
3941+ #define RTC_ISTAT              0xFFC00308L
3942+ #define RTC_SWCNT              0xFFC0030CL
3943+ #define RTC_ALARM              0xFFC00310L
3944+ #define RTC_FAST               0xFFC00314L
3945+ #define RTC_PREN               0xFFC00314L
3946+
3947+ /* RTC_FAST Mask (RTC_PREN Mask) */
3948+ #define ENABLE_PRESCALE        0x00000001
3949+ #define PREN                   0x00000001
3950+
3951+ /* Asynchronous Memory Controller EBUI, Chapter 17*/
3952+ #define EBIU_AMGCTL            0xFFC00A00L
3953+ #define EBIU_AMBCTL0           0xFFC00A04L
3954+ #define EBIU_AMBCTL1           0xFFC00A08L
3955+
3956+ /* SDRAM Controller External Bus Interface Unit */
3957+
3958+ #define EBIU_SDGCTL            0xFFC00A10L
3959+ #define EBIU_SDBCTL            0xFFC00A14L
3960+ #define EBIU_SDRRC             0xFFC00A18L
3961+ #define EBIU_SDSTAT            0xFFC00A1CL
3962+
3963+
3964+
3965+
3966+ /* DCPLB_DATA and ICPLB_DATA Registers */
3967+ /*** Bit Positions */
3968+ #define CPLB_VALID_P            0x00000000  /* 0=invalid entry, 1=valid entry */
3969+ #define CPLB_LOCK_P             0x00000001  /* 0=entry may be replaced, 1=entry locked */
3970+ #define CPLB_USER_RD_P          0x00000002  /* 0=no read access, 1=read access allowed (user mode) */
3971+ /*** Masks */
3972+ #define CPLB_VALID             0x00000001  /* 0=invalid entry, 1=valid entry */
3973+ #define CPLB_LOCK              0x00000002  /* 0=entry may be replaced, 1=entry locked */
3974+ #define CPLB_USER_RD           0x00000004  /* 0=no read access, 1=read access allowed (user mode) */
3975+ #define PAGE_SIZE_1KB          0x00000000  /* 1 KB page size */
3976+ #define PAGE_SIZE_4KB          0x00010000  /* 4 KB page size */
3977+ #define PAGE_SIZE_1MB          0x00020000  /* 1 MB page size */
3978+ #define PAGE_SIZE_4MB          0x00030000  /* 4 MB page size */
3979+ #define CPLB_PORTPRIO             0x00000200  /* 0=low priority port, 1= high priority port */
3980+ #define CPLB_L1_CHBL           0x00001000  /* 0=non-cacheable in L1, 1=cacheable in L1 */
3981+ /*** ICPLB_DATA only */
3982+ #define CPLB_LRUPRIO              0x00000100  /* 0=can be replaced by any line, 1=priority for non-replacement */
3983+ /*** DCPLB_DATA only */
3984+ #define CPLB_USER_WR           0x00000008  /* 0=no write access, 0=write access allowed (user mode) */
3985+ #define CPLB_SUPV_WR           0x00000010  /* 0=no write access, 0=write access allowed (supervisor mode) */
3986+ #define CPLB_DIRTY             0x00000080  /* 1=dirty, 0=clean */
3987+ #define CPLB_L1_AOW                       0x00008000  /* 0=do not allocate cache lines on write-through writes,  */
3988+                                                                                   /* 1= allocate cache lines on write-through writes. */
3989+ #define CPLB_WT                0x00004000  /* 0=write-back, 1=write-through */
3990+
3991+
3992+ #ifdef __cplusplus
3993+ }
3994+ #endif
3995+
3996+ #endif /* _RTEMS_SCORE_BFIN_H */
3997diff -crBN -X exclude rtems-4.10.0/cpukit/score/cpu/bfin/rtems/score/cpu.h rtems/cpukit/score/cpu/bfin/rtems/score/cpu.h
3998*** rtems-4.10.0/cpukit/score/cpu/bfin/rtems/score/cpu.h        2010-04-17 15:24:16.000000000 -0400
3999--- rtems/cpukit/score/cpu/bfin/rtems/score/cpu.h       2011-02-22 17:19:20.000000000 -0500
4000***************
4001*** 625,631 ****
4002   *
4003   *  XXX document implementation including references if appropriate
4004   */
4005! #define CPU_STACK_MINIMUM_SIZE          (1024*4)
4006 
4007  /**
4008   *  CPU's worst alignment requirement for data types on a byte boundary.  This
4009--- 625,631 ----
4010   *
4011   *  XXX document implementation including references if appropriate
4012   */
4013! #define CPU_STACK_MINIMUM_SIZE          (1024*8)
4014 
4015  /**
4016   *  CPU's worst alignment requirement for data types on a byte boundary.  This
4017***************
4018*** 693,699 ****
4019   *
4020   *  XXX document implementation including references if appropriate
4021   */
4022! #define CPU_STACK_ALIGNMENT        0
4023 
4024  /*
4025   *  ISR handler macros
4026--- 693,699 ----
4027   *
4028   *  XXX document implementation including references if appropriate
4029   */
4030! #define CPU_STACK_ALIGNMENT        8
4031 
4032  /*
4033   *  ISR handler macros