Ticket #1738: uC5282_clk_speed.diff

File uC5282_clk_speed.diff, 5.0 KB (added by strauman, on Feb 8, 2011 at 11:38:25 PM)

patch against rtems-4-10-branch implementing proposed change

Line 
1? c/src/lib/libbsp/m68k/uC5282/Feil
2Index: c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c
3===================================================================
4RCS file: /usr1/CVS/rtems/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c,v
5retrieving revision 1.59
6diff -c -r1.59 bspstart.c
7*** c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c     26 Apr 2010 17:44:57 -0000      1.59
8--- c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c     3 Feb 2011 17:58:21 -0000
9***************
10*** 22,27 ****
11--- 22,28 ----
12  #include <rtems/error.h>
13  #include <errno.h>
14  #include <stdio.h>
15+ #include <mcf5282/mcf5282.h>
16 
17  /*
18   * Location of 'VME' access
19***************
20*** 34,40 ****
21--- 35,45 ----
22   */
23  extern char RamSize[];
24  extern char RamBase[];
25+ extern char _CPUClockSpeed[];
26+ extern char _PLLRefClockSpeed[];
27 
28+ uint32_t BSP_sys_clk_speed = (uint32_t)_CPUClockSpeed;
29+ uint32_t BSP_pll_ref_clock = (uint32_t)_PLLRefClockSpeed;
30  /*
31   * CPU-space access
32   * The NOP after writing the CACR is there to address the following issue as
33***************
34*** 236,242 ****
35   */
36  void bsp_start( void )
37  {
38!   int i;
39 
40    /*
41     * Set up default exception handler
42--- 241,249 ----
43   */
44  void bsp_start( void )
45  {
46!   int   i;
47!   const char *clk_speed_str;
48!   uint32_t clk_speed, mfd, rfd;
49 
50    /*
51     * Set up default exception handler
52***************
53*** 299,311 ****
54                       MCF5282_CS_CSMR_V;
55    MCF5282_CS2_CSCR = MCF5282_CS_CSCR_PS_16;
56    MCF5282_GPIO_PJPAR |= 0x06;
57- }
58 
59! extern char _CPUClockSpeed[];
60 
61  uint32_t bsp_get_CPU_clock_speed(void)
62  {
63!   return( (uint32_t)_CPUClockSpeed);
64  }
65 
66  /*
67--- 306,374 ----
68                       MCF5282_CS_CSMR_V;
69    MCF5282_CS2_CSCR = MCF5282_CS_CSCR_PS_16;
70    MCF5282_GPIO_PJPAR |= 0x06;
71 
72!   /*
73!    * Hopefully, the UART clock is still correctly set up
74!    * so they can see the printk() output...
75!    */
76!   clk_speed = 0;
77!   printk("Trying to figure out the system clock\n");
78!   printk("Checking ENV variable SYS_CLOCK_SPEED:\n");
79!   if ( (clk_speed_str = bsp_getbenv("SYS_CLOCK_SPEED")) ) {
80!     printk("Found: %s\n", clk_speed_str);
81!       for ( clk_speed = 0, i=0;
82!             clk_speed_str[i] >= '0' && clk_speed_str[i] <= '9';
83!             i++ ) {
84!               clk_speed = 10*clk_speed + clk_speed_str[i] - '0';
85!       }
86!       if ( 0 != clk_speed_str[i] ) {
87!               printk("Not a decimal number; I'm not using this setting\n");
88!               clk_speed = 0;
89!       }
90!   } else {
91!     printk("Not set.\n");
92!   }
93!
94!   if ( 0 == clk_speed )
95!       clk_speed = BSP_sys_clk_speed;
96!
97!   if ( 0 == clk_speed ) {
98!       printk("Using some heuristics to determine clock speed...\n");
99!       printk("Assuming %uHz PLL ref. clock\n", BSP_pll_ref_clock);
100!       if ( 0xf8 != MCF5282_CLOCK_SYNSR ) {
101!         printk("FATAL ERROR: Unexpected SYNSR contents, can't proceed\n");
102!         bsp_sysReset(0);
103!       }
104!       mfd = MCF5282_CLOCK_SYNCR;
105!       rfd = (mfd >>  8) & 7;
106!       mfd = (mfd >> 12) & 7;
107!       /* Check against 'known' cases */
108!       if ( 0 != rfd || (2 != mfd && 3 != mfd) ) {
109!         printk("WARNING: Pll divisor/multiplier has unknown value; \n");
110!         printk("         either your board is not 64MHz or 80Mhz or\n");
111!         printk("         it uses a PLL reference other than 8MHz.\n");
112!         printk("         I'll proceed anyways but you might have to\n");
113!         printk("         reset the board and set uCbootloader ENV\n");
114!         printk("         variable \"SYS_CLOCK_SPEED\".\n");
115!       }
116!       mfd = 2 * (mfd + 2);
117!       /* sysclk = pll_ref * 2 * (MFD + 2) / 2^(rfd) */
118!       printk("PLL multiplier: %u, output divisor: %u\n", mfd, rfd);
119!       clk_speed = (BSP_pll_ref_clock * mfd) >> rfd;
120!   }
121!
122!   if ( 0 == clk_speed ) {
123!       printk("FATAL ERROR: Unable to determine system clock speed\n");
124!       bsp_sysReset(0);
125!   } else {
126!       BSP_sys_clk_speed = clk_speed;
127!       printk("System clock speed: %uHz\n", bsp_get_CPU_clock_speed());
128!   }
129! }
130 
131  uint32_t bsp_get_CPU_clock_speed(void)
132  {
133!   return( BSP_sys_clk_speed );
134  }
135 
136  /*
137Index: c/src/lib/libbsp/m68k/uC5282/startup/linkcmds
138===================================================================
139RCS file: /usr1/CVS/rtems/c/src/lib/libbsp/m68k/uC5282/startup/linkcmds,v
140retrieving revision 1.16
141diff -c -r1.16 linkcmds
142*** c/src/lib/libbsp/m68k/uC5282/startup/linkcmds       16 Sep 2008 22:16:26 -0000      1.16
143--- c/src/lib/libbsp/m68k/uC5282/startup/linkcmds       3 Feb 2011 17:58:21 -0000
144***************
145*** 30,37 ****
146 
147  /*
148   * System clock speed
149   */
150! _CPUClockSpeed = DEFINED(_CPUClockSpeed) ? _CPUClockSpeed : 64000000 ;
151 
152  /*
153   * Location of on-chip devices
154--- 30,46 ----
155 
156  /*
157   * System clock speed
158+  *
159+  * If autodetection of the system clock pased on the PLL ref. clock
160+  * (AFAIK 8MHz for both 64MHz and 80MHz boards) doesn't work then
161+  * you can:
162+  *   - define (nonzero) system clock speed from app- linkflags (or here)
163+  *   - use a uCbootloader env. var: SYS_CLOCK_SPEED to define it.
164+  * You can also redefine the PLL reference clock speed from linkflags
165+  * or here...
166   */
167! _CPUClockSpeed    = DEFINED(_CPUClockSpeed)    ? _CPUClockSpeed : 0 ;
168! _PLLRefClockSpeed = DEFINED(_PLLRefClockSpeed) ? _PLLRefClockSpeed : 8000000;
169 
170  /*
171   * Location of on-chip devices