Ticket #1729: smp-Patch.diff

c/src/lib/libbsp/i386/i386ex/Makefile.am

@@ -63 +63 @@
 # timer
 libbsp_a_SOURCES += timer/timer.c timer/timerisr.S
 
+if HAS_SMP
+libbsp_a_SOURCES += ../../shared/smp/getcpuid.c ../../shared/smp/smp_stub.c
+endif
+
 if HAS_NETWORKING
 network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__ -D_KERNEL
 noinst_PROGRAMS += network.rel

c/src/lib/libbsp/i386/i386ex/configure.ac

@@ -16 +16 @@
 RTEMS_PROG_CCAS
 
 RTEMS_CHECK_NETWORKING
+RTEMS_CHECK_SMP
+
+AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
+AM_CONDITIONAL(HAS_SMP,[test "$rtems_cv_HAS_SMP" = "yes"])
 
 ## if this is an i386, does gas have good code16 support?
 RTEMS_I386_GAS_CODE16
 AM_CONDITIONAL(RTEMS_GAS_CODE16,test "$RTEMS_GAS_CODE16" = "yes")
 
-AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
-
 RTEMS_BSP_CLEANUP_OPTIONS(0, 0)
 
 # Explicitly list all Makefiles here

c/src/lib/libbsp/i386/pc386/Makefile.am

@@ -108 +108 @@
 # ide
 libbsp_a_SOURCES += ide/idecfg.c ide/ide.c
 
+if HAS_SMP
+libbsp_a_SOURCES += ../../shared/smp/getcpuid.c ../../shared/smp/smp_stub.c
+endif
+
 if HAS_NETWORKING
 ne2000_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__
 noinst_PROGRAMS += ne2000.rel

c/src/lib/libbsp/i386/pc386/configure.ac

@@ -17 +17 @@
 RTEMS_PROG_CCAS
 
 RTEMS_CHECK_NETWORKING
+RTEMS_CHECK_SMP
 
 RTEMS_BSPOPTS_SET([USE_COM1_AS_CONSOLE],[*],[0])
 RTEMS_BSPOPTS_HELP([USE_COM1_AS_CONSOLE],
@@ -62 +63 @@
    from Intel and AMD will maintain a constant-rate TSC regardless.
 ])
 
+#define CLOCK_DRIVER_USE_8254 $CLOCK_DRIVER_USE_8254
 RTEMS_BSPOPTS_SET([CLOCK_DRIVER_USE_8254],[*],[0])
 RTEMS_BSPOPTS_HELP([CLOCK_DRIVER_USE_8254],
 [If enabled, the clock driver will use the good old 8254 chip
@@ -78 +80 @@
   AC_MSG_ERROR([pc386 both TSC and 8254 specified for clock driver])
 fi
 
-#define CLOCK_DRIVER_USE_8254 $CLOCK_DRIVER_USE_8254
+RTEMS_BSPOPTS_SET([BSP_HAS_SMP],[*],[1])
+RTEMS_BSPOPTS_HELP([BSP_HAS_SMP],
+[Always defined when on a pc386 to enable the pc386 support for
+ determining the CPU core number in an SMP configuration.])
+
 ## if this is an i386, does gas have good code16 support?
 RTEMS_I386_GAS_CODE16
 AM_CONDITIONAL(RTEMS_GAS_CODE16,[test "$RTEMS_GAS_CODE16" = "yes"])
 
-AM_CONDITIONAL(HAS_NETWORKING,[test "$HAS_NETWORKING" = "yes"])
+
+AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
+AM_CONDITIONAL(HAS_SMP,[test "$rtems_cv_HAS_SMP" = "yes"])
+
 
 AC_SUBST([RTEMS_ROOT],[${rtems_updir}'$(top_builddir)'])
 

c/src/lib/libbsp/i386/pc386/startup/ldsegs.S

@@ -24 +24 @@
 |   ldsegs.s,v 1.4 1996/04/20 16:48:30 joel Exp - go32 BSP
 | With the following copyright notice:
 | **************************************************************************
-| *  COPYRIGHT (c) 1989-1999.
+| *  COPYRIGHT (c) 1989-2011.
 | *  On-Line Applications Research Corporation (OAR).
 | *
 | *  The license and distribution terms for this file may be
@@ -96 +96 @@
 SYM (_load_segments):
 
         lgdt SYM(gdtdesc)
-        lidt SYM(idtdesc)
+        lidt SYM(IDT_Descriptor)
 
         /* Load CS, flush prefetched queue */
         ljmp $0x8, $next_step
@@ -211 +211 @@
 +--------------------------------------------------------------------------*/
 
         .p2align 4
-SYM(idtdesc):
+        PUBLIC(IDT_Descriptor)
+SYM(IDT_Descriptor):
         .word  (256*8 - 1)
         .long  SYM (Interrupt_descriptor_table)
 

c/src/lib/libbsp/i386/shared/irq/irq_asm.S

@@ -4 +4 @@
  *
  *  Copyright (C) 1998 valette@crf.canon.fr
  *
+ *  COPYRIGHT (c) 1989-2011.
+ *  On-Line Applications Research Corporation (OAR).
+ *
  *  The license and distribution terms for this file may be
- *  found in found in the file LICENSE in this distribution or at
+ *  found in the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
  *
  *  $Id: irq_asm.S,v 1.20 2011/01/06 14:34:08 joel Exp $
  */
 
 #include <rtems/asm.h>
+#include <rtems/system.h>
 #include <bspopts.h>
 #include <bsp/irq_asm.h>
 #include <rtems/score/cpu.h>
@@ -140 +144 @@
 ISR_STOP:
 .check_stack_switch:
         movl      esp, ebp                  /* ebp = previous stack pointer */
-
-        movl      $SYM(_Per_CPU_Information), ebx
+#if defined(RTEMS_SMP) && defined(BSP_HAS_SMP)
+        movl     SYM(_Per_CPU_Information_p), ebx
+        call     SYM(rtems_bsp_smp_get_current)
+        mov      (ebx,eax,4), ebx
+#else
+        movl     $SYM(_Per_CPU_Information), ebx
+#endif
 
         /* is this the outermost interrupt? */
         cmpl      $0, PER_CPU_ISR_NEST_LEVEL(ebx)

c/src/lib/libbsp/i386/ts_386ex/Makefile.am

@@ -67 +67 @@
 # timer
 libbsp_a_SOURCES += timer/timer.c timer/timerisr.S
 
+if HAS_SMP
+libbsp_a_SOURCES += ../../shared/smp/getcpuid.c ../../shared/smp/smp_stub.c
+endif
+
 if HAS_NETWORKING
 include_HEADERS += include/wd80x3.h
 

c/src/lib/libbsp/i386/ts_386ex/configure.ac

@@ -16 +16 @@
 RTEMS_PROG_CCAS
 
 RTEMS_CHECK_NETWORKING
+RTEMS_CHECK_SMP
+
+AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
+AM_CONDITIONAL(HAS_SMP,[test "$rtems_cv_HAS_SMP" = "yes"])
 
 ## if this is an i386, does gas have good code16 support?
 RTEMS_I386_GAS_CODE16
 AM_CONDITIONAL(RTEMS_GAS_CODE16,test "$RTEMS_GAS_CODE16" = "yes")
 
-AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
-
 RTEMS_CONFIG_BUILD_SUBDIRS(tools)
 
 # bsp-specific options

c/src/lib/libbsp/sparc/erc32/Makefile.am

@@ -40 +40 @@
     ../../shared/bspstart.c ../../shared/bootcard.c ../../shared/bspinit.c \
     ../../shared/sbrk.c startup/setvec.c startup/spurious.c \
     startup/erc32mec.c startup/boardinit.S startup/bspidle.c
+# ISR Handler
+libbsp_a_SOURCES += ../../sparc/shared/irq_asm.S
 # gnatsupp
 libbsp_a_SOURCES += gnatsupp/gnatsupp.c ../../sparc/shared/gnatcommon.c
 # console
@@ -51 +53 @@
 # timer
 libbsp_a_SOURCES += timer/timer.c
 
+if HAS_SMP
+libbsp_a_SOURCES += ../../shared/smp/getcpuid.c ../../shared/smp/smp_stub.c
+endif
+
 if HAS_NETWORKING
 erc32sonic_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__
 noinst_PROGRAMS += erc32sonic.rel

c/src/lib/libbsp/sparc/erc32/configure.ac

@@ -16 +16 @@
 RTEMS_PROG_CCAS
 
 RTEMS_CHECK_NETWORKING
+RTEMS_CHECK_SMP
 
 AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
+AM_CONDITIONAL(HAS_SMP,[test "$rtems_cv_HAS_SMP" = "yes"])
+
+## This is needed to generate the field offsets of the per CPU 
+## data structure so they can be accessed from assembly code.
+AC_CHECK_SIZEOF([void *])
 
 RTEMS_CONFIG_BUILD_SUBDIRS(tools)
 

c/src/lib/libbsp/sparc/leon2/Makefile.am

@@ -60 +60 @@
     ../../sparc/shared/bspgetworkarea.c ../../shared/bootcard.c \
     ../../shared/sbrk.c startup/setvec.c startup/spurious.c startup/bspidle.c \
     ../../shared/bspinit.c
+# ISR Handler
+libbsp_a_SOURCES += ../../sparc/shared/irq_asm.S
 # gnatsupp
 libbsp_a_SOURCES += gnatsupp/gnatsupp.c ../../sparc/shared/gnatcommon.c
 # console
@@ -97 +99 @@
 # timer
 libbsp_a_SOURCES += timer/timer.c
 
+if HAS_SMP
+libbsp_a_SOURCES += ../../shared/smp/getcpuid.c ../../shared/smp/smp_stub.c
+endif
+
 if HAS_NETWORKING
 noinst_PROGRAMS += leon_smc91111.rel
 leon_smc91111_rel_SOURCES = leon_smc91111/leon_smc91111.c

c/src/lib/libbsp/sparc/leon2/configure.ac

@@ -16 +16 @@
 RTEMS_PROG_CCAS
 
 RTEMS_CHECK_NETWORKING
+RTEMS_CHECK_SMP
 
 AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
+AM_CONDITIONAL(HAS_SMP,[test "$rtems_cv_HAS_SMP" = "yes"])
+
+## This is needed to generate the field offsets of the per CPU 
+## data structure so they can be accessed from assembly code.
+AC_CHECK_SIZEOF([void *])
 
 RTEMS_CONFIG_BUILD_SUBDIRS(tools)
 

c/src/lib/libbsp/sparc/leon3/Makefile.am

@@ -43 +43 @@
     ../../sparc/shared/bspgetworkarea.c ../../shared/sbrk.c startup/setvec.c \
     startup/spurious.c startup/bspidle.S \
     ../../shared/bspinit.c
+# ISR Handler
+libbsp_a_SOURCES += ../../sparc/shared/irq_asm.S
 # gnatsupp
 libbsp_a_SOURCES += gnatsupp/gnatsupp.c ../../sparc/shared/gnatcommon.c
 # amba
@@ -90 +92 @@
 # timer
 libbsp_a_SOURCES += timer/timer.c
 
+if HAS_SMP
+libbsp_a_SOURCES += ../../shared/smp/getcpuid.c ../../shared/smp/smp_stub.c
+endif
+
 if HAS_NETWORKING
 noinst_PROGRAMS += leon_smc91111.rel
 leon_smc91111_rel_SOURCES = leon_smc91111/leon_smc91111.c

c/src/lib/libbsp/sparc/leon3/configure.ac

@@ -16 +16 @@
 RTEMS_PROG_CCAS
 
 RTEMS_CHECK_NETWORKING
+RTEMS_CHECK_SMP
 
 AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
+AM_CONDITIONAL(HAS_SMP,[test "$rtems_cv_HAS_SMP" = "yes"])
+
+## This is needed to generate the field offsets of the per CPU 
+## data structure so they can be accessed from assembly code.
+AC_CHECK_SIZEOF([void *])
 
 RTEMS_CONFIG_BUILD_SUBDIRS(tools)
 
@@ -37 +43 @@
  time spent in the idle task is minimized.  This significantly reduces
  the wall time required to execute the RTEMS test suites.])
 
+RTEMS_BSPOPTS_SET([BSP_LEON3_SMP],[*],[1])
+RTEMS_BSPOPTS_HELP([BSP_LEON3_SMP],
+[Always defined when on a LEON3 to enable the LEON3 support for
+ determining the CPU core number in an SMP configuration.])
+
 RTEMS_BSP_CLEANUP_OPTIONS(0, 0)
 
 # Explicitly list all Makefiles here

c/src/lib/libbsp/sparc/shared/start.S

@@ -7 +7 @@
  *  distribution of the SPARC Instruction Simulator (SIS) found
  *  at ftp://ftp.estec.esa.nl/pub/ws/wsd/erc32.
  *
- *  COPYRIGHT (c) 1989-2006.
+ *  COPYRIGHT (c) 1989-2011.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -18 +18 @@
  */
 
 #include <rtems/asm.h>
+#include <rtems/system.h>
 #include <bspopts.h>
 
+#if defined(RTEMS_SMP) && BSP_LEON3_SMP 
+#define ENABLE_SMP
+#endif
+
 /*
  *  Unexpected trap will halt the processor by forcing it to error state
  */
@@ -221 +226 @@
         nop
         nop
 
+#if defined(ENABLE_SMP)
+        rd      %asr17, %g1
+        srl     %g1, 28, %g1
+        and     %g1, 0xff, %g1                  ! extract cpu id
+        cmp     %g1, 0
+        beq     cpu0
+        nop
+        set     SYM(bsp_ap_stack), %g1          ! set the stack pointer
+        ld      [%g1], %sp
+        mov     %sp, %fp
+        nop
+        set     SYM(bsp_ap_entry), %g1          ! where to start
+        ld      [%g1], %g1
+        call    %g1
+        nop
+cpu0:
+#endif
+
         set     (SYM(rdb_start)), %g6   ! End of RAM
         st      %sp, [%g6]
         sub     %sp, 4, %sp             ! stack starts at end of RAM - 4
@@ -340 +363 @@
         ta      0                       ! Halt if _main returns ...
         nop
 
+#if defined(ENABLE_SMP)
+        .common bsp_ap_stack, 4, 4
+        .common bsp_ap_entry, 4, 4
+#endif
+
+
 /* end of file */

cpukit/configure.ac

@@ -141 +141 @@
   RTEMS_CHECK_MULTIPROCESSING
 RTEMS_CHECK_POSIX_API
 RTEMS_CHECK_NETWORKING
+RTEMS_CHECK_SMP
 
 rtems_major=`echo _RTEMS_VERSION | sed "s/\..*//"`
 rtems_minor=`echo _RTEMS_VERSION | sed "s/[[0-9]][[0-9]]*\.//;s/\..*//"`
@@ -172 +173 @@
   [1],
   [if posix api is supported])
 
+RTEMS_CPUOPT([RTEMS_SMP],
+  [test x"$RTEMS_HAS_SMP" = xyes],
+  [1],
+  [if SMP is enabled])
+
 RTEMS_CPUOPT([RTEMS_NETWORKING],
   [test x"$rtems_cv_HAS_NETWORKING" = xyes],
   [1],
@@ -296 +302 @@
 AM_CONDITIONAL(NEWLIB,test x"$RTEMS_USE_NEWLIB" = x"yes")
 
 AM_CONDITIONAL(HAS_MP,test x"$enable_multiprocessing" = x"yes" )
+AM_CONDITIONAL(HAS_SMP,[test "$RTEMS_HAS_SMP" = "yes"])
 
 AM_CONDITIONAL(HAS_PTHREADS,test x"$rtems_cv_HAS_POSIX_API" = x"yes")
 AM_CONDITIONAL(LIBNETWORKING,test x"$rtems_cv_HAS_NETWORKING" = x"yes")

cpukit/sapi/include/confdefs.h

@@ -26 +26 @@
  */
 
 /*
- *  COPYRIGHT (c) 1989-2010.
+ *  COPYRIGHT (c) 1989-2011.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -174 +174 @@
   extern int rtems_telnetd_maximum_ptys;
 #endif
 
+#if defined(RTEMS_SMP)
+  /*
+   *  If configured for SMP, then we need to know the maximum CPU cores.
+   */
+  #if !defined(CONFIGURE_SMP_APP)
+    #if !defined(CONFIGURE_SMP_CPUS) 
+      #define CONFIGURE_SMP_CPUS 1
+    #endif
+  #else
+    #if !defined(CONFIGURE_SMP_CPUS) 
+      #error "CONFIGURE_SMP_CPUS not specified for SMP Application"
+    #endif
+  #endif
+#endif
+
 /*
  *  Filesystems and Mount Table Configuration.
  *
@@ -1836 +1851 @@
   _Configure_Object_RAM(1, sizeof(API_Mutex_Control))
 
 /**
- *  This defines the amount of memory reserved for the IDLE task
- *  control structures and stack.
+ *  This defines the formula used to compute the amount of memory
+ *  reserved for IDLE task control structures and stacks.
+ */
+#define CONFIGURE_IDLE_TASKS(_count) \
+    (CONFIGURE_MEMORY_FOR_TASKS(_count, 0) + \
+      _count * _Configure_From_workspace( \
+       (CONFIGURE_IDLE_TASK_STACK_SIZE - CONFIGURE_MINIMUM_TASK_STACK_SIZE)))
+
+/**
+ *  This calculates the amount of memory reserved for the IDLE tasks.
+ *  In an SMP system, each CPU core has its own idle task.
  */
-#define CONFIGURE_MEMORY_FOR_IDLE_TASK \
-    (CONFIGURE_MEMORY_FOR_TASKS(1, 0) + \
-     (CONFIGURE_IDLE_TASK_STACK_SIZE - CONFIGURE_MINIMUM_TASK_STACK_SIZE))
+#if defined(RTEMS_SMP)
+  #define CONFIGURE_MEMORY_FOR_IDLE_TASK \
+          CONFIGURE_IDLE_TASKS(CONFIGURE_SMP_CPUS)
+#else
+  #define CONFIGURE_MEMORY_FOR_IDLE_TASK \
+          CONFIGURE_IDLE_TASKS(1)
+#endif
 
 /**
  *  This macro accounts for general RTEMS system overhead.
@@ -1929 +1957 @@
    CONFIGURE_MEMORY_FOR_USER_EXTENSIONS(CONFIGURE_MAXIMUM_USER_EXTENSIONS) \
   )
 
+#if defined(RTEMS_SMP)
+  #define CONFIGURE_MEMORY_FOR_SMP \
+     (_Configure_From_workspace( \
+         CONFIGURE_SMP_CPUS * sizeof(Per_CPU_Control)) + \
+      _Configure_From_workspace( \
+         CONFIGURE_SMP_CPUS * sizeof(Per_CPU_Control *)) + \
+      (CONFIGURE_SMP_CPUS * \
+        _Configure_From_workspace( CONFIGURE_INTERRUPT_STACK_SIZE )) \
+     )
+#else
+  #define CONFIGURE_MEMORY_FOR_SMP 0
+#endif
+
 #if defined(CONFIGURE_CONFDEFS_DEBUG) && defined(CONFIGURE_INIT)
   /**
    *  This is a debug mechanism, so if you need to, the executable will
@@ -2043 +2084 @@
    CONFIGURE_MEMORY_FOR_CLASSIC + \
    CONFIGURE_MEMORY_FOR_POSIX + \
    (CONFIGURE_MAXIMUM_POSIX_THREADS * CONFIGURE_MINIMUM_TASK_STACK_SIZE ) + \
-   (CONFIGURE_MAXIMUM_GOROUTINES * CONFIGURE_MINIMUM_TASK_STACK_SIZE ) + \
+   (CONFIGURE_MAXIMUM_GOROUTINES * CONFIGURE_MINIMUM_TASK_STACK_SIZE) + \
    CONFIGURE_INITIALIZATION_THREADS_STACKS + \
    CONFIGURE_MEMORY_FOR_STATIC_EXTENSIONS + \
    CONFIGURE_MEMORY_FOR_MP + \
+   CONFIGURE_MEMORY_FOR_SMP + \
    CONFIGURE_MESSAGE_BUFFER_MEMORY + \
    (CONFIGURE_MEMORY_OVERHEAD * 1024) + \
    (CONFIGURE_EXTRA_TASK_STACKS) + (CONFIGURE_ADA_TASKS_STACK) \
@@ -2149 +2191 @@
 
 #endif /* CONFIGURE_HAS_OWN_CONFIGURATION_TABLE */
 
+#if defined(RTEMS_SMP)
+  /*
+   *  Instantiate the variable which specifies the number of CPUs
+   *  in an SMP configuration.
+   */
+  #if defined(CONFIGURE_INIT)
+    uint32_t rtems_smp_maximum_cpus = CONFIGURE_SMP_CPUS;
+  #else
+    extern uint32_t rtems_smp_maximum_cpus;
+  #endif
+#endif
+
 /*
  *  If the user has configured a set of Classic API Initialization Tasks,
  *  then we need to install the code that runs that loop.

cpukit/sapi/src/exinit.c

@@ -1 +1 @@
 /*
  *  Initialization Manager
  *
- *  COPYRIGHT (c) 1989-2008.
+ *  COPYRIGHT (c) 1989-2011.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -57 +57 @@
   #include <rtems/posix/posixapi.h>
 #endif
 
+#if defined(RTEMS_SMP)
+  #include <rtems/bspsmp.h>
+#endif
+
 Objects_Information *_Internal_Objects[ OBJECTS_INTERNAL_CLASSES_LAST + 1 ];
 
 void rtems_initialize_data_structures(void)
@@ -114 +118 @@
    */
   _Workspace_Handler_initialization();
 
+  #if defined(RTEMS_SMP)
+    per_cpu_initialize();
+  #endif
+
   _User_extensions_Handler_initialization();
   _ISR_Handler_initialization();
 
@@ -150 +158 @@
     _POSIX_API_Initialize();
   #endif
 
+  /*
+   * Discover and initialize the secondary cores in an SMP system.
+   */
+  #if defined(RTEMS_SMP)
+    rtems_smp_number_of_cpus = rtems_bsp_smp_initialize(rtems_smp_maximum_cpus);
+  #endif
+
   _System_state_Set( SYSTEM_STATE_BEFORE_MULTITASKING );
 
   /*

cpukit/score/Makefile.am

@@ -12 +12 @@
 include_rtemsdir = $(includedir)/rtems
 
 include_rtems_HEADERS = include/rtems/debug.h include/rtems/system.h \
-    include/rtems/seterr.h
+    include/rtems/seterr.h include/rtems/bspsmp.h
 
 include_rtems_scoredir = $(includedir)/rtems/score
 
@@ -34 +34 @@
     include/rtems/score/timestamp64.h include/rtems/score/tod.h \
     include/rtems/score/tqdata.h include/rtems/score/userext.h \
     include/rtems/score/watchdog.h include/rtems/score/wkspace.h \
-    include/rtems/score/cpuopts.h include/rtems/score/basedefs.h
+    include/rtems/score/cpuopts.h include/rtems/score/basedefs.h \
+    include/rtems/score/lock.h
 
 if HAS_PTHREADS
 include_rtems_score_HEADERS += include/rtems/score/corespinlock.h \
@@ -86 +87 @@
 libscore_a_SOURCES += src/mpci.c src/objectmp.c src/threadmp.c
 endif
 
+libscore_a_SOURCES += src/smp.c src/lock.c
+
 ## CORE_APIMUTEX_C_FILES
 libscore_a_SOURCES += src/apimutex.c src/apimutexallocate.c \
     src/apimutexlock.c src/apimutexunlock.c

cpukit/score/preinstall.am

@@ -30 +30 @@
         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/seterr.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/seterr.h
 
+$(PROJECT_INCLUDE)/rtems/bspsmp.h: include/rtems/bspsmp.h $(PROJECT_INCLUDE)/rtems/$(dirstamp)
+        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/bspsmp.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/bspsmp.h
+
 $(PROJECT_INCLUDE)/rtems/score/$(dirstamp):
         @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score
         @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
@@ -183 +187 @@
         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/basedefs.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/basedefs.h
 
+$(PROJECT_INCLUDE)/rtems/score/lock.h: include/rtems/score/lock.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/lock.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/lock.h
+
 if HAS_PTHREADS
 $(PROJECT_INCLUDE)/rtems/score/corespinlock.h: include/rtems/score/corespinlock.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/corespinlock.h

cpukit/score/cpu/i386/rtems/score/cpu.h

@@ -6 +6 @@
  *  This include file contains information pertaining to the Intel
  *  i386 processor.
  *
- *  COPYRIGHT (c) 1989-2008.
+ *  COPYRIGHT (c) 1989-2011.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -270 +270 @@
 /* variables */
 
 SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
-SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
-SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
 
 #endif /* ASM */
 
@@ -437 +435 @@
 #define _CPU_Context_Restart_self( _the_context ) \
    _CPU_Context_restore( (_the_context) );
 
+#if defined(RTEMS_SMP)
+  #define _CPU_Context_switch_to_first_task_smp( _the_context ) \
+     _CPU_Context_restore( (_the_context) );
+#endif
+
 #define _CPU_Context_Fp_start( _base, _offset ) \
    ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
 

cpukit/score/cpu/sparc/cpu_asm.S

@@ -4 +4 @@
  *  in an specific CPU port of RTEMS.  These algorithms must be implemented
  *  in assembly language.
  *
- *  COPYRIGHT (c) 1989-2010.
+ *  COPYRIGHT (c) 1989-2011.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -319 +319 @@
  *
  *  NOTE: It is unnecessary to reload some registers.
  */
-
         .align 4
         PUBLIC(_CPU_Context_restore)
 SYM(_CPU_Context_restore):
@@ -327 +326 @@
         rd      %psr, %o2
         ba      SYM(_CPU_Context_restore_heir)
         mov     %i0, %o1                      ! in the delay slot
+        .align 4
 
+#if defined(RTEMS_SMP)
 /*
- *  void _ISR_Handler()
- *
- *  This routine provides the RTEMS interrupt management.
- *
- *  We enter this handler from the 4 instructions in the trap table with
- *  the following registers assumed to be set as shown:
- *
- *    l0 = PSR
- *    l1 = PC
- *    l2 = nPC
- *    l3 = trap type
+ *  void _CPU_Context_switch_to_first_task_smp(
+ *    Context_Control *new_context
+ *  )
  *
- *  NOTE: By an executive defined convention, trap type is between 0 and 255 if
- *        it is an asynchonous trap and 256 and 511 if it is synchronous.
+ *  This routine is only used to switch to the first task on a
+ *  secondary core in an SMP configuration.  We do not need to
+ *  flush all the windows and, in fact, this can be dangerous
+ *  as they may or may not be initialized properly.  So we just
+ *  reinitialize the PSR and WIM.
  */
+        PUBLIC(_CPU_Context_switch_to_first_task_smp)
+SYM(_CPU_Context_switch_to_first_task_smp):
+        save    %sp, -CPU_MINIMUM_STACK_FRAME_SIZE, %sp
 
-        .align 4
-        PUBLIC(_ISR_Handler)
-SYM(_ISR_Handler):
-        /*
-         *  Fix the return address for synchronous traps.
-         */
-
-        andcc   %l3, SPARC_SYNCHRONOUS_TRAP_BIT_MASK, %g0
-                                      ! Is this a synchronous trap?
-        be,a    win_ovflow            ! No, then skip the adjustment
-        nop                           ! DELAY
-        mov     %l1, %l6              ! save trapped pc for debug info
-        mov     %l2, %l1              ! do not return to the instruction
-        add     %l2, 4, %l2           ! indicated
-
-win_ovflow:
-        /*
-         *  Save the globals this block uses.
-         *
-         *  These registers are not restored from the locals.  Their contents
-         *  are saved directly from the locals into the ISF below.
-         */
-
-        mov     %g4, %l4                 ! save the globals this block uses
-        mov     %g5, %l5
-
-        /*
-         *  When at a "window overflow" trap, (wim == (1 << cwp)).
-         *  If we get here like that, then process a window overflow.
-         */
-
-        rd      %wim, %g4
-        srl     %g4, %l0, %g5            ! g5 = win >> cwp ; shift count and CWP
-                                         !   are LS 5 bits ; how convenient :)
-        cmp     %g5, 1                   ! Is this an invalid window?
-        bne     dont_do_the_window       ! No, then skip all this stuff
-        ! we are using the delay slot
-
-        /*
-         *  The following is same as a 1 position right rotate of WIM
-         */
-
-        srl     %g4, 1, %g5              ! g5 = WIM >> 1
-        sll     %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %g4
-                                         ! g4 = WIM << (Number Windows - 1)
-        or      %g4, %g5, %g4            ! g4 = (WIM >> 1) |
-                                         !      (WIM << (Number Windows - 1))
-
-        /*
-         *  At this point:
-         *
-         *    g4 = the new WIM
-         *    g5 is free
-         */
-
-        /*
-         *  Since we are tinkering with the register windows, we need to
-         *  make sure that all the required information is in global registers.
-         */
-
-        save                          ! Save into the window
-        wr      %g4, 0, %wim          ! WIM = new WIM
-        nop                           ! delay slots
-        nop
-        nop
-
-        /*
-         *  Now save the window just as if we overflowed to it.
-         */
-
-        std     %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET]
-        std     %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET]
-        std     %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET]
-        std     %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET]
-
-        std     %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET]
-        std     %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET]
-        std     %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET]
-        std     %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET]
-
-        restore
-        nop
-
-dont_do_the_window:
-        /*
-         *  Global registers %g4 and %g5 are saved directly from %l4 and
-         *  %l5 directly into the ISF below.
-         */
-
-save_isf:
-
-        /*
-         *  Save the state of the interrupted task -- especially the global
-         *  registers -- in the Interrupt Stack Frame.  Note that the ISF
-         *  includes a regular minimum stack frame which will be used if
-         *  needed by register window overflow and underflow handlers.
-         *
-         *  REGISTERS SAME AS AT _ISR_Handler
-         */
-
-        sub     %fp, CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE, %sp
-                                               ! make space for ISF
-
-        std     %l0, [%sp + ISF_PSR_OFFSET]    ! save psr, PC
-        st      %l2, [%sp + ISF_NPC_OFFSET]    ! save nPC
-        st      %g1, [%sp + ISF_G1_OFFSET]     ! save g1
-        std     %g2, [%sp + ISF_G2_OFFSET]     ! save g2, g3
-        std     %l4, [%sp + ISF_G4_OFFSET]     ! save g4, g5 -- see above
-        std     %g6, [%sp + ISF_G6_OFFSET]     ! save g6, g7
-
-        std     %i0, [%sp + ISF_I0_OFFSET]     ! save i0, i1
-        std     %i2, [%sp + ISF_I2_OFFSET]     ! save i2, i3
-        std     %i4, [%sp + ISF_I4_OFFSET]     ! save i4, i5
-        std     %i6, [%sp + ISF_I6_FP_OFFSET]  ! save i6/fp, i7
-
-        rd      %y, %g1
-        st      %g1, [%sp + ISF_Y_OFFSET]      ! save y
-        st      %l6, [%sp + ISF_TPC_OFFSET]    ! save real trapped pc
-
-        mov     %sp, %o1                       ! 2nd arg to ISR Handler
-
-        /*
-         *  Increment ISR nest level and Thread dispatch disable level.
-         *
-         *  Register usage for this section:
-         *
-         *    l4 = _Thread_Dispatch_disable_level pointer
-         *    l5 = per cpu info pointer
-         *    l6 = _Thread_Dispatch_disable_level value
-         *    l7 = _ISR_Nest_level value
-         *
-         *  NOTE: It is assumed that l4 - l7 will be preserved until the ISR
-         *        nest and thread dispatch disable levels are unnested.
-         */
-
-        sethi    %hi(SYM(_Thread_Dispatch_disable_level)), %l4
-        ld       [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))], %l6
-
-        sethi    %hi(_Per_CPU_Information), %l5
-        add      %l5, %lo(_Per_CPU_Information), %l5
-
-        ld       [%l5 + PER_CPU_ISR_NEST_LEVEL], %l7
-
-        add      %l6, 1, %l6
-        st       %l6, [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))]
-
-        add      %l7, 1, %l7
-        st       %l7, [%l5 + PER_CPU_ISR_NEST_LEVEL]
-
-        /*
-         *  If ISR nest level was zero (now 1), then switch stack.
-         */
-
-        mov      %sp, %fp
-        subcc    %l7, 1, %l7             ! outermost interrupt handler?
-        bnz      dont_switch_stacks      ! No, then do not switch stacks
-
-        nop
-        ld       [%l5 + PER_CPU_INTERRUPT_STACK_HIGH], %sp
-
-dont_switch_stacks:
-        /*
-         *  Make sure we have a place on the stack for the window overflow
-         *  trap handler to write into.  At this point it is safe to
-         *  enable traps again.
-         */
-
-        sub      %sp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp
-
-        /*
-         *  Check if we have an external interrupt (trap 0x11 - 0x1f). If so,
-         *  set the PIL in the %psr to mask off interrupts with lower priority.
-         *  The original %psr in %l0 is not modified since it will be restored
-         *  when the interrupt handler returns.
-         */
-
-        mov      %l0, %g5
-        and      %l3, 0x0ff, %g4
-
-/* This is a fix for ERC32 with FPU rev.B or rev.C */
-
-#if defined(FPU_REVB)
-
-
-        subcc    %g4, 0x08, %g0
-        be       fpu_revb
-        subcc    %g4, 0x11, %g0
-        bl       dont_fix_pil
-        subcc    %g4, 0x1f, %g0
-        bg       dont_fix_pil
-        sll      %g4, 8, %g4
-        and      %g4, SPARC_PSR_PIL_MASK, %g4
-        andn     %l0, SPARC_PSR_PIL_MASK, %g5
-        or       %g4, %g5, %g5
-        srl      %l0, 12, %g4
-        andcc    %g4, 1, %g0
-        be       dont_fix_pil
-        nop
-        ba,a     enable_irq
-
-
-fpu_revb:
-        srl      %l0, 12, %g4   ! check if EF is set in %psr
-        andcc    %g4, 1, %g0
-        be       dont_fix_pil   ! if FPU disabled than continue as normal
-        and      %l3, 0xff, %g4
-        subcc    %g4, 0x08, %g0
-        bne      enable_irq     ! if not a FPU exception then do two fmovs
-        set      __sparc_fq, %g4
-        st       %fsr, [%g4]    ! if FQ is not empty and FQ[1] = fmovs
-        ld       [%g4], %g4     ! than this is bug 3.14
-        srl      %g4, 13, %g4
-        andcc    %g4, 1, %g0
-        be       dont_fix_pil
-        set      __sparc_fq, %g4
-        std      %fq, [%g4]
-        ld       [%g4+4], %g4
-        set      0x81a00020, %g5
-        subcc    %g4, %g5, %g0
-        bne,a    dont_fix_pil2
-        wr       %l0, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS ****
-        ba,a     simple_return
-        
-enable_irq:
-        or       %g5, SPARC_PSR_PIL_MASK, %g4
-        wr       %g4, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS ****
-        nop; nop; nop
-        fmovs    %f0, %f0
-        ba       dont_fix_pil
-        fmovs    %f0, %f0
-
-        .data
-        .global __sparc_fq
-        .align 8
-__sparc_fq:
-        .word 0,0
-
-        .text
-/* end of ERC32 FPU rev.B/C fix */
-
-#else
-
-        subcc    %g4, 0x11, %g0
-        bl       dont_fix_pil
-        subcc    %g4, 0x1f, %g0
-        bg       dont_fix_pil
-        sll      %g4, 8, %g4
-        and      %g4, SPARC_PSR_PIL_MASK, %g4
-        andn     %l0, SPARC_PSR_PIL_MASK, %g5
-        ba       pil_fixed
-        or       %g4, %g5, %g5
+        mov     %psr, %g1               ! Initialize WIM
+        add     %g1, 1, %g2
+        and     %g2, 0x7, %g2
+        set     1, %g3
+        sll     %g3, %g2, %g3
+        mov     %g3, %wim
+        ba      done_flushing
+        mov     %i0, %o1                      ! in the delay slot
 #endif
 
-dont_fix_pil:
-        or       %g5, SPARC_PSR_PIL_MASK, %g5
-pil_fixed:
-        wr       %g5, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS ****
-dont_fix_pil2:
-
-        /*
-         *  Vector to user's handler.
-         *
-         *  NOTE: TBR may no longer have vector number in it since
-         *        we just enabled traps.  It is definitely in l3.
-         */
-
-        sethi    %hi(SYM(_ISR_Vector_table)), %g4
-        ld       [%g4+%lo(SYM(_ISR_Vector_table))], %g4
-        and      %l3, 0xFF, %g5         ! remove synchronous trap indicator
-        sll      %g5, 2, %g5            ! g5 = offset into table
-        ld       [%g4 + %g5], %g4       ! g4 = _ISR_Vector_table[ vector ]
-
-
-                                        ! o1 = 2nd arg = address of the ISF
-                                        !   WAS LOADED WHEN ISF WAS SAVED!!!
-        mov      %l3, %o0               ! o0 = 1st arg = vector number
-        call     %g4, 0
-        nop                             ! delay slot
-
-        /*
-         *  Redisable traps so we can finish up the interrupt processing.
-         *  This is a VERY conservative place to do this.
-         *
-         *  NOTE: %l0 has the PSR which was in place when we took the trap.
-         */
-
-        mov      %l0, %psr             ! **** DISABLE TRAPS ****
-        nop; nop; nop
-
-        /*
-         *  Decrement ISR nest level and Thread dispatch disable level.
-         *
-         *  Register usage for this section:
-         *
-         *    l4 = _Thread_Dispatch_disable_level pointer
-         *    l5 = _ISR_Nest_level pointer
-         *    l6 = _Thread_Dispatch_disable_level value
-         *    l7 = _ISR_Nest_level value
-         */
-
-        sub      %l6, 1, %l6
-        st       %l6, [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))]
-
-        st       %l7, [%l5 + PER_CPU_ISR_NEST_LEVEL]
-
-        /*
-         *  If dispatching is disabled (includes nested interrupt case),
-         *  then do a "simple" exit.
-         */
-
-        orcc     %l6, %g0, %g0   ! Is dispatching disabled?
-        bnz      simple_return   ! Yes, then do a "simple" exit
-        ! NOTE: Use the delay slot
-        sethi    %hi(SYM(_CPU_ISR_Dispatch_disable)), %l6
-
-        ! Are we dispatching from a previous ISR in the interrupted thread?
-        ld       [%l6 + %lo(SYM(_CPU_ISR_Dispatch_disable))], %l7
-        orcc     %l7, %g0, %g0   ! Is this thread already doing an ISR?
-        bnz      simple_return   ! Yes, then do a "simple" exit
-        nop
-
-
-        /*
-         *  If a context switch is necessary, then do fudge stack to
-         *  return to the interrupt dispatcher.
-         */
-
-        ldub     [%l5 + PER_CPU_DISPATCH_NEEDED], %l5
-
-        orcc     %l5, %g0, %g0   ! Is thread switch necessary?
-        bz       simple_return   ! no, then do a simple return
-        nop
-
-        /*
-         *  Invoke interrupt dispatcher.
-         */
-
-        PUBLIC(_ISR_Dispatch)
-SYM(_ISR_Dispatch):
-        ! Set ISR dispatch nesting prevention flag
-        mov      1,%l6
-        sethi    %hi(SYM(_CPU_ISR_Dispatch_disable)), %l5
-        st       %l6,[%l5 + %lo(SYM(_CPU_ISR_Dispatch_disable))]
-
-        /*
-         *  The following subtract should get us back on the interrupted
-         *  tasks stack and add enough room to invoke the dispatcher.
-         *  When we enable traps, we are mostly back in the context
-         *  of the task and subsequent interrupts can operate normally.
-         */
-
-        sub      %fp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp
-
-        or      %l0, SPARC_PSR_ET_MASK, %l7    ! l7 = PSR with ET=1
-        mov     %l7, %psr                      !  **** ENABLE TRAPS ****
-        nop
-        nop
-        nop
-isr_dispatch:
-        call    SYM(_Thread_Dispatch), 0
-        nop
-
-        /*
-         *  We invoked _Thread_Dispatch in a state similar to the interrupted
-         *  task.  In order to safely be able to tinker with the register
-         *  windows and get the task back to its pre-interrupt state,
-         *  we need to disable interrupts disabled so we can safely tinker
-         *  with the register windowing.  In particular, the CWP in the PSR
-         *  is fragile during this period. (See PR578.)
-         */
-        mov     2,%g1                           ! syscall (disable interrupts)
-        ta      0                               ! syscall (disable interrupts)
-
-        /*
-         *  While we had ISR dispatching disabled in this thread,
-         *  did we miss anything.  If so, then we need to do another
-         *  _Thread_Dispatch before leaving this ISR Dispatch context.
-         */
-
-        sethi    %hi(_Per_CPU_Information), %l5
-        add      %l5, %lo(_Per_CPU_Information), %l5
-
-        ldub     [%l5 + PER_CPU_DISPATCH_NEEDED], %l7
-
-        orcc     %l7, %g0, %g0    ! Is thread switch necesary?
-        bz       allow_nest_again ! No, then clear out and return
-        nop
-
-        ! Yes, then invoke the dispatcher
-dispatchAgain:
-        mov     3,%g1                           ! syscall (enable interrupts)
-        ta      0                               ! syscall (enable interrupts)
-        ba      isr_dispatch
-        nop
-
-allow_nest_again:
-
-        ! Zero out ISR stack nesting prevention flag
-        sethi    %hi(SYM(_CPU_ISR_Dispatch_disable)), %l5
-        st       %g0,[%l5 + %lo(SYM(_CPU_ISR_Dispatch_disable))]
-
-        /*
-         *  The CWP in place at this point may be different from
-         *  that which was in effect at the beginning of the ISR if we
-         *  have been context switched between the beginning of this invocation
-         *  of _ISR_Handler and this point.  Thus the CWP and WIM should
-         *  not be changed back to their values at ISR entry time.  Any
-         *  changes to the PSR must preserve the CWP.
-         */
-
-simple_return:
-        ld      [%fp + ISF_Y_OFFSET], %l5      ! restore y
-        wr      %l5, 0, %y
-
-        ldd     [%fp + ISF_PSR_OFFSET], %l0    ! restore psr, PC
-        ld      [%fp + ISF_NPC_OFFSET], %l2    ! restore nPC
-        rd      %psr, %l3
-        and     %l3, SPARC_PSR_CWP_MASK, %l3   ! want "current" CWP
-        andn    %l0, SPARC_PSR_CWP_MASK, %l0   ! want rest from task
-        or      %l3, %l0, %l0                  ! install it later...
-        andn    %l0, SPARC_PSR_ET_MASK, %l0
-
-        /*
-         *  Restore tasks global and out registers
-         */
-
-        mov    %fp, %g1
-
-                                              ! g1 is restored later
-        ldd     [%fp + ISF_G2_OFFSET], %g2    ! restore g2, g3
-        ldd     [%fp + ISF_G4_OFFSET], %g4    ! restore g4, g5
-        ldd     [%fp + ISF_G6_OFFSET], %g6    ! restore g6, g7
-
-        ldd     [%fp + ISF_I0_OFFSET], %i0    ! restore i0, i1
-        ldd     [%fp + ISF_I2_OFFSET], %i2    ! restore i2, i3
-        ldd     [%fp + ISF_I4_OFFSET], %i4    ! restore i4, i5
-        ldd     [%fp + ISF_I6_FP_OFFSET], %i6 ! restore i6/fp, i7
-
-        /*
-         *  Registers:
-         *
-         *   ALL global registers EXCEPT G1 and the input registers have
-         *   already been restored and thuse off limits.
-         *
-         *   The following is the contents of the local registers:
-         *
-         *     l0 = original psr
-         *     l1 = return address (i.e. PC)
-         *     l2 = nPC
-         *     l3 = CWP
-         */
-
-        /*
-         *  if (CWP + 1) is an invalid window then we need to reload it.
-         *
-         *  WARNING: Traps should now be disabled
-         */
-
-        mov     %l0, %psr                  !  **** DISABLE TRAPS ****
-        nop
-        nop
-        nop
-        rd      %wim, %l4
-        add     %l0, 1, %l6                ! l6 = cwp + 1
-        and     %l6, SPARC_PSR_CWP_MASK, %l6 ! do the modulo on it
-        srl     %l4, %l6, %l5              ! l5 = win >> cwp + 1 ; shift count
-                                           !  and CWP are conveniently LS 5 bits
-        cmp     %l5, 1                     ! Is tasks window invalid?
-        bne     good_task_window
-
-        /*
-         *  The following code is the same as a 1 position left rotate of WIM.
-         */
-
-        sll     %l4, 1, %l5                ! l5 = WIM << 1
-        srl     %l4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %l4
-                                           ! l4 = WIM >> (Number Windows - 1)
-        or      %l4, %l5, %l4              ! l4 = (WIM << 1) |
-                                           !      (WIM >> (Number Windows - 1))
-
-        /*
-         *  Now restore the window just as if we underflowed to it.
-         */
-
-        wr      %l4, 0, %wim               ! WIM = new WIM
-        nop                                ! must delay after writing WIM
-        nop
-        nop
-        restore                            ! now into the tasks window
-
-        ldd     [%g1 + CPU_STACK_FRAME_L0_OFFSET], %l0
-        ldd     [%g1 + CPU_STACK_FRAME_L2_OFFSET], %l2
-        ldd     [%g1 + CPU_STACK_FRAME_L4_OFFSET], %l4
-        ldd     [%g1 + CPU_STACK_FRAME_L6_OFFSET], %l6
-        ldd     [%g1 + CPU_STACK_FRAME_I0_OFFSET], %i0
-        ldd     [%g1 + CPU_STACK_FRAME_I2_OFFSET], %i2
-        ldd     [%g1 + CPU_STACK_FRAME_I4_OFFSET], %i4
-        ldd     [%g1 + CPU_STACK_FRAME_I6_FP_OFFSET], %i6
-                                           ! reload of sp clobbers ISF
-        save                               ! Back to ISR dispatch window
-
-good_task_window:
-
-        mov     %l0, %psr                  !  **** DISABLE TRAPS ****
-        nop; nop; nop
-                                           !  and restore condition codes.
-        ld      [%g1 + ISF_G1_OFFSET], %g1 ! restore g1
-        jmp     %l1                        ! transfer control and
-        rett    %l2                        ! go back to tasks window
-
 /* end of file */

cpukit/score/cpu/sparc/rtems/score/cpu.h

@@ -6 +6 @@
  *  This include file contains information pertaining to the port of
  *  the executive to the SPARC processor.
  *
- *  COPYRIGHT (c) 1989-2006.
+ *  COPYRIGHT (c) 1989-2011.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -927 +927 @@
   Context_Control *new_context
 ) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
 
+#if defined(RTEMS_SMP)
+/*
+ *  _CPU_Context_switch_to_first_task_smp
+ *
+ *  This routine is only used to switch to the first task on a
+ *  secondary core in an SMP configuration.  We do not need to
+ *  flush all the windows and, in fact, this can be dangerous
+ *  as they may or may not be initialized properly.
+ */
+void _CPU_Context_switch_to_first_task_smp(
+  Context_Control *new_context
+);
+#endif
+
 /*
  *  _CPU_Context_save_fp
  *

cpukit/score/include/rtems/score/context.h

@@ -5 +5 @@
  */
 
 /*
- *  COPYRIGHT (c) 1989-2006.
+ *  COPYRIGHT (c) 1989-2011.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -45 +45 @@
 
 /**
  *  @brief Initialize Context Area
+ *
  *  This routine initializes @a _the_context such that the stack
  *  pointer, interrupt level, and entry point are correct for the
  *  thread's initial state.
@@ -100 +101 @@
 #define _Context_Restart_self( _the_context ) \
    _CPU_Context_Restart_self( _the_context )
 
+#if defined(RTEMS_SMP)
+/*
+ *  @brief Switch to First Task on Secondary Core
+ *
+ *  This routine is only used to switch to the first task on a
+ *  secondary core in an SMP configuration.  Since the switch
+ *  to the first task is done from an interrupt handler, this
+ *  may be different from simply restarting the currently running
+ *  task.
+ *
+ *  @param[in] _the_context is the context of the first thread to
+ *             run on this core
+ */
+#define _Context_Switch_to_first_task_smp( _the_context ) \
+   _CPU_Context_switch_to_first_task_smp( _the_context )
+#endif
+
 /**
  *  @brief Return Starting Address of Floating Point Context
  *

cpukit/score/include/rtems/score/percpu.h

@@ -1 +1 @@
 /**
- *  @file  rtems/score/percpu.h
+ *  @file  rtems/percpu.h
  *
  *  This include file defines the per CPU information required
  *  by RTEMS.
  */
 
 /*
- *  COPYRIGHT (c) 1989-2010.
+ *  COPYRIGHT (c) 1989-2011.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
  *  found in the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
  *
- *  $Id: percpu.h,v 1.4 2010/07/30 18:53:06 joel Exp $
+ *  $Id$
  */
 
 #ifndef _RTEMS_PERCPU_H
@@ -23 +23 @@
 
 #ifdef ASM
   #include <rtems/asm.h>
+#else
+  #if defined(RTEMS_SMP)
+    #include <rtems/score/lock.h>
+  #endif
 #endif
 
 /**
@@ -41 +45 @@
 #endif
 
 #ifndef ASM
+#ifndef __THREAD_CONTROL_DEFINED__
+#define __THREAD_CONTROL_DEFINED__
+typedef struct Thread_Control_struct Thread_Control;
+#endif
+
+#if (CPU_ALLOCATE_INTERRUPT_STACK == FALSE) && defined(RTEMS_SMP)
+  #error "RTEMS must allocate per CPU interrupt stack for SMP"
+#endif
+ 
+/**
+ *  This defines the constant used to indicate that the cpu code is in
+ *  its initial powered up start.
+ */
+#define RTEMS_BSP_SMP_CPU_INITIAL_STATE 1
 
 /**
- * This forward defines the Thread Control Block structure.
+ *  This defines the constant used to indicate that the cpu code has
+ *  completed basic initialization and awaits further commands.
  */
-typedef struct Thread_Control_struct Thread_Control;
+#define RTEMS_BSP_SMP_CPU_INITIALIZED  2
 
 /**
- *  @brief Per CPU Core Structure
+ *  This defines the constant used to indicate that the cpu code has
+ *  shut itself down.
+ */
+#define RTEMS_BSP_SMP_CPU_SHUTDOWN  3
+
+/**
+ *  @brief Per CPU Core BSP Structure
  *
  *  This structure is used to hold per core state information.
+ *
+ *  @note There will also be a SuperCore per cpu structure.  Some of these
+ *        may move there.  In particular, the starting interrupt stack pointer
+ *        makes sense to move there since the OS per CPU structure will
+ *        need to be used for EVERY ISR received.  Then this structure will
+ *        only needed from C.  But until that structure exists and
+ *        RTEMS does SMP scheduling, we will just leave everything here.
  */
 typedef struct {
+  #if defined(RTEMS_SMP)
+    /** This element is used to lock this structure */
+    rtems_lock_t  Lock; 
+
+    /** This indicates that the CPU is online. */
+    volatile uint32_t  state; 
+
+    /**
+     *  This is the request for the interrupt.
+     *  
+     *  @note This may become a chain protected by atomic instructions.
+     */
+    volatile uint32_t  message; 
+  #endif
+
 #if (CPU_ALLOCATE_INTERRUPT_STACK == TRUE) || \
     (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
   /**
    * This contains a pointer to the lower range of the interrupt stack for
    * this CPU.  This is the address allocated and freed.
    */
-  void  *interrupt_stack_low;
+  void  *interrupt_stack_low; 
 
   /**
    * This contains a pointer to the interrupt stack pointer for this CPU.
    * It will be loaded at the beginning on an ISR.
    */
-  void  *interrupt_stack_high;
+  void  *interrupt_stack_high; 
 #endif
 
   /**
@@ -91 +138 @@
 #endif
 
 #ifdef ASM
+#if defined(RTEMS_SMP)
+  #define PER_CPU_LOCK     0
+  #define PER_CPU_STATE    (1 * __RTEMS_SIZEOF_VOID_P__)
+  #define PER_CPU_MESSAGE  (2 * __RTEMS_SIZEOF_VOID_P__)
+  #define PER_CPU_END_SMP  (3 * __RTEMS_SIZEOF_VOID_P__)
+#else
+  #define PER_CPU_END_SMP  0
+#endif
 
 #if (CPU_ALLOCATE_INTERRUPT_STACK == TRUE) || \
     (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
@@ -98 +153 @@
    *  If this CPU target lets RTEMS allocates the interrupt stack, then
    *  we need to have places in the per cpu table to hold them.
    */
-  #define PER_CPU_INTERRUPT_STACK_LOW   0
-  #define PER_CPU_INTERRUPT_STACK_HIGH  (1 * __RTEMS_SIZEOF_VOID_P__)
-  #define PER_CPU_END_STACK             (2 * __RTEMS_SIZEOF_VOID_P__)
+  #define PER_CPU_INTERRUPT_STACK_LOW   PER_CPU_END_SMP
+  #define PER_CPU_INTERRUPT_STACK_HIGH  \
+          PER_CPU_INTERRUPT_STACK_LOW + (1 * __RTEMS_SIZEOF_VOID_P__)
+  #define PER_CPU_END_STACK             \
+          PER_CPU_INTERRUPT_STACK_HIGH + (1 * __RTEMS_SIZEOF_VOID_P__)
 #else
-  /*
-   *  Otherwise, there are no interrupt stack addresses in the per CPU table.
-   */
-  #define PER_CPU_END_STACK             0
+  #define PER_CPU_END_STACK             PER_CPU_END_SMP
 #endif
 
 /*
@@ -147 +201 @@
  *
  *  This is an array of per CPU core information.
  */
-extern Per_CPU_Control _Per_CPU_Information;
+#if defined(RTEMS_SMP)
+  extern Per_CPU_Control *_Per_CPU_Information;
+#else
+  extern Per_CPU_Control _Per_CPU_Information;
+#endif
+
+#if defined(RTEMS_SMP)
+/**
+ *  @brief Set of Pointers to Per CPU Core Information
+ *
+ *  This is an array of pointers to each CPU's per CPU data structure.
+ *  It should be simpler to retrieve this pointer in assembly language
+ *  that to calculate the array offset.
+ */
+extern Per_CPU_Control **Per_CPU_Information_p;
+
+/**
+ *  @brief Allocate and Initialize Per CPU Structures
+ *
+ *  This method allocates and initialize the per CPU structure.
+ */
+void _Per_CPU_Initialize(void);
+
+/* BSP provided routine */
+int rtems_bsp_smp_get_current(void)  __attribute__ ((pure));
+
+#endif
 
 /*
  * On an SMP system, these macros dereference the CPU core number.
  * But on a non-SMP system, these macros are simple references.
  * Thus when built for non-SMP, there should be no performance penalty.
  */
-#define _Thread_Heir              _Per_CPU_Information.heir
-#define _Thread_Executing         _Per_CPU_Information.executing
-#define _Thread_Idle              _Per_CPU_Information.idle
-#define _ISR_Nest_level           _Per_CPU_Information.isr_nest_level
-#define _CPU_Interrupt_stack_low  _Per_CPU_Information.interrupt_stack_low
-#define _CPU_Interrupt_stack_high _Per_CPU_Information.interrupt_stack_high
-#define _Thread_Dispatch_necessary _Per_CPU_Information.dispatch_necessary
+#if defined(RTEMS_SMP)
+  #define _Thread_Heir \
+    _Per_CPU_Information[rtems_bsp_smp_get_current()].heir
+  #define _Thread_Executing \
+    _Per_CPU_Information[rtems_bsp_smp_get_current()].executing
+  #define _Thread_Idle \
+    _Per_CPU_Information[rtems_bsp_smp_get_current()].idle
+  #define _ISR_Nest_level \
+    _Per_CPU_Information[rtems_bsp_smp_get_current()].isr_nest_level
+  #define _CPU_Interrupt_stack_low \
+    _Per_CPU_Information[rtems_bsp_smp_get_current()].interrupt_stack_low
+  #define _CPU_Interrupt_stack_high \
+    _Per_CPU_Information[rtems_bsp_smp_get_current()].interrupt_stack_high
+  #define _Thread_Dispatch_necessary \
+    _Per_CPU_Information[rtems_bsp_smp_get_current()].dispatch_necessary
+#else
+  #define _Thread_Heir               _Per_CPU_Information.heir
+  #define _Thread_Executing          _Per_CPU_Information.executing
+  #define _Thread_Idle               _Per_CPU_Information.idle
+  #define _ISR_Nest_level            _Per_CPU_Information.isr_nest_level
+  #define _CPU_Interrupt_stack_low   _Per_CPU_Information.interrupt_stack_low
+  #define _CPU_Interrupt_stack_high  _Per_CPU_Information.interrupt_stack_high
+  #define _Thread_Dispatch_necessary _Per_CPU_Information.dispatch_necessary
+#endif
 
 #endif  /* ASM */
 

cpukit/score/src/percpu.c

@@ -1 +1 @@
 /*
- *  COPYRIGHT (c) 1989-2010.
+ *  COPYRIGHT (c) 1989-2011.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -21 +21 @@
 #include <rtems/config.h>
 #include <string.h>
 
-/*
- * On single core systems, we can efficiently directly access a single
- * statically allocated per cpu structure.  And the fields are initialized
- * as individual elements just like it has always been done.
- */
-Per_CPU_Control _Per_CPU_Information;
+#if defined(RTEMS_SMP)
+  Per_CPU_Control *_Per_CPU_Information;
+  Per_CPU_Control **_Per_CPU_Information_p;
+  extern uint32_t rtems_smp_maximum_cpus;
+
+  void per_cpu_initialize(void)
+  {
+    int         cpu;
+    size_t      size;
+    uintptr_t   ptr;
+
+    /*
+     *  Allocate and initialize per CPU structures.
+     */
+    size = (rtems_smp_maximum_cpus) * sizeof(Per_CPU_Control);
+    _Per_CPU_Information = 
+      (Per_CPU_Control *)_Workspace_Allocate_or_fatal_error( size );
+    memset( _Per_CPU_Information, '\0', size );
+
+    /*
+     *  Allocate per cpu pointer table
+     */
+    size = (rtems_smp_maximum_cpus) * sizeof(Per_CPU_Control *);
+
+    _Per_CPU_Information_p = 
+      (Per_CPU_Control **)_Workspace_Allocate_or_fatal_error( size );
+
+    size = Configuration.interrupt_stack_size;
+    _Per_CPU_Information_p[0] = &_Per_CPU_Information[0];
+    for (cpu=1 ; cpu < rtems_smp_maximum_cpus ; cpu++ ) {
+      Per_CPU_Control *p = &_Per_CPU_Information[cpu];
+
+      _Per_CPU_Information_p[cpu] = p;
+
+      p->interrupt_stack_low = _Workspace_Allocate_or_fatal_error( size );
+
+      ptr = (uintptr_t) _Addresses_Add_offset( p->interrupt_stack_low, size );
+      ptr &= ~CPU_STACK_ALIGNMENT;
+      p->interrupt_stack_high = (void *)ptr;
+      p->state = RTEMS_BSP_SMP_CPU_INITIAL_STATE;
+    }
+  }
+#else
+
+  /*
+   * On single core systems, we can efficiently directly access a single
+   * statically allocated per cpu structure.  And the fields are initialized
+   * as individual elements just like it has always been done.
+   */
+  Per_CPU_Control _Per_CPU_Information;
+
+#endif

cpukit/score/src/thread.c

@@ -2 +2 @@
  *  Thread Handler
  *
  *
- *  COPYRIGHT (c) 1989-2008.
+ *  COPYRIGHT (c) 1989-2011.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -33 +33 @@
 #include <rtems/score/wkspace.h>
 #include <rtems/config.h>
 
-/*PAGE
- *
+#if defined(RTEMS_SMP)
+  #include <rtems/bspsmp.h>
+#endif
+
+/*
  *  _Thread_Handler_initialization
  *
  *  This routine initializes all thread manager related data structures.
@@ -48 +51 @@
 {
   uint32_t     ticks_per_timeslice;
   uint32_t     maximum_extensions;
+  uint32_t     maximum_internal_threads;
   #if defined(RTEMS_MULTIPROCESSING)
     uint32_t   maximum_proxies;
   #endif
@@ -80 +84 @@
 
   _Thread_Ticks_per_timeslice  = ticks_per_timeslice;
 
-#if defined(RTEMS_MULTIPROCESSING)
-  _Thread_MP_Handler_initialization( maximum_proxies );
-#endif
+  #if defined(RTEMS_MULTIPROCESSING)
+    _Thread_MP_Handler_initialization( maximum_proxies );
+  #endif
 
   /*
-   *  Initialize this class of objects.
+   *  Initialize the internal class of threads.  We need an IDLE thread
+   *  per CPU in an SMP system.  In addition, if this is a loosely
+   *  coupled multiprocessing system, account for the MPCI Server Thread.
    */
+  #if defined(RTEMS_SMP)
+    maximum_internal_threads = rtems_smp_maximum_cpus;
+  #else
+    maximum_internal_threads = 1;
+  #endif
+
+  #if defined(RTEMS_MULTIPROCESSING)
+    if ( _System_state_Is_multiprocessing )
+      maximum_internal_threads += 1;
+  #endif
 
   _Objects_Initialize_information(
     &_Thread_Internal_information,
     OBJECTS_INTERNAL_API,
     OBJECTS_INTERNAL_THREADS,
-#if defined(RTEMS_MULTIPROCESSING)
-    ( _System_state_Is_multiprocessing ) ?  2 : 1,
-#else
-    1,
-#endif
+    maximum_internal_threads,
     sizeof( Thread_Control ),
                                 /* size of this object's control block */
     false,                      /* true if names for this object are strings */
     8                           /* maximum length of each object's name */
-#if defined(RTEMS_MULTIPROCESSING)
-    ,
-    false,                      /* true if this is a global object class */
-    NULL                        /* Proxy extraction support callout */
-#endif
+    #if defined(RTEMS_MULTIPROCESSING)
+      ,
+      false,                      /* true if this is a global object class */
+      NULL                        /* Proxy extraction support callout */
+    #endif
   );
 
 }

cpukit/score/src/threadcreateidle.c

@@ -2 +2 @@
  *  Thread Handler
  *
  *
- *  COPYRIGHT (c) 1989-2008.
+ *  COPYRIGHT (c) 1989-2011.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -31 +31 @@
 #include <rtems/score/wkspace.h>
 #include <rtems/config.h>
 
-/*PAGE
- *
- *  _Thread_Create_idle
- */
+#if defined(RTEMS_SMP)
+  #include <rtems/bspsmp.h>
+#endif
 
-void _Thread_Create_idle( void )
+static inline void _Thread_Create_idle_helper(
+  uint32_t name_u32
+  #if defined(RTEMS_SMP)
+    ,
+    int    cpu
+  #endif
+) 
 {
-  Objects_Name name;
+  Objects_Name    name;
+  Thread_Control *idle;
 
-  name.name_u32 = _Objects_Build_name( 'I', 'D', 'L', 'E' );
+  name.name_u32 = name_u32;
 
   /*
    *  The entire workspace is zeroed during its initialization.  Thus, all
    *  fields not explicitly assigned were explicitly zeroed by
    *  _Workspace_Initialization.
    */
-  _Thread_Idle = _Thread_Internal_allocate();
+  idle = _Thread_Internal_allocate();
 
   /*
    *  This is only called during initialization and we better be sure
@@ -58 +64 @@
 
   _Thread_Initialize(
     &_Thread_Internal_information,
-    _Thread_Idle,
+    idle,
     NULL,        /* allocate the stack */
     _Stack_Ensure_minimum( Configuration.idle_task_stack_size ),
     CPU_IDLE_TASK_IS_FP,
@@ -76 +82 @@
    *  WARNING!!! This is necessary to "kick" start the system and
    *             MUST be done before _Thread_Start is invoked.
    */
-  _Thread_Heir      =
-  _Thread_Executing = _Thread_Idle;
+  #if defined(RTEMS_SMP)
+    _Per_CPU_Information[ cpu ].idle      =
+    _Per_CPU_Information[ cpu ].heir      =
+    _Per_CPU_Information[ cpu ].executing = idle;
+  #else
+    _Thread_Idle      =
+    _Thread_Heir      =
+    _Thread_Executing = idle;
+  #endif
 
   _Thread_Start(
-    _Thread_Idle,
+    idle,
     THREAD_START_NUMERIC,
     Configuration.idle_task,
     NULL,
     0
   );
+}
+
+void _Thread_Create_idle( void )
+{
+  #if defined(RTEMS_SMP)
+    int cpu;
 
+    for ( cpu=0 ; cpu < rtems_smp_number_of_cpus ; cpu++ ) {
+      _Thread_Create_idle_helper(
+        _Objects_Build_name( 'I', 'D', 'L', 'E' ),
+        cpu
+      );
+    }
+  #else
+    _Thread_Create_idle_helper(_Objects_Build_name( 'I', 'D', 'L', 'E' ));
+  #endif
 }