RCS file: /usr1/CVS/rtems/c/src/lib/libcpu/sparc64/shared/score/interrupt.S,v
retrieving revision 1.2
diff -u -p -r1.2 interrupt.S
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PUBLIC(_ISR_Handler) |
195 | 195 | subcc %g4, 1, %g4 ! outermost interrupt handler? |
196 | 196 | bnz dont_switch_stacks ! No, then do not switch stacks |
197 | 197 | |
198 | | setx SYM(_CPU_Interrupt_stack_high), %o5, %g1 |
| 198 | setx SYM(INTERRUPT_STACK_HIGH), %o5, %g1 |
199 | 199 | ldx [%g1], %sp |
200 | 200 | |
201 | 201 | /* |
RCS file: /usr1/CVS/rtems/cpukit/score/cpu/sparc64/rtems/score/cpu.h,v
retrieving revision 1.2
diff -u -p -r1.2 cpu.h
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SCORE_EXTERN Context_Control_fp _CPU_Nu |
570 | 570 | * The SPARC supports a software based interrupt stack and these |
571 | 571 | * are required. |
572 | 572 | */ |
573 | | |
| 573 | /* |
574 | 574 | SCORE_EXTERN void *_CPU_Interrupt_stack_low; |
575 | 575 | SCORE_EXTERN void *_CPU_Interrupt_stack_high; |
576 | | |
| 576 | */ |
577 | 577 | /* |
578 | 578 | * This flag is context switched with each thread. It indicates |
579 | 579 | * that THIS thread has an _ISR_Dispatch stack frame on its stack. |