Ticket #1573: percpu-3.diff

File percpu-3.diff, 89.7 KB (added by Joel Sherrill, on 06/24/10 at 17:32:19)

Per CPU Patch V3

  • c/src/lib/libbsp/i386/shared/irq/irq.c 

    RCS file: /usr1/CVS/rtems/c/src/lib/libbsp/i386/shared/irq/irq.c,v
retrieving revision 1.22
diff -u -r1.22 irq.c
     
    249249  irq_count[vector]++;
    250250  bsp_interrupt_handler_dispatch(vector);
    251251}
    252 
    253 void _ThreadProcessSignalsFromIrq (void)
    254 {
    255   /*
    256    * Process pending signals that have not already been
    257    * processed by _Thread_Displatch. This happens quite
    258    * unfrequently : the ISR must have posted an action
    259    * to the current running thread.
    260    */
    261   if ( _Thread_Do_post_task_switch_extension ||
    262        _Thread_Executing->do_post_task_switch_extension ) {
    263     _Thread_Executing->do_post_task_switch_extension = false;
    264     _API_extensions_Run_postswitch();
    265   }
    266   /*
    267    * I plan to process other thread related events here.
    268    * This will include DEBUG session requested from keyboard...
    269    */
    270 }

  • c/src/lib/libbsp/i386/shared/irq/irq_asm.S 

    RCS file: /usr1/CVS/rtems/c/src/lib/libbsp/i386/shared/irq/irq_asm.S,v
retrieving revision 1.17
diff -u -r1.17 irq_asm.S
     
    88 *  found in found in the file LICENSE in this distribution or at
    99 *  http://www.rtems.com/license/LICENSE.
    1010 *
    11  *  $Id: irq_asm.S,v 1.17 2010/06/15 16:36:19 joel Exp $
     11 *  $Id: irq_asm.S,v 1.16 2009/11/30 03:47:10 ralf Exp $
    1212 */
    1313
    1414#include <rtems/asm.h>
     15#include <bspopts.h>
    1516#include <bsp/irq_asm.h>
    1617#include <rtems/score/cpu.h>
     18#include <rtems/score/percpu.h>
    1719
    1820#ifndef CPU_STACK_ALIGNMENT
    1921#error "Missing header? CPU_STACK_ALIGNMENT is not defined here"
    … …  
    2224/* Stack frame we use for intermediate storage               */
    2325#define ARG_OFF 0
    2426#define MSK_OFF 4
    25 #define EBP_OFF 8        /* code restoring ebp/esp relies on */
    26 #define ESP_OFF 12       /* esp being on top of ebp!         */
     27#define EBX_OFF 8        /* ebx                              */
     28#define EBP_OFF 12       /* code restoring ebp/esp relies on */
     29#define ESP_OFF 16       /* esp being on top of ebp!         */
    2730#ifdef __SSE__
    28 #define FRM_SIZ (16+512)
    29 #define SSE_OFF 16
     31#define FRM_SIZ (20+512)
     32#define SSE_OFF 20
    3033#else
    31 #define FRM_SIZ 16
     34#define FRM_SIZ 20
    3235#endif
    3336
    3437        BEGIN_CODE
    … …  
    6467
    6568        /*
    6669         * Establish an aligned stack frame
    67          *   original-sp
    68          *   saved-bp
    69          *   saved-irq-mask
    70          *   vector-arg-to-C_dispatch_isr   <- aligned SP
     70         *   original sp
     71         *   saved ebx
     72         *   saved ebp
     73         *   saved irq mask
     74         *   vector arg to C_dispatch_isr   <- aligned SP
    7175         */
    7276        movl      esp, eax
    7377        subl      $FRM_SIZ, esp
    7478        andl      $ - CPU_STACK_ALIGNMENT, esp
     79        movl      ebx, EBX_OFF(esp)
    7580        movl      eax, ESP_OFF(esp)
    7681        movl      ebp, EBP_OFF(esp)
    7782
    … …  
    8287         */
    8388
    8489        /* We save SSE here (on the task stack) because we possibly
    85          * call other C-code (besides the ISR, namely _Thread_Dispatch()
    86          * or _ThreadProcessSignalsFromIrq()).
     90         * call other C-code (besides the ISR, namely _Thread_Dispatch())
    8791         */
    8892    /*  don't wait here; a possible exception condition will eventually be
    8993     *  detected when the task resumes control and executes a FP instruction
    … …  
    9599        ldmxcsr ARG_OFF(esp)            /* clean-slate MXCSR              */
    96100#endif
    97101
     102        /* Do not disable any 8259 interrupts if this isn't from one */
     103        cmp       ecx, 16               /* is this a PIC IRQ? */
     104        jge       .check_stack_switch
    98105
    99106        /*
    100107         * acknowledge the interrupt
    101          *
    102108         */
    103         movw      SYM (i8259s_cache), ax /* move current i8259 interrupt mask in ax */
     109        movw      SYM (i8259s_cache), ax /* save current i8259 interrupt mask */
    104110        movl      eax, MSK_OFF(esp)      /* save in stack frame */
     111
    105112        /*
    106113         * compute the new PIC mask:
    107114         *
    … …  
    129136         *  Now switch stacks if necessary
    130137         */
    131138
     139PUBLIC (ISR_STOP)
     140ISR_STOP:
    132141.check_stack_switch:
    133142        movl      esp, ebp                  /* ebp = previous stack pointer */
    134         cmpl      $0, SYM (_ISR_Nest_level) /* is this the outermost interrupt? */
     143
     144        movl      $SYM(rtems_per_cpu_info), ebx
     145
     146        /* is this the outermost interrupt? */
     147        cmpl      $0, PER_CPU_ISR_NEST_LEVEL(ebx)
    135148        jne       nested                    /* No, then continue */
    136         movl      SYM (_CPU_Interrupt_stack_high), esp
     149        movl      PER_CPU_INTERRUPT_STACK_HIGH(ebx), esp
    137150
    138151        /*
    139152         *  We want to insure that the old stack pointer is in ebp
    … …  
    142155         */
    143156
    144157nested:
    145         incl      SYM (_ISR_Nest_level)     /* one nest level deeper */
     158        incl      PER_CPU_ISR_NEST_LEVEL(ebx)  /* one nest level deeper */
    146159        incl      SYM (_Thread_Dispatch_disable_level) /* disable multitasking */
    147160
    148161        /*
    … …  
    151164         */
    152165        sti
    153166
    154     /*
     167        /*
    155168         *  ECX is preloaded with the vector number; store as arg
    156169         *  on top of stack. Note that _CPU_Interrupt_stack_high
    157170         *  was adjusted in _CPU_Interrupt_stack_setup() (score/rtems/cpu.h)
    … …  
    166179         */
    167180        cli
    168181
     182        movl      ARG_OFF(esp), ecx     /* grab vector arg from stack */
     183
    169184        /*
    170185         * Restore stack. This moves back to the task stack
    171186         * when all interrupts are unnested.
    … …  
    175190        /*
    176191         * restore the original i8259 masks
    177192         */
     193        /* Do not touch 8259 interrupts if this isn't from one */
     194        cmp       ecx, 16               /* is this a PIC IRQ? */
     195        jge       .dont_restore_i8259
     196
    178197        movl      MSK_OFF(esp), eax
    179198        movw      ax, SYM (i8259s_cache)
    180199        outb      $PIC_MASTER_IMR_IO_PORT
    181200        movb      ah, al
    182201        outb      $PIC_SLAVE_IMR_IO_PORT
    183202
    184         decl      SYM (_ISR_Nest_level)     /* one less ISR nest level */
     203.dont_restore_i8259:
     204        decl      PER_CPU_ISR_NEST_LEVEL(ebx)  /* one less ISR nest level */
    185205                                            /* If interrupts are nested, */
    186206                                            /*   then dispatching is disabled */
    187207
    … …  
    190210                                            /* Is dispatch disabled */
    191211        jne       .exit                     /* Yes, then exit */
    192212
    193         cmpb      $0, SYM (_Context_Switch_necessary)
     213        cmpb      $0, PER_CPU_DISPATCH_NEEDED(ebx)
    194214                                            /* Is task switch necessary? */
    195215        jne       .schedule                 /* Yes, then call the scheduler */
    196 
    197         cmpb      $0, SYM (_ISR_Signals_to_thread_executing)
    198                                             /* signals sent to Run_thread */
    199                                             /*   while in interrupt handler? */
    200         je        .exit                     /* No, exit */
    201 
    202 .bframe:
    203         movb      $0, SYM (_ISR_Signals_to_thread_executing)
    204         /*
    205          * This code is the less critical path. In order to have a single
    206          * Thread Context, we take the same frame than the one pushed on
    207          * exceptions. This makes sense because Signal is a software
    208          * exception.
    209          */
    210         call      _ThreadProcessSignalsFromIrq
    211 
    212         jmp       .exit
     216        jmp       .exit                     /* No, exit */
    213217
    214218.schedule:
    215219        /*
    … …  
    229233        fxrstor   SSE_OFF(esp)
    230234#endif
    231235
    232         /* restore ebp and original esp */
    233         addl      $EBP_OFF, esp
     236        /* restore ebx, ebp and original esp */
     237        addl      $EBX_OFF, esp
     238        popl      ebx
    234239        popl      ebp
    235240        popl      esp
     241
    236242        /*
    237243         * BEGINNING OF DE-ESTABLISH SEGMENTS
    238244         *
    … …  
    277283DISTINCT_INTERRUPT_ENTRY(13)
    278284DISTINCT_INTERRUPT_ENTRY(14)
    279285DISTINCT_INTERRUPT_ENTRY(15)
     286DISTINCT_INTERRUPT_ENTRY(16)
    280287
    281288        /*
    282289         * routine used to initialize the IDT by default

  • c/src/lib/libbsp/mips/shared/irq/exception.S 

    RCS file: /usr1/CVS/rtems/c/src/lib/libbsp/mips/shared/irq/exception.S,v
retrieving revision 1.2
diff -u -r1.2 exception.S
     
    3535
    3636#include <bspopts.h>
    3737#include <rtems/asm.h>
     38#include <rtems/score/percpu.h>
    3839#include <rtems/mips/iregdef.h>
    3940#include <rtems/mips/idtcpu.h>
    4041#if BSP_HAS_USC320
    … …  
    8889#endif
    8990
    9091
    91 EXTERN(_ISR_Nest_level, 4)
    9292EXTERN(_Thread_Dispatch_disable_level,4)
    93 EXTERN(_Context_Switch_necessary,1)
    9493EXTERN(_ISR_Signals_to_thread_executing,1)
    9594.extern _Thread_Dispatch
    9695.extern _ISR_Vector_table
    … …  
    236235  /*
    237236   *  _ISR_Nest_level++;
    238237   */
    239         lw      t0,_ISR_Nest_level
     238        lw      t0,ISR_NEST_LEVEL
    240239        NOP
    241240        add     t0,t0,1
    242         sw      t0,_ISR_Nest_level
     241        sw      t0,ISR_NEST_LEVEL
    243242  /*
    244243   *  _Thread_Dispatch_disable_level++;
    245244   */
    … …  
    299298  /*
    300299   *  --_ISR_Nest_level;
    301300   */
    302         lw      t2,_ISR_Nest_level
     301        lw      t2,ISR_NEST_LEVEL
    303302        NOP
    304303        add     t2,t2,-1
    305         sw      t2,_ISR_Nest_level
     304        sw      t2,ISR_NEST_LEVEL
    306305  /*
    307306   *  --_Thread_Dispatch_disable_level;
    308307   */
    … …  
    324323   *    restore stack
    325324   *  #endif
    326325   *
    327    *  if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing )
     326   *  if ( !_Context_Switch_necessary )
    328327   *    goto the label "exit interrupt (simple case)"
    329328   */
    330         lb      t0,_Context_Switch_necessary
    331         lb      t1,_ISR_Signals_to_thread_executing
     329        lb      t0,DISPATCH_NEEDED
    332330        NOP
    333         or      t0,t0,t1
     331        or      t0,t0,t0
    334332        beq     t0,zero,_ISR_Handler_exit
    335333        NOP
    336334

  • c/src/lib/libbsp/powerpc/score603e/irq/irq.c 

    RCS file: /usr1/CVS/rtems/c/src/lib/libbsp/powerpc/score603e/irq/irq.c,v
retrieving revision 1.13
diff -u -r1.13 irq.c
     
    472472  return 0;
    473473}
    474474
    475 void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx)
    476 {
    477 printk(" _ThreadProcessSignalsFromIrq \n");
    478   /*
    479    * Process pending signals that have not already been
    480    * processed by _Thread_Displatch. This happens quite
    481    * unfrequently : the ISR must have posted an action
    482    * to the current running thread.
    483    */
    484   if ( _Thread_Do_post_task_switch_extension ||
    485        _Thread_Executing->do_post_task_switch_extension ) {
    486     _Thread_Executing->do_post_task_switch_extension = false;
    487     _API_extensions_Run_postswitch();
    488   }
    489   /*
    490    * I plan to process other thread related events here.
    491    * This will include DEBUG session requested from keyboard...
    492    */
    493 }
    494 
    495475rtems_status_code bsp_interrupt_facility_initialize(void)
    496476{
    497477  /* Install exception handler */

  • c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.c 

    RCS file: /usr1/CVS/rtems/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.c,v
retrieving revision 1.8
diff -u -r1.8 irq.c
     
    482482    usiu.simask = ppc_cached_irq_mask;
    483483  }
    484484}
    485 
    486 void _ThreadProcessSignalsFromIrq (CPU_Exception_frame* ctx)
    487 {
    488   /*
    489    * Process pending signals that have not already been
    490    * processed by _Thread_Displatch. This happens quite
    491    * unfrequently : the ISR must have posted an action
    492    * to the current running thread.
    493    */
    494   if ( _Thread_Do_post_task_switch_extension ||
    495        _Thread_Executing->do_post_task_switch_extension ) {
    496     _Thread_Executing->do_post_task_switch_extension = false;
    497     _API_extensions_Run_postswitch();
    498   }
    499   /*
    500    * I plan to process other thread related events here.
    501    * This will include DEBUG session requested from keyboard...
    502    */
    503 }

  • c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_asm.S 

    RCS file: /usr1/CVS/rtems/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_asm.S,v
retrieving revision 1.5
diff -u -r1.5 irq_asm.S
     
    2626
    2727#include <rtems/asm.h>
    2828#include <rtems/score/cpu.h>
     29#include <rtems/score/percpu.h>
    2930#include <libcpu/vectors.h>
    3031#include <libcpu/raw_exception.h>
    3132
    … …  
    118119        /*
    119120         * Retrieve current nesting level from _ISR_Nest_level
    120121         */
    121         lis             r7, _ISR_Nest_level@ha
    122         lwz             r3, _ISR_Nest_level@l(r7)
     122        lis             r7, ISR_NEST_LEVEL@ha
     123        lwz             r3, ISR_NEST_LEVEL@l(r7)
    123124
    124125        /*
    125126         * Check if stack switch is necessary
    … …  
    141142        lwz     r6, _Thread_Dispatch_disable_level@l(r15)
    142143
    143144        /* store new nesting level in _ISR_Nest_level */
    144         stw     r3, _ISR_Nest_level@l(r7)
     145        stw     r3, ISR_NEST_LEVEL@l(r7)
    145146
    146147        addi    r6, r6, 1
    147148
    … …  
    170171         * value as an easy exit condition because if interrupt nesting level > 1
    171172         * then _Thread_Dispatch_disable_level > 1
    172173         */
    173         lis             r7, _ISR_Nest_level@ha
    174         lwz             r4, _ISR_Nest_level@l(r7)
     174        lis             r7, ISR_NEST_LEVEL@ha
     175        lwz             r4, ISR_NEST_LEVEL@l(r7)
    175176
    176177        /*
    177178         * start decrementing _Thread_Dispatch_disable_level
    … …  
    181182        addi    r4, r4, -1      /* Continue decrementing nesting level */
    182183        addi    r3, r3, -1      /* Continue decrementing _Thread_Dispatch_disable_level */
    183184
    184         stw     r4, _ISR_Nest_level@l(r7) /* End decrementing nesting level */
     185        stw     r4, ISR_NEST_LEVEL@l(r7) /* End decrementing nesting level */
    185186        stw     r3,_Thread_Dispatch_disable_level@l(r15) /* End decrementing _Thread_Dispatch_disable_level */
    186187
    187188        cmpwi   r3, 0
    … …  
    199200         * Interrupt are still disabled. Time to check if scheduler request to
    200201         * do something with the current thread...
    201202         */
    202         addis   r4, 0, _Context_Switch_necessary@ha
    203         lbz     r5, _Context_Switch_necessary@l(r4)
     203        addis   r4, 0, DISPATCH_NEEDED@ha
     204        lbz     r5, DISPATCH_NEEDED@l(r4)
    204205        cmpwi   r5, 0
    205         bne     switch
    206 
    207         addis   r6, 0, _ISR_Signals_to_thread_executing@ha
    208         lbz     r7, _ISR_Signals_to_thread_executing@l(r6)
    209         cmpwi   r7, 0
    210         li      r8, 0
    211206        beq     easy_exit
    212207
    213         stb     r8, _ISR_Signals_to_thread_executing@l(r6)
    214 
    215208        /*
    216          * going to call _ThreadProcessSignalsFromIrq
     209         * going to call _Thread_Dispatch
    217210         * Push a complete exception like frame...
    218211         */
    219212        stmw    r16, GPR16_OFFSET(r1)
    … …  
    232225        /*
    233226         * Call High Level signal handling code
    234227         */
    235         bl      _ThreadProcessSignalsFromIrq
     228        bl      _Thread_Dispatch
    236229
    237230        /*
    238231         * start restoring exception like frame
    … …  
    272265        rfi
    273266
    274267
    275 switch:
    276         bl      SYM (_Thread_Dispatch)
    277 
    278268easy_exit:
    279269        /*
    280270         * start restoring interrupt frame

  • c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc.S 

    RCS file: /usr1/CVS/rtems/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc.S,v
retrieving revision 1.5
diff -u -r1.5 ppc_exc.S
     
    1313 */
    1414
    1515/* Load macro definitions */
     16#include <rtems/asm.h>
     17#include <rtems/system.h>
     18#include <rtems/score/percpu.h>
     19
    1620#include "ppc_exc_asm_macros.h"
    1721
    1822/******************************************************/

  • c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h 

    RCS file: /usr1/CVS/rtems/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h,v
retrieving revision 1.10
diff -u -r1.10 ppc_exc_asm_macros.h
     
    422422         */
    423423
    424424        /* Increment ISR nest level and thread dispatch disable level */
    425         lwz     SCRATCH_REGISTER_0, _ISR_Nest_level@sdarel(r13)
     425        lis     SCRATCH_REGISTER_2, ISR_NEST_LEVEL@ha
     426        lwz     SCRATCH_REGISTER_0, ISR_NEST_LEVEL@l(SCRATCH_REGISTER_2)
    426427        lwz     SCRATCH_REGISTER_1, _Thread_Dispatch_disable_level@sdarel(r13)
    427428        addi    SCRATCH_REGISTER_0, SCRATCH_REGISTER_0, 1
    428429        addi    SCRATCH_REGISTER_1, SCRATCH_REGISTER_1, 1
    429         stw     SCRATCH_REGISTER_0, _ISR_Nest_level@sdarel(r13)
     430        stw     SCRATCH_REGISTER_0, ISR_NEST_LEVEL@l(SCRATCH_REGISTER_2)
    430431        stw     SCRATCH_REGISTER_1, _Thread_Dispatch_disable_level@sdarel(r13)
    431432
    432433        /*
    … …  
    612613         */
    613614
    614615        /* Decrement ISR nest level and thread dispatch disable level */
    615         lwz     SCRATCH_REGISTER_0, _ISR_Nest_level@sdarel(r13)
     616        lis     SCRATCH_REGISTER_2, ISR_NEST_LEVEL@ha
     617        lwz     SCRATCH_REGISTER_0, ISR_NEST_LEVEL@l(SCRATCH_REGISTER_2)
    616618        lwz     SCRATCH_REGISTER_1, _Thread_Dispatch_disable_level@sdarel(r13)
    617619        subi    SCRATCH_REGISTER_0, SCRATCH_REGISTER_0, 1
    618620        subic.  SCRATCH_REGISTER_1, SCRATCH_REGISTER_1, 1
    619         stw     SCRATCH_REGISTER_0, _ISR_Nest_level@sdarel(r13)
     621        stw     SCRATCH_REGISTER_0, ISR_NEST_LEVEL@l(SCRATCH_REGISTER_2)
    620622        stw     SCRATCH_REGISTER_1, _Thread_Dispatch_disable_level@sdarel(r13)
    621623
    622624        /* Branch to skip thread dispatching */

  • c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_hdl.c 

    RCS file: /usr1/CVS/rtems/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_hdl.c,v
retrieving revision 1.8
diff -u -r1.8 ppc_exc_hdl.c
     
    8686     *        interrupts around the execution of _Thread_Dispatch();
    8787     */
    8888    _Thread_Dispatch();
    89   } else if ( _ISR_Signals_to_thread_executing ) {
    90     _ISR_Signals_to_thread_executing = 0;
    91     /*
    92      * Process pending signals that have not already been
    93      * processed by _Thread_Dispatch. This happens quite
    94      * unfrequently : the ISR must have posted an action
    95      * to the current running thread.
    96      */
    97     if ( _Thread_Do_post_task_switch_extension ||
    98         _Thread_Executing->do_post_task_switch_extension ) {
    99       _Thread_Executing->do_post_task_switch_extension = false;
    100       _API_extensions_Run_postswitch();
    101     }
    10289  }
    10390}

  • c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c 

    RCS file: /usr1/CVS/rtems/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c,v
retrieving revision 1.15
diff -u -r1.15 cpu_asm.c
     
    173173    return;
    174174
    175175  if ( _Thread_Dispatch_disable_level ) {
    176     _ISR_Signals_to_thread_executing = FALSE;
    177176    return;
    178177  }
    179178
    180   if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) {
    181     _ISR_Signals_to_thread_executing = FALSE;
     179  if ( _Context_Switch_necessary ) {
    182180    _Thread_Dispatch();
    183181  }
    184182}

  • c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c 

    RCS file: /usr1/CVS/rtems/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c,v
retrieving revision 1.17
diff -u -r1.17 cpu_asm.c
     
    175175    return;
    176176
    177177  if ( _Thread_Dispatch_disable_level ) {
    178     _ISR_Signals_to_thread_executing = FALSE;
    179178    return;
    180179  }
    181180
    182   if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) {
    183     _ISR_Signals_to_thread_executing = FALSE;
     181  if ( _Context_Switch_necessary ) {
    184182    _Thread_Dispatch();
    185183  }
    186184}

  • c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c 

    RCS file: /usr1/CVS/rtems/c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c,v
retrieving revision 1.13
diff -u -r1.13 cpu_asm.c
     
    9898    return;
    9999
    100100  if ( _Thread_Dispatch_disable_level ) {
    101     _ISR_Signals_to_thread_executing = FALSE;
    102101    return;
    103102  }
    104103
    105   if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) {
    106     _ISR_Signals_to_thread_executing = FALSE;
     104  if ( _Context_Switch_necessary ) {
    107105    _Thread_Dispatch();
    108106  }
    109107}

  • c/src/lib/libcpu/sh/shgdb/score/cpu_asm.c 

    RCS file: /usr1/CVS/rtems/c/src/lib/libcpu/sh/shgdb/score/cpu_asm.c,v
retrieving revision 1.2
diff -u -r1.2 cpu_asm.c
     
    7272    return;
    7373
    7474  if ( _Thread_Dispatch_disable_level ) {
    75     _ISR_Signals_to_thread_executing = FALSE;
    7675    return;
    7776  }
    7877
    79   if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) {
    80     _ISR_Signals_to_thread_executing = FALSE;
     78  if ( _Context_Switch_necessary ) {
    8179    _Thread_Dispatch();
    8280  }
    8381}

  • c/src/lib/libcpu/sparc64/shared/score/interrupt.S 

    RCS file: /usr1/CVS/rtems/c/src/lib/libcpu/sparc64/shared/score/interrupt.S,v
retrieving revision 1.1
diff -u -r1.1 interrupt.S
     
    2626 */
    2727
    2828#include <rtems/asm.h>
     29#include <rtems/score/percpu.h>
    2930
    3031
    3132/*
    … …  
    178179
    179180  setx  SYM(_Thread_Dispatch_disable_level), %o5, %g3
    180181  lduw  [%g3], %g5
    181   setx  SYM(_ISR_Nest_level), %o5, %g6
     182  setx  ISR_NEST_LEVEL, %o5, %g6
    182183  lduw  [%g6], %g4
    183184
    184185  add      %g5, 1, %g5
    … …  
    345346    bnz      simple_return   ! Yes, then do a "simple" exit
    346347    nop
    347348
    348     setx    SYM(_Context_Switch_necessary), %o5, %g7
     349    setx    DISPATCH_NEEDED, %o5, %g7
    349350
    350351
    351352    /*
    … …  
    360361    nop
    361362
    362363    /*
    363      *  Finally, check to see if signals were sent to the currently
    364      *  executing task.  If so, we need to invoke the interrupt dispatcher.
    365      */
    366     setx    SYM(_ISR_Signals_to_thread_executing), %o5, %g5
    367     ldub    [%g5], %o5
    368 
    369     orcc    %o5, %g0, %g0   ! Were signals sent to the currently
    370     !   executing thread?
    371     bz      simple_return   ! yes, then invoke the dispatcher
    372     ! use the delay slot to clear the signals
    373     !   to the currently executing task flag
    374     stb     %g0, [%g5]
    375 
    376 
    377     /*
    378364     *  Invoke interrupt dispatcher.
    379365     */
    380366PUBLIC(_ISR_Dispatch)
    … …  
    408394   *  _Thread_Dispatch before leaving this ISR Dispatch context.
    409395   */
    410396
    411   setx     SYM(_Context_Switch_necessary), %o5, %o1
     397  setx     DISPATCH_NEEDED, %o5, %o1
    412398  ldub     [%o1], %o2
    413399
    414   ! NOTE: Use some of delay slot to start loading this
    415   setx     SYM(_ISR_Signals_to_thread_executing), %o5, %o1
    416   ldub     [%o1], %o3
    417 
    418400  orcc     %o2, %g0, %g0   ! Is thread switch necessary?
    419   bnz      dispatchAgain   ! yes, then invoke the dispatcher AGAIN
    420   ! NOTE: Use the delay slot to catch the orcc below
    421 
    422   /*
    423    *  Finally, check to see if signals were sent to the currently
    424    *  executing task.  If so, we need to invoke the interrupt dispatcher.
    425    */
    426 
    427   ! NOTE: Delay slots above were used to perform the load AND
    428   !       this orcc falls into the delay slot for bnz above
    429   orcc     %o3, %g0, %g0   ! Were signals sent to the currently
    430   !   executing thread?
    431401  bz       allow_nest_again ! No, then clear out and return
    432402  nop
    433403
    434404  ! Yes, then invoke the dispatcher
    435   dispatchAgain:
     405dispatchAgain:
    436406  mov      3, %g4        ! syscall (enable interrupts)
    437407  ta       0             ! syscall (enable interrupts)
    438408  ba       isr_dispatch

  • cpukit/configure.ac 

    RCS file: /usr1/CVS/rtems/cpukit/configure.ac,v
retrieving revision 1.187
diff -u -r1.187 configure.ac
     
    251251## Check if libc provides BSD's strlcpy/strlcat
    252252AC_CHECK_FUNCS(strlcpy strlcat)
    253253
     254## This is needed to generate the field offsets of the per CPU
     255## data structure so they can be accessed from assembly code.
     256AC_CHECK_SIZEOF([void *])
    254257
    255258# ... far too many conditionals ...
    256259AM_CONDITIONAL(LIBRPC,[test x"$rtems_cv_HAS_NETWORKING" = x"yes"])

  • cpukit/posix/src/killinfo.c 

    RCS file: /usr1/CVS/rtems/cpukit/posix/src/killinfo.c,v
retrieving revision 1.24
diff -u -r1.24 killinfo.c
     
    314314   */
    315315process_it:
    316316
    317   the_thread->do_post_task_switch_extension = true;
    318 
    319317  /*
    320318   *  Returns true if the signal was synchronously given to a thread
    321319   *  blocked waiting for the signal.

  • cpukit/posix/src/psignalclearprocesssignals.c 

    RCS file: /usr1/CVS/rtems/cpukit/posix/src/psignalclearprocesssignals.c,v
retrieving revision 1.6
diff -u -r1.6 psignalclearprocesssignals.c
     
    5353    }
    5454    if ( clear_signal ) {
    5555      _POSIX_signals_Pending &= ~mask;
    56       if ( !_POSIX_signals_Pending )
    57         _Thread_Do_post_task_switch_extension--;
    5856    }
    5957  _ISR_Enable( level );
    6058}

  • cpukit/posix/src/psignalsetprocesssignals.c 

    RCS file: /usr1/CVS/rtems/cpukit/posix/src/psignalsetprocesssignals.c,v
retrieving revision 1.6
diff -u -r1.6 psignalsetprocesssignals.c
     
    4141  ISR_Level  level;
    4242
    4343  _ISR_Disable( level );
    44     if ( !_POSIX_signals_Pending )
    45       _Thread_Do_post_task_switch_extension++;
    4644    _POSIX_signals_Pending |= mask;
    4745  _ISR_Enable( level );
    4846}

  • cpukit/posix/src/psignalunblockthread.c 

    RCS file: /usr1/CVS/rtems/cpukit/posix/src/psignalunblockthread.c,v
retrieving revision 1.10
diff -u -r1.10 psignalunblockthread.c
     
    9898     *    + Any other combination, do nothing.
    9999     */
    100100
    101     the_thread->do_post_task_switch_extension = true;
    102 
    103101    if ( the_thread->current_state & STATES_INTERRUPTIBLE_BY_SIGNAL ) {
    104102      the_thread->Wait.return_code = EINTR;
    105103      /*
    … …  
    120118          }
    121119    } else if ( the_thread->current_state == STATES_READY ) {
    122120      if ( _ISR_Is_in_progress() && _Thread_Is_executing( the_thread ) )
    123         _ISR_Signals_to_thread_executing = true;
     121        _Context_Switch_necessary = true;
    124122    }
    125123  }
    126124  return false;

  • cpukit/posix/src/pthreadcreate.c 

    RCS file: /usr1/CVS/rtems/cpukit/posix/src/pthreadcreate.c,v
retrieving revision 1.20
diff -u -r1.20 pthreadcreate.c
     
    191191  api->schedparam  = schedparam;
    192192
    193193  /*
    194    *  This insures we evaluate the process-wide signals pending when we
    195    *  first run.
    196    *
    197    *  NOTE:  Since the thread starts with all unblocked, this is necessary.
    198    */
    199   the_thread->do_post_task_switch_extension = true;
    200 
    201   /*
    202194   *  POSIX threads are allocated and started in one operation.
    203195   */
    204196  status = _Thread_Start(

  • cpukit/posix/src/pthreadkill.c 

    RCS file: /usr1/CVS/rtems/cpukit/posix/src/pthreadkill.c,v
retrieving revision 1.15
diff -u -r1.15 pthreadkill.c
     
    6363
    6464        (void) _POSIX_signals_Unblock_thread( the_thread, sig, NULL );
    6565
    66         the_thread->do_post_task_switch_extension = true;
    67 
    6866        if ( _ISR_Is_in_progress() && _Thread_Is_executing( the_thread ) )
    69           _ISR_Signals_to_thread_executing = true;
     67          _Context_Switch_necessary = true;
    7068      }
    7169      _Thread_Enable_dispatch();
    7270      return 0;

  • cpukit/posix/src/pthreadsigmask.c 

    RCS file: /usr1/CVS/rtems/cpukit/posix/src/pthreadsigmask.c,v
retrieving revision 1.8
diff -u -r1.8 pthreadsigmask.c
     
    6565
    6666  if ( ~api->signals_blocked &
    6767       (api->signals_pending | _POSIX_signals_Pending) ) {
    68     _Thread_Executing->do_post_task_switch_extension = true;
    6968    _Thread_Dispatch();
    7069  }
    7170

  • cpukit/rtems/src/signalsend.c 

    RCS file: /usr1/CVS/rtems/cpukit/rtems/src/signalsend.c,v
retrieving revision 1.10
diff -u -r1.10 signalsend.c
     
    6464        if ( asr->is_enabled ) {
    6565          _ASR_Post_signals( signal_set, &asr->signals_posted );
    6666
    67           the_thread->do_post_task_switch_extension = true;
    68 
    6967          if ( _ISR_Is_in_progress() && _Thread_Is_executing( the_thread ) )
    70             _ISR_Signals_to_thread_executing = true;
     68            _Context_Switch_necessary = true;
    7169        } else {
    7270          _ASR_Post_signals( signal_set, &asr->signals_pending );
    7371        }

  • cpukit/rtems/src/taskmode.c 

    RCS file: /usr1/CVS/rtems/cpukit/rtems/src/taskmode.c,v
retrieving revision 1.11
diff -u -r1.11 taskmode.c
     
    117117      _ASR_Swap_signals( asr );
    118118      if ( _ASR_Are_signals_pending( asr ) ) {
    119119        needs_asr_dispatching = true;
    120         executing->do_post_task_switch_extension = true;
    121120      }
    122121    }
    123122  }

  • cpukit/score/Makefile.am 

    RCS file: /usr1/CVS/rtems/cpukit/score/Makefile.am,v
retrieving revision 1.81
diff -u -r1.81 Makefile.am
     
    2424    include/rtems/score/coremutex.h include/rtems/score/coresem.h \
    2525    include/rtems/score/heap.h include/rtems/score/protectedheap.h \
    2626    include/rtems/score/interr.h include/rtems/score/isr.h \
    27     include/rtems/score/object.h include/rtems/score/priority.h \
    28     include/rtems/score/stack.h include/rtems/score/states.h \
    29     include/rtems/score/sysstate.h include/rtems/score/thread.h \
    30     include/rtems/score/threadq.h include/rtems/score/threadsync.h \
    31     include/rtems/score/timespec.h include/rtems/score/timestamp.h \
    32     include/rtems/score/timestamp64.h include/rtems/score/tod.h \
    33     include/rtems/score/tqdata.h include/rtems/score/userext.h \
    34     include/rtems/score/watchdog.h include/rtems/score/wkspace.h \
    35     include/rtems/score/cpuopts.h
     27    include/rtems/score/object.h include/rtems/score/percpu.h \
     28    include/rtems/score/priority.h include/rtems/score/stack.h \
     29    include/rtems/score/states.h include/rtems/score/sysstate.h \
     30    include/rtems/score/thread.h include/rtems/score/threadq.h \
     31    include/rtems/score/threadsync.h include/rtems/score/timespec.h \
     32    include/rtems/score/timestamp.h include/rtems/score/timestamp64.h \
     33    include/rtems/score/tod.h include/rtems/score/tqdata.h \
     34    include/rtems/score/userext.h include/rtems/score/watchdog.h \
     35    include/rtems/score/wkspace.h include/rtems/score/cpuopts.h
    3636
    3737if HAS_PTHREADS
    3838include_rtems_score_HEADERS += include/rtems/score/corespinlock.h \
    … …  
    101101    src/coremutexseize.c src/coremutexsurrender.c \
    102102    src/coremutexseizeintr.c
    103103
     104## CORE_PERCPU_C_FILES
     105libscore_a_SOURCES += src/percpu.c
     106
    104107## CORE_RWLOCK_C_FILES
    105108if HAS_PTHREADS
    106109libscore_a_SOURCES += src/corerwlock.c src/corerwlockobtainread.c \

  • cpukit/score/preinstall.am 

    RCS file: /usr1/CVS/rtems/cpukit/score/preinstall.am,v
retrieving revision 1.21
diff -u -r1.21 preinstall.am
     
    9999        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/object.h
    100100PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/object.h
    101101
     102$(PROJECT_INCLUDE)/rtems/score/percpu.h: include/rtems/score/percpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
     103        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/percpu.h
     104PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/percpu.h
     105
    102106$(PROJECT_INCLUDE)/rtems/score/priority.h: include/rtems/score/priority.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
    103107        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/priority.h
    104108PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/priority.h

  • cpukit/score/cpu/arm/arm_exc_interrupt.S 

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/arm/arm_exc_interrupt.S,v
retrieving revision 1.5
diff -u -r1.5 arm_exc_interrupt.S
     
    3030#endif
    3131
    3232#include <rtems/asm.h>
     33#include <rtems/score/percpu.h>
    3334
    3435#define EXCHANGE_LR r4
    3536#define EXCHANGE_SPSR r5
    … …  
    4243#define CONTEXT_LIST {r0, r1, r2, r3, EXCHANGE_LR, EXCHANGE_SPSR, r12}
    4344#define CONTEXT_SIZE 28
    4445
    45 .extern _ISR_Nest_level
    46 .extern _ISR_Signals_to_thread_executing
    47 .extern _ISR_Thread_dispatch
    4846.extern _Thread_Dispatch_disable_level
    4947
    5048.extern bsp_interrupt_dispatch
    … …  
    8179        ldmia   r1, EXCHANGE_LIST
    8280
    8381        /* Get interrupt nest level */
    84         ldr     r0, =_ISR_Nest_level
     82        ldr     r0, =ISR_NEST_LEVEL
    8583        ldr     r2, [r0]
    8684
    8785        /* Switch stack if necessary and save original stack pointer */
    … …  
    105103        bl      bsp_interrupt_dispatch
    106104
    107105        /* Decrement interrupt nest and thread dispatch disable level */
    108         ldr     r0, =_ISR_Nest_level
     106        ldr     r0, =ISR_NEST_LEVEL
    109107        ldr     r1, =_Thread_Dispatch_disable_level
    110108        ldr     r2, [r0]
    111109        ldr     r3, [r1]
    … …  
    124122        bne     thread_dispatch_done
    125123
    126124        /* Check context switch necessary */
    127         ldr     r0, =_Context_Switch_necessary
    128         ldrb    r1, [r0]
    129         ldr     r0, =_ISR_Signals_to_thread_executing
    130         cmp     r1, #0
    131         bne     do_thread_dispatch
    132 
    133         /* Check ISR signals to thread executing */
     125        ldr     r0, =DISPATCH_NEEDED
    134126        ldrb    r1, [r0]
    135127        cmp     r1, #0
    136128        beq     thread_dispatch_done
    … …  
    142134
    143135do_thread_dispatch:
    144136
    145         /* Clear ISR signals to thread executing */
    146         strb    r3, [r0]
    147 
    148137        /* Thread dispatch */
    149138        bl      _Thread_Dispatch
    150139

  • cpukit/score/cpu/avr/cpu_asm.S 

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/avr/cpu_asm.S,v
retrieving revision 1.9
diff -u -r1.9 cpu_asm.S
     
    2828
    2929#include <rtems/asm.h>
    3030#include <avr/sfr_defs.h>
     31#include <rtems/score/percpu.h>
    3132
    3233
    3334#define jmpb_hi         r25
    … …  
    438439   *    goto the label "exit interrupt (simple case)"
    439440   *
    440441   *  if ( _Thread_Dispatch_disable_level )
    441    *    _ISR_Signals_to_thread_executing = FALSE;
    442442   *    goto the label "exit interrupt (simple case)"
    443443   *
    444    *  if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) {
    445    *    _ISR_Signals_to_thread_executing = FALSE;
     444   *  if ( _Context_Switch_necessary ) {
    446445   *    call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
    447446   *    prepare to get out of interrupt
    448447   *    return from interrupt  (maybe to _ISR_Dispatch)

  • cpukit/score/cpu/avr/rtems/score/cpu.h 

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/avr/rtems/score/cpu.h,v
retrieving revision 1.25
diff -u -r1.25 cpu.h
     
    456456SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
    457457
    458458/*
    459  *  On some CPUs, RTEMS supports a software managed interrupt stack.
    460  *  This stack is allocated by the Interrupt Manager and the switch
    461  *  is performed in _ISR_Handler.  These variables contain pointers
    462  *  to the lowest and highest addresses in the chunk of memory allocated
    463  *  for the interrupt stack.  Since it is unknown whether the stack
    464  *  grows up or down (in general), this give the CPU dependent
    465  *  code the option of picking the version it wants to use.
    466  *
    467  *  NOTE: These two variables are required if the macro
    468  *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
    469  *
    470  *  AVR Specific Information:
    471  *
    472  *  XXX document implementation including references if appropriate
    473  */
    474 
    475 SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
    476 SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
    477 
    478 /*
    479459 *  Nothing prevents the porter from declaring more CPU specific variables.
    480460 *
    481461 *  AVR Specific Information:

  • cpukit/score/cpu/bfin/cpu_asm.S 

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/bfin/cpu_asm.S,v
retrieving revision 1.10
diff -u -r1.10 cpu_asm.S
     
    2828#include <rtems/score/cpu_asm.h>
    2929#include <rtems/score/bfin.h>
    3030#include <rtems/bfin/bfin.h>
     31#include <rtems/score/percpu.h>
    3132
    3233#define LO(con32) ((con32) & 0xFFFF)
    3334#define HI(con32) (((con32) >> 16) & 0xFFFF)
    … …  
    313314
    314315
    315316        .globl SYM(_ISR_Handler)
    316         .extern SYM(_CPU_Interrupt_stack_high)
    317         .extern SYM(_ISR_Nest_level)
    318         .extern SYM(_Thread_Dispatch_disable_level)
    319         .extern SYM(_Context_Switch_necessary)
    320         .extern SYM(_ISR_Signals_to_thread_executing)
    321317SYM(_ISR_Handler):
     318        .extern SYM(_Thread_Dispatch_disable_level)
    322319        /* all interrupts are disabled at this point */
    323320        /* the following few items are pushed onto the task stack for at
    324321           most one interrupt; nested interrupts will be using the interrupt
    … …  
    328325        [--sp] = p0;
    329326        [--sp] = r1;
    330327        [--sp] = r0;
    331         p0.h = SYM(_ISR_Nest_level);
    332         p0.l = SYM(_ISR_Nest_level);
     328        p0.h = ISR_NEST_LEVEL;
     329        p0.l = ISR_NEST_LEVEL;
    333330        r0 = [p0];
    334331        r0 += 1;
    335332        [p0] = r0;
    … …  
    337334        if !cc jump noStackSwitch;
    338335        /* setup interrupt stack */
    339336        r0 = sp;
    340         p0.h = SYM(_CPU_Interrupt_stack_high);
    341         p0.l = SYM(_CPU_Interrupt_stack_high);
     337        p0.h = INTERRUPT_STACK_HIGH;
     338        p0.l = INTERRUPT_STACK_HIGH;
    342339        sp = [p0];
    343340        [--sp] = r0;
    344341noStackSwitch:
    … …  
    452449        /* this disables interrupts again */
    453450        reti = [sp++];
    454451
    455         p0.h = SYM(_ISR_Nest_level);
    456         p0.l = SYM(_ISR_Nest_level);
     452        p0.h = ISR_NEST_LEVEL;
     453        p0.l = ISR_NEST_LEVEL;
    457454        r0 = [p0];
    458455        r0 += -1;
    459456        [p0] = r0;
    … …  
    473470        if !cc jump noDispatch
    474471
    475472        /* do thread dispatch if necessary */
    476         p0.h = SYM(_Context_Switch_necessary);
    477         p0.l = SYM(_Context_Switch_necessary);
    478         r0 = B[p0] (Z);
    479         cc = r0 == 0;
    480         p0.h = SYM(_ISR_Signals_to_thread_executing);
    481         p0.l = SYM(_ISR_Signals_to_thread_executing);
    482         if !cc jump doDispatch
     473        p0.h = DISPATCH_NEEDED;
     474        p0.l = DISPATCH_NEEDED;
    483475        r0 = B[p0] (Z);
    484476        cc = r0 == 0;
    485477        if cc jump noDispatch

  • cpukit/score/cpu/bfin/rtems/score/cpu.h 

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/bfin/rtems/score/cpu.h,v
retrieving revision 1.19
diff -u -r1.19 cpu.h
     
    544544 *  XXX document implementation including references if appropriate
    545545 */
    546546
    547 /**
    548  *  @ingroup CPUInterrupt
    549  *  This variable points to the lowest physical address of the interrupt
    550  *  stack.
    551  */
    552 SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
    553 
    554 /**
    555  *  @ingroup CPUInterrupt
    556  *  This variable points to the lowest physical address of the interrupt
    557  *  stack.
    558  */
    559 SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
    560 
    561547/*
    562548 *  Nothing prevents the porter from declaring more CPU specific variables.
    563549 *

  • cpukit/score/cpu/h8300/cpu_asm.S 

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/h8300/cpu_asm.S,v
retrieving revision 1.11
diff -u -r1.11 cpu_asm.S
     
    1818#include "config.h"
    1919#endif
    2020
     21#include <rtems/asm.h>
     22#include <rtems/score/percpu.h>
    2123
    2224;.equ   RUNCONTEXT_ARG,  er0
    2325;.equ   HEIRCONTEXT_ARG, er1
    … …  
    5153
    5254        .align 2
    5355
    54         .global __CPU_Context_switch
     56        .global SYM(_CPU_Context_switch)
    5557
    56 __CPU_Context_switch:
     58SYM(_CPU_Context_switch):
    5759        /* Save Context */
    5860#if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__)
    5961        stc.w   ccr,@(0:16,er0)
    … …  
    8082
    8183        .align 2
    8284
    83         .global __CPU_Context_restore
     85        .global SYM(_CPU_Context_restore)
    8486
    85 __CPU_Context_restore:
     87SYM(_CPU_Context_restore):
    8688       
    8789#if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__)
    8890        mov.l   er0,er1
    … …  
    100102       
    101103*/
    102104        .align 2
    103         .global __ISR_Handler
    104         .extern __ISR_Nest_level
    105         .extern __Vector_table
    106         .extern __Context_switch_necessary
     105        .global SYM(_ISR_Handler)
     106        .extern SYM(_Vector_table)
    107107
    108108       
    109 __ISR_Handler:
     109SYM(_ISR_Handler):
    110110#if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__)
    111111        mov.l   er1,@-er7
    112112        mov.l   er2,@-er7
    … …  
    118118/*  Set IRQ Stack */
    119119        orc             #0xc0,ccr
    120120        mov.l   er7,er6         ; save stack pointer
    121         mov.l   @__ISR_Nest_level,er1
     121        mov.l   @ISR_NEST_LEVEL,er1
    122122        bne             nested
    123         mov.l   @__CPU_Interrupt_stack_high,er7
     123        mov.l   @INTERRUPT_STACK_HIGH,er7
    124124       
    125125nested:
    126126        mov.l   er6,@-er7       ; save sp so pop regardless of nest level
    127127       
    128128;; Inc  system counters
    129         mov.l   @__ISR_Nest_level,er1
     129        mov.l   @ISR_NEST_LEVEL,er1
    130130        inc.l   #1,er1
    131         mov.l   er1,@__ISR_Nest_level
    132         mov.l   @__Thread_Dispatch_disable_level,er1
     131        mov.l   er1,@ISR_NEST_LEVEL
     132        mov.l   @SYM(_Thread_Dispatch_disable_level),er1
    133133        inc.l   #1,er1
    134         mov.l   er1,@__Thread_Dispatch_disable_level
     134        mov.l   er1,@SYM(_Thread_Dispatch_disable_level)
    135135       
    136136/* Vector to ISR */
    137137
    138         mov.l   @__ISR_Vector_table,er1
     138        mov.l   @SYM(_ISR_Vector_table),er1
    139139        mov             er0,er2 ; copy vector
    140140        shll.l  er2
    141141        shll.l  er2             ; vector = vector * 4 (sizeof(int))
    … …  
    144144        jsr             @er1    ; er0 = arg1 =vector
    145145       
    146146        orc             #0xc0,ccr
    147         mov.l   @__ISR_Nest_level,er1
     147        mov.l   @ISR_NEST_LEVEL,er1
    148148        dec.l   #1,er1
    149         mov.l   er1,@__ISR_Nest_level
    150         mov.l   @__Thread_Dispatch_disable_level,er1
     149        mov.l   er1,@ISR_NEST_LEVEL
     150        mov.l   @SYM(_Thread_Dispatch_disable_level),er1
    151151        dec.l   #1,er1
    152         mov.l   er1,@__Thread_Dispatch_disable_level
    153         bne             exit
     152        mov.l   er1,@SYM(_Thread_Dispatch_disable_level)
     153        bne     exit
    154154       
    155         mov.b   @__Context_Switch_necessary,er1
    156         bne             bframe          ; If yes then dispatch next task
    157        
    158         mov.b   @__ISR_Signals_to_thread_executing,er1
    159         beq             exit            ; If no signals waiting
     155        mov.b   @DISPATCH_NEEDED,er1
     156        beq     exit            ; If no then exit
    160157
    161158        /* Context switch here through ISR_Dispatch */
    162        
    163159bframe:
    164         orc             #0xc0,ccr
     160        orc     #0xc0,ccr
    165161/*      Pop Stack       */
    166         mov             @er7+,er6
    167         mov             er6,er7
    168         mov.l   #0,er2
    169         mov.l   er2,@__ISR_Signals_to_thread_executing
     162        mov     @er7+,er6
     163        mov     er6,er7
    170164
    171165        /* Set up IRQ stack frame and dispatch to _ISR_Dispatch */
    172166       
    173167        mov.l   #0xc0000000,er2         /* Disable IRQ */
    174         or.l    #_ISR_Dispatch,er2
     168        or.l    #SYM(_ISR_Dispatch),er2
    175169        mov.l   er2,@-er7
    176170        rte
    177171
    … …  
    200194*/
    201195
    202196        .align 2
    203         .global _ISR_Dispatch
     197        .global SYM(_ISR_Dispatch)
    204198
    205 _ISR_Dispatch:
     199SYM(_ISR_Dispatch):
    206200       
    207201#if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__)
    208         jsr             @__Thread_Dispatch
     202        jsr             @SYM(_Thread_Dispatch)
    209203        mov             @er7+,er6
    210204        mov             @er7+,er5
    211205        mov             @er7+,er4
    … …  
    218212       
    219213
    220214        .align 2
    221         .global __CPU_Context_save_fp
     215        .global SYM(_CPU_Context_save_fp)
    222216
    223 __CPU_Context_save_fp:
     217SYM(_CPU_Context_save_fp):
    224218        rts
    225219
    226220
    227221        .align 2
    228         .global __CPU_Context_restore_fp
     222        .global SYM(_CPU_Context_restore_fp)
    229223
    230 __CPU_Context_restore_fp:
     224SYM(_CPU_Context_restore_fp):
    231225        rts

  • cpukit/score/cpu/h8300/rtems/asm.h 

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/h8300/rtems/asm.h,v
retrieving revision 1.8
diff -u -r1.8 asm.h
     
    3737 *  Indicate we are in an assembly file and get the basic CPU definitions.
    3838 */
    3939
    40 #define ASM
    4140#include <rtems/score/h8300.h>
    4241
    4342/*
    … …  
    116115#define EXTERN(sym) .globl SYM (sym)
    117116
    118117#endif
    119 
    120         asm( \".h8300h\" );

  • cpukit/score/cpu/h8300/rtems/score/cpu.h 

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/h8300/rtems/score/cpu.h,v
retrieving revision 1.39
diff -u -r1.39 cpu.h
     
    432432SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
    433433
    434434/*
    435  *  On some CPUs, RTEMS supports a software managed interrupt stack.
    436  *  This stack is allocated by the Interrupt Manager and the switch
    437  *  is performed in _ISR_Handler.  These variables contain pointers
    438  *  to the lowest and highest addresses in the chunk of memory allocated
    439  *  for the interrupt stack.  Since it is unknown whether the stack
    440  *  grows up or down (in general), this give the CPU dependent
    441  *  code the option of picking the version it wants to use.
    442  *
    443  *  NOTE: These two variables are required if the macro
    444  *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
    445  *
    446  *  H8300 Specific Information:
    447  *
    448  *  XXX
    449  */
    450 
    451 SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
    452 SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
    453 
    454 /*
    455435 *  Nothing prevents the porter from declaring more CPU specific variables.
    456436 *
    457437 *  H8300 Specific Information:

  • cpukit/score/cpu/lm32/irq.c 

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/lm32/irq.c,v
retrieving revision 1.4
diff -u -r1.4 irq.c
     
    1919
    2020#include <rtems/system.h>
    2121#include <rtems/score/cpu.h>
    22 #include <rtems/score/isr.h>
    2322#include <rtems/score/thread.h>
     23#include <rtems/score/isr.h>
     24#include <rtems/score/percpu.h>
    2425
    2526/*
    2627 *  This routine provides the RTEMS interrupt management.
    … …  
    7778  if ( _ISR_Nest_level )
    7879    return;
    7980
    80   if ( _Thread_Dispatch_disable_level ) {
    81     _ISR_Signals_to_thread_executing = FALSE;
    82     return;
    83   }
    84 
    85   if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) {
    86     _ISR_Signals_to_thread_executing = FALSE;
     81  if ( _Context_Switch_necessary ) {
    8782
    8883    /* save off our stack frame so the context switcher can get to it */
    8984    _exception_stack_frame = ifr;

  • cpukit/score/cpu/lm32/rtems/score/cpu.h 

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/lm32/rtems/score/cpu.h,v
retrieving revision 1.8
diff -u -r1.8 cpu.h
     
    560560 *  XXX document implementation including references if appropriate
    561561 */
    562562
    563 /**
    564  *  @ingroup CPUInterrupt
    565  *  This variable points to the lowest physical address of the interrupt
    566  *  stack.
    567  */
    568 SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
    569 
    570 /**
    571  *  @ingroup CPUInterrupt
    572  *  This variable points to the lowest physical address of the interrupt
    573  *  stack.
    574  */
    575 SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
    576 
    577563/*
    578564 *  Nothing prevents the porter from declaring more CPU specific variables.
    579565 *

  • cpukit/score/cpu/m32c/cpu_asm.c 

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/m32c/cpu_asm.c,v
retrieving revision 1.5
diff -u -r1.5 cpu_asm.c
     
    8787   *    goto the label "exit interrupt (simple case)"
    8888   *
    8989   *  if ( _Thread_Dispatch_disable_level )
    90    *    _ISR_Signals_to_thread_executing = FALSE;
    9190   *    goto the label "exit interrupt (simple case)"
    9291   *
    93    *  if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) {
    94    *    _ISR_Signals_to_thread_executing = FALSE;
     92   *  if ( _Context_Switch_necessary ) {
    9593   *    call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
    9694   *    prepare to get out of interrupt
    9795   *    return from interrupt  (maybe to _ISR_Dispatch)

  • cpukit/score/cpu/m32c/rtems/score/cpu.h 

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/m32c/rtems/score/cpu.h,v
retrieving revision 1.7
diff -u -r1.7 cpu.h
     
    522522 *  XXX document implementation including references if appropriate
    523523 */
    524524
    525 /**
    526  *  @ingroup CPUInterrupt
    527  *  This variable points to the lowest physical address of the interrupt
    528  *  stack.
    529  */
    530 SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
    531 
    532 /**
    533  *  @ingroup CPUInterrupt
    534  *  This variable points to the lowest physical address of the interrupt
    535  *  stack.
    536  */
    537 SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
    538 
    539525/*
    540526 *  Nothing prevents the porter from declaring more CPU specific variables.
    541527 *

  • cpukit/score/cpu/m32r/cpu_asm.c 

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/m32r/cpu_asm.c,v
retrieving revision 1.3
diff -u -r1.3 cpu_asm.c
     
    7777   *    goto the label "exit interrupt (simple case)"
    7878   *
    7979   *  if ( _Thread_Dispatch_disable_level )
    80    *    _ISR_Signals_to_thread_executing = FALSE;
    8180   *    goto the label "exit interrupt (simple case)"
    8281   *
    83    *  if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) {
    84    *    _ISR_Signals_to_thread_executing = FALSE;
     82   *  if ( _Context_Switch_necessary ) {
    8583   *    call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
    8684   *    prepare to get out of interrupt
    8785   *    return from interrupt  (maybe to _ISR_Dispatch)

  • cpukit/score/cpu/m32r/rtems/score/cpu.h 

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/m32r/rtems/score/cpu.h,v
retrieving revision 1.4
diff -u -r1.4 cpu.h
     
    555555 *  XXX document implementation including references if appropriate
    556556 */
    557557
    558 /**
    559  *  @ingroup CPUInterrupt
    560  *  This variable points to the lowest physical address of the interrupt
    561  *  stack.
    562  */
    563 SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
    564 
    565 /**
    566  *  @ingroup CPUInterrupt
    567  *  This variable points to the lowest physical address of the interrupt
    568  *  stack.
    569  */
    570 SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
    571 
    572558/*
    573559 *  Nothing prevents the porter from declaring more CPU specific variables.
    574560 *

  • cpukit/score/cpu/m68k/cpu_asm.S 

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/m68k/cpu_asm.S,v
retrieving revision 1.18
diff -u -r1.18 cpu_asm.S
     
    1919#endif
    2020
    2121#include <rtems/asm.h>
     22#include <rtems/score/percpu.h>
    2223
    2324/*  void _CPU_Context_switch( run_context, heir_context )
    2425 *
    … …  
    263264
    264265#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 )
    265266        | Make a0 point just above interrupt stack
    266         movel   _CPU_Interrupt_stack_high,a0
    267         cmpl    _CPU_Interrupt_stack_low,a7  | stack below interrupt stack?
     267        movel   INTERRUPT_STACK_HIGH,a0
     268        cmpl    INTERRUPT_STACK_LOW,a7  | stack below interrupt stack?
    268269        bcs.b   1f                      | yes, switch to interrupt stack
    269270        cmpl    a0,a7                   | stack above interrupt stack?
    270271        bcs.b   2f                      | no, do not switch stacks
    … …  
    2762772:
    277278#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */
    278279
    279         addql   #1,SYM(_ISR_Nest_level) | one nest level deeper
     280        addql   #1,ISR_NEST_LEVEL        | one nest level deeper
    280281
    281282        movel   SYM (_ISR_Vector_table),a0 | a0= base of RTEMS table
    282283#if ( M68K_HAS_PREINDEXING == 1 )
    … …  
    290291        movel   d0,a7@-                  | push vector number
    291292        jbsr    a0@                      | invoke the user ISR
    292293        addql   #4,a7                    | remove vector number
    293         subql   #1,SYM(_ISR_Nest_level)  | Reduce interrupt-nesting count
     294        subql   #1,ISR_NEST_LEVEL        | Reduce interrupt-nesting count
    294295
    295296#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 )
    296         movel   _CPU_Interrupt_stack_high,a0
     297        movel   INTERRUPT_STACK_HIGH,a0
    297298        subql   #4,a0
    298299        cmpl    a0,a7                   | At top of interrupt stack?
    299300        bne.b   1f                      | No, do not restore task stack pointer
    … …  
    322323        beq.b   exit
    323324  #endif
    324325#endif
    325         tstb    SYM (_Context_Switch_necessary)
     326        tstb    DISPATCH_NEEDED
    326327                                         | Is thread switch necessary?
    327         bne.b   bframe                   | Yes, invoke dispatcher
    328 
    329         tstb    SYM (_ISR_Signals_to_thread_executing)
    330                                          | signals sent to Run_thread
    331                                          |   while in interrupt handler?
    332328        beq.b   exit                     | No, then exit
    333329
    334 bframe: clrb    SYM (_ISR_Signals_to_thread_executing)
     330bframe:
    335331                                         | If sent, will be processed
    336332#if ( M68K_HAS_SEPARATE_STACKS == 1 )
    337333        movec   msp,a0                   | a0 = master stack pointer

  • cpukit/score/cpu/m68k/rtems/score/cpu.h 

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/m68k/rtems/score/cpu.h,v
retrieving revision 1.42
diff -u -r1.42 cpu.h
     
    308308
    309309/* variables */
    310310
    311 SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
    312 SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
    313 
    314311extern void*                     _VBR;
    315312
    316313#if ( M68K_HAS_VBR == 0 )

  • cpukit/score/cpu/mips/cpu_asm.S 

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/mips/cpu_asm.S,v
retrieving revision 1.41
diff -u -r1.41 cpu_asm.S
     
    5757#include <rtems/asm.h>
    5858#include <rtems/mips/iregdef.h>
    5959#include <rtems/mips/idtcpu.h>
     60#include <rtems/score/percpu.h>
    6061
    6162#define ASSEMBLY_ONLY
    6263#include <rtems/score/cpu.h>
    … …  
    201202
    202203ASM_EXTERN(__exceptionStackFrame, SZ_INT)
    203204
    204 
    205 
    206205/*
    207206 *  _CPU_Context_save_fp_context
    208207 *
    … …  
    585584
    586585ENDFRAME(_CPU_Context_restore)
    587586
    588 
    589 ASM_EXTERN(_ISR_Nest_level,4)
    590587ASM_EXTERN(_Thread_Dispatch_disable_level,4)
    591 ASM_EXTERN(_Context_Switch_necessary,1)
    592 ASM_EXTERN(_ISR_Signals_to_thread_executing,1)
    593588ASM_EXTERN(_Thread_Executing,4)
    594589
    595590.extern _Thread_Dispatch
    596591.extern _ISR_Vector_table
    597592
    598 
    599 
    600 
    601 
    602593/*  void _DBG_Handler()
    603594 *
    604595 *  This routine services the (at least) MIPS1 debug vector,
    … …  
    606597 *  while optional, is best located here because its intrinsically
    607598 *  associated with exceptions in general & thus tied pretty
    608599 *  closely to _ISR_Handler.
    609  *
    610600 */
    611 
    612 
    613601FRAME(_DBG_Handler,sp,0,ra)
    614602        .set noreorder
    615603        la      k0,_ISR_Handler
    … …  
    618606        .set reorder
    619607ENDFRAME(_DBG_Handler)
    620608
    621 
    622 
    623 
    624 
    625609/*  void __ISR_Handler()
    626610 *
    627611 *  This routine provides the RTEMS interrupt management.
    … …  
    693677
    694678
    695679#ifdef INSTRUMENT_EXECUTING_THREAD
    696         lw t2, _Thread_Executing
     680        lw t2, THREAD_EXECUTING
    697681        NOP
    698682        sw t2, 0x8001FFF0
    699683#endif
    … …  
    904888  /*
    905889   *  _ISR_Nest_level++;
    906890   */
    907         lw      t0,_ISR_Nest_level
     891        lw      t0,ISR_NEST_LEVEL
    908892        NOP
    909893        add     t0,t0,1
    910         sw      t0,_ISR_Nest_level
     894        sw      t0,ISR_NEST_LEVEL
    911895  /*
    912896   *  _Thread_Dispatch_disable_level++;
    913897   */
    … …  
    940924  /*
    941925   *  --_ISR_Nest_level;
    942926   */
    943         lw      t2,_ISR_Nest_level
     927        lw      t2,ISR_NEST_LEVEL
    944928        NOP
    945929        add     t2,t2,-1
    946         sw      t2,_ISR_Nest_level
     930        sw      t2,ISR_NEST_LEVEL
    947931  /*
    948932   *  --_Thread_Dispatch_disable_level;
    949933   */
    … …  
    965949   *    restore stack
    966950   *  #endif
    967951   *
    968    *  if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing )
     952   *  if !_Context_Switch_necessary
    969953   *    goto the label "exit interrupt (simple case)"
    970954   */
    971         lbu     t0,_Context_Switch_necessary
    972         lbu     t1,_ISR_Signals_to_thread_executing
     955        lbu     t0,DISPATCH_NEEDED
    973956        NOP
    974         or      t0,t0,t1
     957        or      t0,t0,t0
    975958        beq     t0,zero,_ISR_Handler_exit
    976959        NOP
    977960
    978961
    979962
    980963#ifdef INSTRUMENT_EXECUTING_THREAD
    981         lw      t0,_Thread_Executing
     964        lw      t0,THREAD_EXECUTING
    982965        NOP
    983966        sw      t0,0x8001FFF4
    984967#endif
    … …  
    10681051
    10691052
    10701053#ifdef INSTRUMENT_EXECUTING_THREAD
    1071         lw      t0,_Thread_Executing
     1054        lw      t0,THREAD_EXECUTING
    10721055        NOP
    10731056        sw      t0,0x8001FFF8
    10741057#endif
    … …  
    10931076        /* restore context from stack */
    10941077
    10951078#ifdef INSTRUMENT_EXECUTING_THREAD
    1096         lw      t0,_Thread_Executing
     1079        lw      t0,THREAD_EXECUTING
    10971080        NOP
    10981081        sw      t0, 0x8001FFFC
    10991082#endif

  • cpukit/score/cpu/mips/rtems/score/cpu.h 

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/mips/rtems/score/cpu.h,v
retrieving revision 1.56
diff -u -r1.56 cpu.h
     
    617617SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
    618618
    619619/*
    620  *  On some CPUs, RTEMS supports a software managed interrupt stack.
    621  *  This stack is allocated by the Interrupt Manager and the switch
    622  *  is performed in _ISR_Handler.  These variables contain pointers
    623  *  to the lowest and highest addresses in the chunk of memory allocated
    624  *  for the interrupt stack.  Since it is unknown whether the stack
    625  *  grows up or down (in general), this give the CPU dependent
    626  *  code the option of picking the version it wants to use.
    627  *
    628  *  NOTE: These two variables are required if the macro
    629  *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
    630  */
    631 
    632 SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
    633 SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
    634 
    635 /*
    636620 *  Nothing prevents the porter from declaring more CPU specific variables.
    637621 */
    638622

  • cpukit/score/cpu/nios2/irq.c 

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/nios2/irq.c,v
retrieving revision 1.5
diff -u -r1.5 irq.c
     
    6464
    6565  _ISR_Nest_level--;
    6666
    67   if( _ISR_Nest_level == 0)
    68   {
     67  if( _ISR_Nest_level == 0) {
    6968#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
    7069    stack_ptr = _old_stack_ptr;
    7170#endif
    7271
    7372    if( _Thread_Dispatch_disable_level == 0 )
    7473    {
    75       if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing )
    76       {
    77         _ISR_Signals_to_thread_executing = FALSE;
     74      if ( _Context_Switch_necessary ) {
    7875        _CPU_ISR_Enable( level );
    7976        _Thread_Dispatch();
    8077        /* may have switched to another task and not return here immed. */
    8178        _CPU_ISR_Disable( level ); /* Keep _pairs_ of Enable/Disable */
    8279      }
    8380    }
    84     else
    85     {
    86       _ISR_Signals_to_thread_executing = FALSE;
    87     };
    88   };
     81  }
    8982
    9083  _CPU_ISR_Enable( level );
    9184}

  • cpukit/score/cpu/nios2/rtems/score/cpu.h 

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/nios2/rtems/score/cpu.h,v
retrieving revision 1.13
diff -u -r1.13 cpu.h
     
    590590 *  XXX document implementation including references if appropriate
    591591 */
    592592
    593 /**
    594  *  @ingroup CPUInterrupt
    595  *  This variable points to the lowest physical address of the interrupt
    596  *  stack.
    597  */
    598 SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
    599 
    600 /**
    601  *  @ingroup CPUInterrupt
    602  *  This variable points to the lowest physical address of the interrupt
    603  *  stack.
    604  */
    605 SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
    606 
    607593/*
    608594 *  Nothing prevents the porter from declaring more CPU specific variables.
    609595 *

  • cpukit/score/cpu/no_cpu/cpu_asm.c 

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/no_cpu/cpu_asm.c,v
retrieving revision 1.18
diff -u -r1.18 cpu_asm.c
     
    166166   *    goto the label "exit interrupt (simple case)"
    167167   *
    168168   *  if ( _Thread_Dispatch_disable_level )
    169    *    _ISR_Signals_to_thread_executing = FALSE;
    170169   *    goto the label "exit interrupt (simple case)"
    171170   *
    172    *  if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) {
    173    *    _ISR_Signals_to_thread_executing = FALSE;
     171   *  if ( _Context_Switch_necessary ) {
    174172   *    call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
    175173   *    prepare to get out of interrupt
    176174   *    return from interrupt  (maybe to _ISR_Dispatch)

  • cpukit/score/cpu/no_cpu/rtems/score/cpu.h 

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/no_cpu/rtems/score/cpu.h,v
retrieving revision 1.31
diff -u -r1.31 cpu.h
     
    548548 *  XXX document implementation including references if appropriate
    549549 */
    550550
    551 /**
    552  *  @ingroup CPUInterrupt
    553  *  This variable points to the lowest physical address of the interrupt
    554  *  stack.
    555  */
    556 SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
    557 
    558 /**
    559  *  @ingroup CPUInterrupt
    560  *  This variable points to the lowest physical address of the interrupt
    561  *  stack.
    562  */
    563 SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
    564 
    565551/*
    566552 *  Nothing prevents the porter from declaring more CPU specific variables.
    567553 *

  • cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h 

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h,v
retrieving revision 1.38
diff -u -r1.38 cpu.h
     
    163163
    164164/* EXTERN Context_Control_fp  _CPU_Null_fp_context; */
    165165
    166 /*
    167  *  On some CPUs, RTEMS supports a software managed interrupt stack.
    168  *  This stack is allocated by the Interrupt Manager and the switch
    169  *  is performed in _ISR_Handler.  These variables contain pointers
    170  *  to the lowest and highest addresses in the chunk of memory allocated
    171  *  for the interrupt stack.  Since it is unknown whether the stack
    172  *  grows up or down (in general), this give the CPU dependent
    173  *  code the option of picking the version it wants to use.
    174  *
    175  *  NOTE: These two variables are required if the macro
    176  *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
    177  */
    178 
    179 SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
    180 SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
    181 
    182166#endif /* ndef ASM */
    183167
    184168/*

  • cpukit/score/cpu/sh/rtems/score/cpu.h 

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/sh/rtems/score/cpu.h,v
retrieving revision 1.31
diff -u -r1.31 cpu.h
     
    413413#endif
    414414
    415415/*
    416  *  On some CPUs, RTEMS supports a software managed interrupt stack.
    417  *  This stack is allocated by the Interrupt Manager and the switch
    418  *  is performed in _ISR_Handler.  These variables contain pointers
    419  *  to the lowest and highest addresses in the chunk of memory allocated
    420  *  for the interrupt stack.  Since it is unknown whether the stack
    421  *  grows up or down (in general), this give the CPU dependent
    422  *  code the option of picking the version it wants to use.
    423  *
    424  *  NOTE: These two variables are required if the macro
    425  *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
    426  */
    427 
    428 SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
    429 SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
    430 
    431 /*
    432416 *  Nothing prevents the porter from declaring more CPU specific variables.
    433417 */
    434418

  • cpukit/score/cpu/sparc/cpu_asm.S 

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/sparc/cpu_asm.S,v
retrieving revision 1.17
diff -u -r1.17 cpu_asm.S
     
    44 *  in an specific CPU port of RTEMS.  These algorithms must be implemented
    55 *  in assembly language.
    66 *
    7  *  COPYRIGHT (c) 1989-2007.
     7 *  COPYRIGHT (c) 1989-2010.
    88 *  On-Line Applications Research Corporation (OAR).
    99 *
    1010 *  The license and distribution terms for this file may be
    … …  
    2626#endif
    2727
    2828#include <rtems/asm.h>
     29#include <rtems/system.h>
    2930
    3031#if (SPARC_HAS_FPU == 1)
    3132
    … …  
    471472         *  Register usage for this section:
    472473         *
    473474         *    l4 = _Thread_Dispatch_disable_level pointer
    474          *    l5 = _ISR_Nest_level pointer
     475         *    l5 = per cpu info pointer
    475476         *    l6 = _Thread_Dispatch_disable_level value
    476477         *    l7 = _ISR_Nest_level value
    477478         *
    … …  
    481482
    482483        sethi    %hi(SYM(_Thread_Dispatch_disable_level)), %l4
    483484        ld       [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))], %l6
    484         sethi    %hi(SYM(_ISR_Nest_level)), %l5
    485         ld       [%l5 + %lo(SYM(_ISR_Nest_level))], %l7
     485
     486        sethi    %hi(_Per_CPU_Information), %l5
     487        add      %l5, %lo(_Per_CPU_Information), %l5
     488
     489        ld       [%l5 + PER_CPU_ISR_NEST_LEVEL], %l7
    486490
    487491        add      %l6, 1, %l6
    488492        st       %l6, [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))]
    489493
    490494        add      %l7, 1, %l7
    491         st       %l7, [%l5 + %lo(SYM(_ISR_Nest_level))]
     495        st       %l7, [%l5 + PER_CPU_ISR_NEST_LEVEL]
    492496
    493497        /*
    494498         *  If ISR nest level was zero (now 1), then switch stack.
    … …  
    498502        subcc    %l7, 1, %l7             ! outermost interrupt handler?
    499503        bnz      dont_switch_stacks      ! No, then do not switch stacks
    500504
    501         sethi    %hi(SYM(_CPU_Interrupt_stack_high)), %g4
    502         ld       [%g4 + %lo(SYM(_CPU_Interrupt_stack_high))], %sp
     505        nop
     506        ld       [%l5 + PER_CPU_INTERRUPT_STACK_HIGH], %sp
    503507
    504508dont_switch_stacks:
    505509        /*
    … …  
    644648        sub      %l6, 1, %l6
    645649        st       %l6, [%l4 + %lo(SYM(_Thread_Dispatch_disable_level))]
    646650
    647         st       %l7, [%l5 + %lo(SYM(_ISR_Nest_level))]
     651        st       %l7, [%l5 + PER_CPU_ISR_NEST_LEVEL]
    648652
    649653        /*
    650654         *  If dispatching is disabled (includes nested interrupt case),
    … …  
    660664        ld       [%l6 + %lo(SYM(_CPU_ISR_Dispatch_disable))], %l7
    661665        orcc     %l7, %g0, %g0   ! Is this thread already doing an ISR?
    662666        bnz      simple_return   ! Yes, then do a "simple" exit
    663         ! NOTE: Use the delay slot
    664         sethi    %hi(SYM(_Context_Switch_necessary)), %l4
     667        nop
    665668
    666669
    667670        /*
    … …  
    669672         *  return to the interrupt dispatcher.
    670673         */
    671674
    672         ldub     [%l4 + %lo(SYM(_Context_Switch_necessary))], %l5
     675        ldub     [%l5 + PER_CPU_DISPATCH_NEEDED], %l5
    673676
    674677        orcc     %l5, %g0, %g0   ! Is thread switch necessary?
    675         bnz      SYM(_ISR_Dispatch) ! yes, then invoke the dispatcher
    676         ! NOTE: Use the delay slot
    677         sethi    %hi(SYM(_ISR_Signals_to_thread_executing)), %l6
    678 
    679         /*
    680          *  Finally, check to see if signals were sent to the currently
    681          *  executing task.  If so, we need to invoke the interrupt dispatcher.
    682          */
    683 
    684         ldub     [%l6 + %lo(SYM(_ISR_Signals_to_thread_executing))], %l7
    685 
    686         orcc     %l7, %g0, %g0   ! Were signals sent to the currently
    687                                  !   executing thread?
    688         bz       simple_return   ! yes, then invoke the dispatcher
    689                                  ! use the delay slot to clear the signals
    690                                  !   to the currently executing task flag
    691         st       %g0, [%l6 + %lo(SYM(_ISR_Signals_to_thread_executing))]
    692 
     678        bz       simple_return   ! no, then do a simple return
     679        nop
    693680
    694681        /*
    695682         *  Invoke interrupt dispatcher.
    … …  
    737724         *  _Thread_Dispatch before leaving this ISR Dispatch context.
    738725         */
    739726
    740         sethi    %hi(SYM(_Context_Switch_necessary)), %l4
    741         ldub     [%l4 + %lo(SYM(_Context_Switch_necessary))], %l5
    742 
    743         ! NOTE: Use some of delay slot to start loading this
    744         sethi    %hi(SYM(_ISR_Signals_to_thread_executing)), %l6
    745         ldub     [%l6 + %lo(SYM(_ISR_Signals_to_thread_executing))], %l7
     727        sethi    %hi(_Per_CPU_Information), %l5
     728        add      %l5, %lo(_Per_CPU_Information), %l5
    746729
    747         orcc     %l5, %g0, %g0   ! Is thread switch necessary?
    748         bnz      dispatchAgain   ! yes, then invoke the dispatcher AGAIN
    749         ! NOTE: Use the delay slot to catch the orcc below
     730        ldub     [%l5 + PER_CPU_DISPATCH_NEEDED], %l7
    750731
    751         /*
    752          *  Finally, check to see if signals were sent to the currently
    753          *  executing task.  If so, we need to invoke the interrupt dispatcher.
    754          */
    755 
    756         ! NOTE: Delay slots above were used to perform the load AND
    757         !       this orcc falls into the delay slot for bnz above
    758         orcc     %l7, %g0, %g0   ! Were signals sent to the currently
    759                                  !   executing thread?
     732        orcc     %l7, %g0, %g0    ! Is thread switch necesary?
    760733        bz       allow_nest_again ! No, then clear out and return
    761         ! NOTE: use the delay slot from the bz to load 3 into %g1
     734        nop
    762735
    763736        ! Yes, then invoke the dispatcher
    764737dispatchAgain:

  • cpukit/score/cpu/sparc/rtems/score/cpu.h 

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/sparc/rtems/score/cpu.h,v
retrieving revision 1.35
diff -u -r1.35 cpu.h
     
    523523SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context CPU_STRUCTURE_ALIGNMENT;
    524524
    525525/*
    526  *  This stack is allocated by the Interrupt Manager and the switch
    527  *  is performed in _ISR_Handler.  These variables contain pointers
    528  *  to the lowest and highest addresses in the chunk of memory allocated
    529  *  for the interrupt stack.  Since it is unknown whether the stack
    530  *  grows up or down (in general), this give the CPU dependent
    531  *  code the option of picking the version it wants to use.  Thus
    532  *  both must be present if either is.
    533  *
    534  *  The SPARC supports a software based interrupt stack and these
    535  *  are required.
    536  */
    537 
    538 SCORE_EXTERN void *_CPU_Interrupt_stack_low;
    539 SCORE_EXTERN void *_CPU_Interrupt_stack_high;
    540 
    541 /*
    542526 *  This flag is context switched with each thread.  It indicates
    543527 *  that THIS thread has an _ISR_Dispatch stack frame on its stack.
    544528 *  By using this flag, we can avoid nesting more interrupt dispatching
    … …  
    965949  Context_Control_fp **fp_context_ptr
    966950);
    967951
     952
    968953/*
    969954 *  CPU_swap_u32
    970955 *

  • cpukit/score/include/rtems/system.h 

    RCS file: /usr1/CVS/rtems/cpukit/score/include/rtems/system.h,v
retrieving revision 1.64
diff -u -r1.64 system.h
     
    169169#include <stdint.h>
    170170#endif
    171171#include <rtems/score/cpu.h>        /* processor specific information */
     172#include <rtems/score/percpu.h>
    172173
    173174#ifndef ASM
    174175/**

  • cpukit/score/include/rtems/score/context.h 

    RCS file: /usr1/CVS/rtems/cpukit/score/include/rtems/score/context.h,v
retrieving revision 1.21
diff -u -r1.21 context.h
     
    2323 *
    2424 *  This handler encapsulates functionality which abstracts thread context
    2525 *  management in a portable manner.
     26 *
     27 *  The context switch needed variable is contained in the per cpu
     28 *  data structure.
    2629 */
    2730/**@{*/
    2831
    … …  
    4144#define CONTEXT_FP_SIZE CPU_CONTEXT_FP_SIZE
    4245
    4346/**
    44  *  @brief Is Context Switch Needed?
    45  *
    46  *  This variable is set to true when a reschedule operation
    47  *  has determined that the processor should be taken away from the
    48  *  currently executing thread and given to the heir thread.
    49  */
    50 
    51 SCORE_EXTERN volatile bool _Context_Switch_necessary;
    52 
    53 /**
    5447 *  @brief Initialize Context Area
    5548 *  This routine initializes @a _the_context such that the stack
    5649 *  pointer, interrupt level, and entry point are correct for the

  • cpukit/score/include/rtems/score/isr.h 

    RCS file: /usr1/CVS/rtems/cpukit/score/include/rtems/score/isr.h,v
retrieving revision 1.31
diff -u -r1.31 isr.h
     
    2121#ifndef _RTEMS_SCORE_ISR_H
    2222#define _RTEMS_SCORE_ISR_H
    2323
     24#include <rtems/score/percpu.h>
     25
    2426/**
    2527 *  @defgroup ScoreISR ISR Handler
    2628 *
    2729 *  This handler encapsulates functionality which provides the foundation
    2830 *  ISR services used in all of the APIs supported by RTEMS.
     31 *
     32 *  The ISR Nest level counter variable is maintained as part of the
     33 *  per cpu data structure.
    2934 */
    3035/**@{*/
    3136
    … …  
    7580 */
    7681#define ISR_INTERRUPT_MAXIMUM_VECTOR_NUMBER  CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER
    7782
    78 /**
    79  *  The following is true if signals have been sent to the currently
    80  *  executing thread by an ISR handler.
    81  */
    82 SCORE_EXTERN bool       _ISR_Signals_to_thread_executing;
    83 
    84 /**
    85  *  The following contains the interrupt service routine nest level.
    86  *  When this variable is zero, a thread is executing.
    87  */
    88 SCORE_EXTERN volatile uint32_t   _ISR_Nest_level;
    89 
    9083#if (CPU_SIMPLE_VECTORED_INTERRUPTS == TRUE)
    9184/**
    9285 *  The following declares the Vector Table.  Application

  • new file cpukit/score/include/rtems/score/percpu.h 

    RCS file: cpukit/score/include/rtems/score/percpu.h
diff -N cpukit/score/include/rtems/score/percpu.h
    - +  
     1/**
     2 *  @file  rtems/score/percpu.h
     3 *
     4 *  This include file defines the per CPU information required
     5 *  by RTEMS.
     6 */
     7
     8/*
     9 *  COPYRIGHT (c) 1989-2010.
     10 *  On-Line Applications Research Corporation (OAR).
     11 *
     12 *  The license and distribution terms for this file may be
     13 *  found in the file LICENSE in this distribution or at
     14 *  http://www.rtems.com/license/LICENSE.
     15 *
     16 *  $Id: percpu.h,v 1.1 2010/05/12 15:09:32 joel Exp $
     17 */
     18
     19#ifndef _RTEMS_PERCPU_H
     20#define _RTEMS_PERCPU_H
     21
     22#ifdef ASM
     23  #include <rtems/asm.h>
     24#endif
     25
     26/**
     27 *  @defgroup PerCPU RTEMS Per CPU Information
     28 *
     29 *  This defines the per CPU state information required by RTEMS
     30 *  and the BSP.  In an SMP configuration, there will be multiple
     31 *  instances of this data structure -- one per CPU -- and the
     32 *  current CPU number will be used as the index.
     33 */
     34
     35/**@{*/
     36
     37#ifdef __cplusplus
     38extern "C" {
     39#endif
     40
     41#ifndef ASM
     42
     43/**
     44 * This forward defines the Thread Control Block structure.
     45 */
     46typedef struct Thread_Control_struct Thread_Control;
     47
     48/**
     49 *  @brief Per CPU Core Structure
     50 *
     51 *  This structure is used to hold per core state information.
     52 */
     53typedef struct {
     54#if (CPU_ALLOCATE_INTERRUPT_STACK == TRUE) || \
     55    (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
     56  /**
     57   * This contains a pointer to the lower range of the interrupt stack for
     58   * this CPU.  This is the address allocated and freed.
     59   */
     60  void  *interrupt_stack_low;
     61
     62  /**
     63   * This contains a pointer to the interrupt stack pointer for this CPU.
     64   * It will be loaded at the beginning on an ISR.
     65   */
     66  void  *interrupt_stack_high;
     67#endif
     68
     69  /**
     70   *
     71   *  This contains the current interrupt nesting level on this
     72   *  CPU.
     73   */
     74  uint32_t isr_nest_level;
     75
     76  /** This is the thread executing on this CPU. */
     77  Thread_Control *executing;
     78
     79  /** This is the heir thread for this this CPU. */
     80  Thread_Control *heir;
     81
     82  /** This is the idle thread for this CPU. */
     83  Thread_Control *idle;
     84
     85  /** This is set to true when this CPU needs to run the dispatcher. */
     86  volatile bool dispatch_needed;
     87
     88} Per_CPU_Control;
     89#endif
     90
     91#ifdef ASM
     92
     93#if (CPU_ALLOCATE_INTERRUPT_STACK == TRUE) || \
     94    (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
     95  /*
     96   *  If this CPU target lets RTEMS allocates the interrupt stack, then
     97   *  we need to have places in the per cpu table to hold them.
     98   */
     99  #define PER_CPU_INTERRUPT_STACK_LOW   0
     100  #define PER_CPU_INTERRUPT_STACK_HIGH  (1 * SIZEOF_VOID_P)
     101  #define PER_CPU_END_STACK             (2 * SIZEOF_VOID_P)
     102#else
     103  /*
     104   *  Otherwise, there are no interrupt stack addresses in the per CPU table.
     105   */
     106  #define PER_CPU_END_STACK             0
     107#endif
     108
     109/*
     110 *  These are the offsets of the required elements in the per CPU table.
     111 */
     112#define PER_CPU_ISR_NEST_LEVEL   PER_CPU_END_STACK + 0
     113#define PER_CPU_EXECUTING        PER_CPU_END_STACK + (1 * SIZEOF_VOID_P)
     114#define PER_CPU_HEIR             PER_CPU_END_STACK + (2 * SIZEOF_VOID_P)
     115#define PER_CPU_IDLE             PER_CPU_END_STACK + (3 * SIZEOF_VOID_P)
     116#define PER_CPU_DISPATCH_NEEDED  PER_CPU_END_STACK + (4 * SIZEOF_VOID_P)
     117#define ISR_NEST_LEVEL \
     118    (SYM(_Per_CPU_Information) + PER_CPU_ISR_NEST_LEVEL)
     119#define DISPATCH_NEEDED \
     120    (SYM(_Per_CPU_Information) + PER_CPU_DISPATCH_NEEDED)
     121
     122/*
     123 * Do not define these offsets if they are not in the table.
     124 */
     125#if (CPU_ALLOCATE_INTERRUPT_STACK == TRUE) || \
     126    (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
     127  #define INTERRUPT_STACK_LOW \
     128      (SYM(_Per_CPU_Information) + PER_CPU_INTERRUPT_STACK_LOW)
     129  #define INTERRUPT_STACK_HIGH \
     130      (SYM(_Per_CPU_Information) + PER_CPU_INTERRUPT_STACK_HIGH)
     131#endif
     132
     133#endif
     134
     135#ifndef ASM
     136
     137/**
     138 *  @brief Set of Per CPU Core Information
     139 *
     140 *  This is an array of per CPU core information.
     141 */
     142extern Per_CPU_Control _Per_CPU_Information;
     143
     144/*
     145 * On an SMP system, these macros dereference the CPU core number.
     146 * But on a non-SMP system, these macros are simple references.
     147 * Thus when built for non-SMP, there should be no performance penalty.
     148 */
     149#define _Thread_Heir              _Per_CPU_Information.heir
     150#define _Thread_Executing         _Per_CPU_Information.executing
     151#define _Thread_Idle              _Per_CPU_Information.idle
     152#define _ISR_Nest_level           _Per_CPU_Information.isr_nest_level
     153#define _CPU_Interrupt_stack_low  _Per_CPU_Information.interrupt_stack_low
     154#define _CPU_Interrupt_stack_high _Per_CPU_Information.interrupt_stack_high
     155#define _Context_Switch_necessary _Per_CPU_Information.dispatch_needed
     156
     157#endif  /* ASM */
     158
     159#ifdef __cplusplus
     160}
     161#endif
     162
     163/**@}*/
     164
     165#endif
     166/* end of include file */

  • cpukit/score/include/rtems/score/thread.h 

    RCS file: /usr1/CVS/rtems/cpukit/score/include/rtems/score/thread.h,v
retrieving revision 1.93
diff -u -r1.93 thread.h
     
    2424 *
    2525 *  This handler encapsulates functionality related to the management of
    2626 *  threads.  This includes the creation, deletion, and scheduling of threads.
     27 *
     28 *  The following variables are maintained as part of the per cpu data
     29 *  structure.
     30 *
     31 *  + Idle thread pointer
     32 *  + Executing thread pointer
     33 *  + Heir thread pointer
    2734 */
    2835/**@{*/
    2936
    … …  
    5562  typedef uint32_t Thread_CPU_usage_t;
    5663#endif
    5764
     65#include <rtems/score/percpu.h>
    5866#include <rtems/score/context.h>
    5967#include <rtems/score/cpu.h>
    6068#if defined(RTEMS_MULTIPROCESSING)
    … …  
    147155  #endif
    148156}  Thread_CPU_budget_algorithms;
    149157
    150 /** This type defines the Thread Control Block structure.
    151  */
    152 typedef struct Thread_Control_struct Thread_Control;
    153 
    154158/**  This defines thes the entry point for the thread specific timeslice
    155159 *   budget management algorithm.
    156160 */
    … …  
    363367  /** This field is true if the thread is offered globally */
    364368  bool                                  is_global;
    365369#endif
    366   /** This field is is true if the post task context switch should be
    367    *  executed for this thread at the next context switch.
    368    */
    369   bool                                  do_post_task_switch_extension;
    370370  /** This field is true if the thread is preemptible. */
    371371  bool                                  is_preemptible;
    372372#if __RTEMS_ADA__
    … …  
    427427SCORE_EXTERN Objects_Information _Thread_Internal_information;
    428428
    429429/**
    430  *  The following define the thread control pointers used to access
    431  *  and manipulate the idle thread.
    432  */
    433 SCORE_EXTERN Thread_Control *_Thread_Idle;
    434 
    435 /**
    436430 *  The following context area contains the context of the "thread"
    437431 *  which invoked the start multitasking routine.  This context is
    438432 *  restored as the last action of the stop multitasking routine.  Thus
    … …  
    449443SCORE_EXTERN volatile uint32_t   _Thread_Dispatch_disable_level;
    450444
    451445/**
    452  *  If this is non-zero, then the post-task switch extension
    453  *  is run regardless of the state of the per thread flag.
    454  */
    455 SCORE_EXTERN uint32_t   _Thread_Do_post_task_switch_extension;
    456 
    457 /**
    458446 *  The following holds how many user extensions are in the system.  This
    459447 *  is used to determine how many user extension data areas to allocate
    460448 *  per thread.
    … …  
    473461SCORE_EXTERN Chain_Control *_Thread_Ready_chain;
    474462
    475463/**
    476  *  The following points to the thread which is currently executing.
    477  *  This thread is implicitly manipulated by numerous directives.
    478  */
    479 SCORE_EXTERN Thread_Control *_Thread_Executing;
    480 
    481 /**
    482  *  The following points to the highest priority ready thread
    483  *  in the system.  Unless the current thread is not preemptibl,
    484  *  then this thread will be context switched to when the next
    485  *  dispatch occurs.
    486  */
    487 SCORE_EXTERN Thread_Control *_Thread_Heir;
    488 
    489 /**
    490464 *  The following points to the thread whose floating point
    491465 *  context is currently loaded.
    492466 */

  • cpukit/score/src/isr.c 

    RCS file: /usr1/CVS/rtems/cpukit/score/src/isr.c,v
retrieving revision 1.18
diff -u -r1.18 isr.c
     
    3434
    3535void _ISR_Handler_initialization( void )
    3636{
    37   _ISR_Signals_to_thread_executing = false;
    38 
    3937  _ISR_Nest_level = 0;
    4038
    4139#if (CPU_SIMPLE_VECTORED_INTERRUPTS == TRUE)
    … …  
    6462    Configuration.interrupt_stack_size
    6563  );
    6664
     65  _CPU_Interrupt_stack_high = (void *)
     66    ((uintptr_t) _CPU_Interrupt_stack_high & ~CPU_STACK_ALIGNMENT);
     67
    6768  /* Interrupt stack might have to be aligned and/or setup
    6869   * in a specific way.
    6970   */

  • cpukit/score/src/isrthreaddispatch.c 

    RCS file: /usr1/CVS/rtems/cpukit/score/src/isrthreaddispatch.c,v
retrieving revision 1.3
diff -u -r1.3 isrthreaddispatch.c
     
    3333{
    3434  if ( _Context_Switch_necessary ) {
    3535    _Thread_Dispatch();
    36   } else if ( _ISR_Signals_to_thread_executing ) {
    37     _ISR_Signals_to_thread_executing = false;
    38     if (
    39       _Thread_Do_post_task_switch_extension
    40         || _Thread_Executing->do_post_task_switch_extension
    41     ) {
    42       _Thread_Executing->do_post_task_switch_extension = false;
    43       _API_extensions_Run_postswitch();
    44     }
    4536  }
    4637}
    4738

  • new file cpukit/score/src/percpu.c 

    RCS file: cpukit/score/src/percpu.c
diff -N cpukit/score/src/percpu.c
    - +  
     1/*
     2 *  COPYRIGHT (c) 1989-2010.
     3 *  On-Line Applications Research Corporation (OAR).
     4 *
     5 *  The license and distribution terms for this file may be
     6 *  found in the file LICENSE in this distribution or at
     7 *  http://www.rtems.com/license/LICENSE.
     8 *
     9 *  $Id: chain.c,v 1.18 2007/05/09 18:27:26 joel Exp $
     10 */
     11
     12#if HAVE_CONFIG_H
     13#include "config.h"
     14#endif
     15
     16#include <rtems/system.h>
     17#include <rtems/score/thread.h>
     18#include <rtems/score/percpu.h>
     19#include <rtems/score/wkspace.h>
     20#include <rtems/score/wkspace.h>
     21#include <rtems/config.h>
     22#include <string.h>
     23
     24/*
     25 * On single core systems, we can efficiently directly access a single
     26 * statically allocated per cpu structure.  And the fields are initialized
     27 * as individual elements just like it has always been done.
     28 */
     29Per_CPU_Control _Per_CPU_Information;

  • cpukit/score/src/thread.c 

    RCS file: /usr1/CVS/rtems/cpukit/score/src/thread.c,v
retrieving revision 1.62
diff -u -r1.62 thread.c
     
    7676  _Thread_Allocated_fp      = NULL;
    7777#endif
    7878
    79   _Thread_Do_post_task_switch_extension = 0;
    80 
    8179  _Thread_Maximum_extensions = maximum_extensions;
    8280
    8381  _Thread_Ticks_per_timeslice  = ticks_per_timeslice;

  • cpukit/score/src/threaddispatch.c 

    RCS file: /usr1/CVS/rtems/cpukit/score/src/threaddispatch.c,v
retrieving revision 1.20
diff -u -r1.20 threaddispatch.c
     
    9494    _Thread_Dispatch_disable_level = 1;
    9595    _Context_Switch_necessary = false;
    9696    _Thread_Executing = heir;
     97
     98    /*
     99     *  When the heir and executing are the same, then we are being
     100     *  requested to do the post switch dispatching.  This is normally
     101     *  done to dispatch signals.
     102     */
     103    if ( heir == executing )
     104      goto post_switch;
     105
     106    /*
     107     *  Since heir and executing are not the same, we need to do a real
     108     *  context switch.
     109     */
    97110#if __RTEMS_ADA__
    98111    executing->rtems_ada_self = rtems_ada_self;
    99112    rtems_ada_self = heir->rtems_ada_self;
    100113#endif
    101114    if ( heir->budget_algorithm == THREAD_CPU_BUDGET_ALGORITHM_RESET_TIMESLICE )
    102115      heir->cpu_time_budget = _Thread_Ticks_per_timeslice;
     116
    103117    _ISR_Enable( level );
    104118
    105119    #ifndef __RTEMS_USE_TICKS_FOR_STATISTICS__
    … …  
    170184    _ISR_Disable( level );
    171185  }
    172186
     187post_switch:
    173188  _Thread_Dispatch_disable_level = 0;
    174189
    175190  _ISR_Enable( level );
    176191
    177   if ( _Thread_Do_post_task_switch_extension ||
    178        executing->do_post_task_switch_extension ) {
    179     executing->do_post_task_switch_extension = false;
    180     _API_extensions_Run_postswitch();
    181   }
    182 
     192  _API_extensions_Run_postswitch();
    183193}

  • cpukit/score/src/threadloadenv.c 

    RCS file: /usr1/CVS/rtems/cpukit/score/src/threadloadenv.c,v
retrieving revision 1.7
diff -u -r1.7 threadloadenv.c
     
    5858#endif
    5959    is_fp = false;
    6060
    61 
    62   the_thread->do_post_task_switch_extension = false;
    6361  the_thread->is_preemptible   = the_thread->Start.is_preemptible;
    6462  the_thread->budget_algorithm = the_thread->Start.budget_algorithm;
    6563  the_thread->budget_callout   = the_thread->Start.budget_callout;

  • doc/porting/interrupts.t 

    RCS file: /usr1/CVS/rtems/doc/porting/interrupts.t,v
retrieving revision 1.9
diff -u -r1.9 interrupts.t
     
    366366#endif
    367367 
    368368if ( _Thread_Dispatch_disable_level )
    369    _ISR_Signals_to_thread_executing = FALSE;
    370369    goto the label "exit interrupt (simple case)"
    371370 
    372 if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing )
    373    _ISR_Signals_to_thread_executing = FALSE;
     371if ( _Context_Switch_necessary )
    374372   call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
    375373   prepare to get out of interrupt
    376374   return from interrupt  (maybe to _ISR_Dispatch)