Ticket #1396: mvme5500-rtems4.8.0-2009320.diff
File mvme5500-rtems4.8.0-2009320.diff, 137.7 KB (added by feng1, on 03/20/09 at 12:41:32) |
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ChangeLog
diff -Naur mvme5500.orig/ChangeLog mvme5500/ChangeLog
old new 1 2009-02-12 Kate Feng <feng1@bnl.gov> 2 * pci/pci.c : Updated it to be consistent with the original pci.c 3 * written by Eric Valette. There is no change in its function. 4 5 2009-01-30 Kate Feng <feng1@bnl.gov> 6 * irq/irq_init.c : set defaultIrq->next_handler to be 0 7 * for BSP_SHARED_HANDLER_SUPPORT. 8 * 9 2008-03-18 Kate Feng <feng1@bnl.gov> 10 * network/if_1GHz/if_wm.c : fixed some bugs in the 1GHz driver. 11 12 2008-02-12 Kate Feng <feng1@bnl.gov> 13 * irq/BSP_irq.c : added supports for shared IRQ. 14 15 2007-11-31 Kate Feng <feng1@bnl.gov> 16 * pci/pci_interface.c : Enabled PCI "Read", "Read Line", and "Read Multiple" 17 * Agressive Prefetch to improve the performance of the PCI based 18 * applications (e.g. 1GHz NIC). 19 20 2007-11-30 Kate Feng <feng1@bnl.gov> 21 * irq/BSP_irq.c : Replaced the irq/irq.c, and used GT_GPP_Value 22 * register to monitor the cause of the level sensitive interrupts. 23 * This unique solution solves various bugs in the 1GHz network drivers 24 * Fixed bugs in compute_pic_masks_from_prio() 25 1 26 2007-11-30 Joel Sherrill <joel.sherrill@OARcorp.com> 2 27 3 28 * irq/GT64260Int.c, network/if_100MHz/Makefile.am, … … 6 31 2007-09-20 Kate Feng <feng1@bnl.gov> 7 32 8 33 * network/if_100MHz/GT64260eth.c: Add else. 9 34 10 35 2007-09-19 Kate Feng <feng1@bnl.gov> 11 36 12 37 * README: Update. -
GT64260/CVS/Entries
diff -Naur mvme5500.orig/GT64260/CVS/Entries mvme5500/GT64260/CVS/Entries
old new 1 /GT64260TWSI.c/1.2/Fri Apr 15 20:13:18 2005// 2 /GT64260TWSI.h/1.2/Fri Apr 15 20:13:18 2005// 3 /MVME5500I2C.c/1.1/Wed Oct 20 15:21:05 2004// 4 /VPD.h/1.1/Wed Oct 20 15:21:05 2004// 5 /bspMvme5500.h/1.1/Wed Oct 20 15:21:05 2004// 6 /gtreg.h/1.1/Wed Oct 20 15:21:05 2004// 7 D -
GT64260/CVS/Repository
diff -Naur mvme5500.orig/GT64260/CVS/Repository mvme5500/GT64260/CVS/Repository
old new 1 rtems/c/src/lib/libbsp/powerpc/mvme5500/GT64260 -
GT64260/CVS/Root
diff -Naur mvme5500.orig/GT64260/CVS/Root mvme5500/GT64260/CVS/Root
old new 1 :pserver:anoncvs@www.rtems.com:/usr1/CVS -
GT64260/GT64260TWSI.c
diff -Naur mvme5500.orig/GT64260/GT64260TWSI.c mvme5500/GT64260/GT64260TWSI.c
old new 1 1 /* GT64260TWSI.c : Two-Wire Serial Interface (TWSI) support for the GT64260 2 2 * 3 * Copyright (c) 2004, Brookhaven National Laboratory and 4 * Shuchen Kate Feng <feng1@bnl.gov> 3 * Copyright (c) 2004, Brookhaven National Laboratory 4 * and Shuchen Kate Feng <feng1@bnl.gov> 5 * under the Deaprtment of Energy contract DE-AC02-98CH10886 5 6 * All rights reserved. 6 7 * 7 8 * The license and distribution terms for this file may be -
GT64260/GT64260TWSI.h
diff -Naur mvme5500.orig/GT64260/GT64260TWSI.h mvme5500/GT64260/GT64260TWSI.h
old new 1 1 /* 2 2 * $Id: GT64260TWSI.h,v 1.2 2005/04/15 20:13:18 joel Exp $ 3 * 4 * Copyright 2003 S. Kate Feng <feng1@bnl.gov>, 5 * NSLS, Brookhaven National Laboratory. All rights reserved. 6 * under the Deaprtment of Energy contract DE-AC02-98CH10886 3 7 */ 4 8 5 9 #ifndef __GT64260TWSI_h -
GT64260/gtreg.h
diff -Naur mvme5500.orig/GT64260/gtreg.h mvme5500/GT64260/gtreg.h
old new 190 190 #define GT_MPP_Control2 0xf008 191 191 #define GT_MPP_Control3 0xf00c 192 192 193 /* <skf> added */193 /* <skf> added for GT64260 */ 194 194 #define GT_MPP_SerialPortMultiplex 0xf010 195 195 196 196 #define GT_GPP_IO_Control 0xf100 … … 790 790 #define TWSI_SFT_RST 0xc01c 791 791 792 792 /* Interrupt Controller - Interrupt Controller Registers */ 793 /* <skf> added for GT64360 */ 794 795 #define GT64360_MAIN_INT_CAUSE_LO 0x004 /* read Only */ 796 #define GT64360_MAIN_INT_CAUSE_HI 0x00c /* read Only */ 797 #define GT64360_CPU0_INT_MASK_LO 0x014 798 #define GT64360_CPU0_INT_MASK_HI 0x01c 799 #define GT64360_CPU0_SEL_CAUSE 0x024 /* read Only */ 800 801 #define GT64360_CPU1_INT_MASK_LO 0x034 802 #define GT64360_CPU1_INT_MASK_HI 0x03c 803 #define GT64360_CPU1_SEL_CAUSE 0x044 /* read Only */ 804 793 805 /* Section 25.2 : Table 734 <skf> */ 794 806 795 #define GT _MAIN_INT_CAUSE_LO 0xc18 /* read Only */796 #define GT _MAIN_INT_CAUSE_HI0xc68 /* read Only */797 #define GT _CPU_INT_MASK_LO 0xc1c798 #define GT _CPU_INT_MASK_HI0xc6c799 #define GT _CPU_SEL_CAUSE 0xc70 /* read Only */807 #define GT64260_MAIN_INT_CAUSE_LO 0xc18 /* read Only */ 808 #define GT64260_MAIN_INT_CAUSE_HI 0xc68 /* read Only */ 809 #define GT64260_CPU_INT_MASK_LO 0xc1c 810 #define GT64260_CPU_INT_MASK_HI 0xc6c 811 #define GT64260_CPU_SEL_CAUSE 0xc70 /* read Only */ 800 812 #define GT_PCI0_INT_MASK_LO 0xc24 801 813 #define GT_PCI0_INT_MASK_HI 0xc64 802 814 #define GT_PCI0_SEL_CAUSE 0xc74 /* read Only */ -
GT64260/MVME5500I2C.c
diff -Naur mvme5500.orig/GT64260/MVME5500I2C.c mvme5500/GT64260/MVME5500I2C.c
old new 2 2 * 3 3 * Copyright (c) 2003, 2004 Brookhaven National Laboratory 4 4 * Author: S. Kate Feng <feng1@bnl.gov> 5 * under the Deaprtment of Energy contract DE-AC02-98CH10886 5 6 * All rights reserved. 6 7 * 7 8 * The license and distribution terms for this file may be … … 29 30 /**************************************************************************** 30 31 * I2Cread_eeprom - read EEPROM VPD from the I2C 31 32 */ 32 int I2Cread_eeprom(unchar I2cBusAddr,u32 devA2A1A0,u32 AddrBytes, unchar*pBuff,u32 numBytes)33 int I2Cread_eeprom(unchar I2cBusAddr,u32 devA2A1A0,u32 AddrBytes,void *pBuff,u32 numBytes) 33 34 { 34 35 int status=0, lastByte=0; 36 unchar *ptr=(unchar *) pBuff; 35 37 36 38 switch (AddrBytes) { 37 39 case 1: … … 83 85 /* read data from device */ 84 86 for ( ; numBytes > 0; numBytes-- ) { 85 87 if ( numBytes == 1) lastByte=1; 86 if (GT64260TWSIread(pBuff,lastByte) == -1) return (-1); 88 if (GT64260TWSIread(ptr,lastByte) == -1) { 89 printk("numBytes %d\n", numBytes); 90 return (-1); 91 } 87 92 #ifdef I2C_DEBUG 88 printk("%2x ", *p Buff);93 printk("%2x ", *ptr); 89 94 if ( (numBytes % 20)==0 ) printk("\n"); 90 95 #endif 91 p Buff++;96 ptr++; 92 97 } 93 98 #ifdef I2C_DEBUG 94 99 printk("\n"); -
GT64260/VPD.h
diff -Naur mvme5500.orig/GT64260/VPD.h mvme5500/GT64260/VPD.h
old new 2 2 * 3 3 * (C) 2004, NSLS, Brookhaven National Laboratory, 4 4 * S. Kate Feng, <feng1@bnl.gov> 5 * 5 * under the Deaprtment of Energy contract DE-AC02-98CH10886 6 6 */ 7 7 8 8 extern unsigned char ConfVPD_buff[200]; 9 9 10 #define VPD_ENET0_OFFSET 0x3c 11 #define VPD_ENET1_OFFSET 0x45 10 typedef struct ConfVpdRec { 11 char VendorId[8]; 12 char pad0[4]; 13 char BrdId[13]; 14 char pad1[2]; 15 char ManAssmNum[12]; 16 char pad2[2]; 17 char SerialNum[7]; 18 char pad3[2]; 19 /* char IntClk[4];*/ 20 uint32_t IntClk; 21 char pad4[3]; 22 /*char ExtClk[4];*/ 23 uint32_t ExtClk; 24 char pad5[3]; 25 char EnetAddr0[7]; 26 char pad6[2]; 27 char EnetAddr1[7]; 28 char pad7[20]; 29 } ConfVpdRec_t; 30 31 #define VPD_BOARD_ID 8 32 #define VPD_ENET0_OFFSET 0x40 33 #define VPD_ENET1_OFFSET 0x49 34 35 /* 36 4D4F544F 524F4C41 0200010D 4D564D45 MOTOROLA....MVME 37 35353030 2D303136 33020C30 312D5733 5500-0163..01-W3 38 38323946 30314403 07373035 31383238 829F01D..7051828 39 05053B9A CA000106 0507F281 55010807 ..;.........U... 40 ethernet address 41 xxxxxxxx xxxxxxxx xxxxxxxx xxxx3701 ................ 42 09043734 35350A04 87A6E98C 0B0C0089 ..7455..."=..... 43 00181002 02101000 78070B0C FFFFFFFF ........x....... 44 10020210 10017805 0E0FFFFF FFFFFFFF ......x......... 45 FFFFFF01 FF01FFFF FF0F0400 03000019 ................ 46 0A010107 02030000 000100FF FFFFFFFF ................ 47 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF ................ 48 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF ................ 49 00000000 00000000 00000000 00000000 ................ 50 00000000 00000000 00000000 00000000 ................ 51 00000000 00000000 00000000 00000000 ................ 52 00000000 00000000 00000000 00000000 ................ 53 54 For the MVME5500 : 55 56 Product Identifier : MVME5500-0163 57 Manufacturing Assembly Number : 01-W3829F01D 58 Serial Number : 7051828 59 Internal Clock Speed (Hertz) : 3B9ACA00 (&1000000000) 60 External Clock Speed (Hertz) : 07F28155 (&133333333) 61 Ethernet Address : xx xx xx xx xx xx xx 62 Ethernet Address : xx xx xx xx xx xx xx 63 Microprocessor Type : 7455 64 SROM/EEPROM CRC : D3223DD0 (&-752730672) 65 Flash0 Memory Configuration : 00 89 00 18 10 02 02 10 66 : 10 00 78 07 67 Flash1 Memory Configuration : FF FF FF FF 10 02 02 10 68 : 10 01 78 05 69 L2 Cache Configuration : FF FF FF FF FF FF FF FF 70 : FF 01 FF 01 FF FF FF 71 VPD Revision : 00 03 00 00 72 L3 Cache Configuration : 01 01 07 02 03 00 00 00 73 : 01 00 74 75 */ -
include/bsp.h
diff -Naur mvme5500.orig/include/bsp.h mvme5500/include/bsp.h
old new 7 7 * found in found in the file LICENSE in this distribution or at 8 8 * http://www.rtems.com/license/LICENSE. 9 9 * 10 * S. Kate Feng 2003-2007 : Modified it to support the mvme5500 BSP. 10 * (C) S. Kate Feng 2003-2007 : Modified it to support the mvme5500 BSP. 11 * 11 12 * 12 13 */ 13 14 … … 22 23 #include <libcpu/io.h> 23 24 #include <bsp/vectors.h> 24 25 25 #include <bsp/bspMvme5500.h> 26 /* Board type */ 27 typedef enum { 28 undefined = 0, 29 MVME5500, 30 MVME6100 31 } BSP_BoardTypes; 32 33 BSP_BoardTypes BSP_getBoardType(); 34 35 /* Board type */ 36 typedef enum { 37 Undefined, 38 UNIVERSE2, 39 TSI148, 40 } BSP_VMEchipTypes; 41 42 BSP_VMEchipTypes BSP_getVMEchipType(); 43 44 /* The version of Discovery system controller */ 45 46 typedef enum { 47 notdefined, 48 GT64260A, 49 GT64260B, 50 MV64360, 51 } DiscoveryChipVersion; 52 53 DiscoveryChipVersion BSP_getDiscoveryChipVersion(); 54 55 #define _256M 0x10000000 56 #define _512M 0x20000000 57 58 #define GT64x60_REG_BASE 0xf1000000 /* Base of GT64260 Reg Space */ 59 #define GT64x60_REG_SPACE_SIZE 0x10000 /* 64Kb Internal Reg Space */ 60 61 #define GT64x60_DEV1_BASE 0xf1100000 /* Device bank1(chip select 1) base 62 */ 63 #define GT64260_DEV1_SIZE 0x00100000 /* Device bank size */ 26 64 27 65 /* fundamental addresses for this BSP (PREPxxx are from libcpu/io.h) */ 28 #define _IO_BASE GT64260_REG_BASE 66 #define _IO_BASE GT64x60_REG_BASE 67 68 #define BSP_NVRAM_BASE_ADDR 0xf1110000 69 70 #define BSP_RTC_INTA_REG 0x7ff0 71 #define BSP_RTC_SECOND 0x7ff2 72 #define BSP_RTC_MINUTE 0x7ff3 73 #define BSP_RTC_HOUR 0x7ff4 74 #define BSP_RTC_DATE 0x7ff5 75 #define BSP_RTC_INTERRUPTS 0x7ff6 76 #define BSP_RTC_WATCHDOG 0x7ff7 29 77 30 78 /* PCI0 Domain I/O space */ 31 79 #define PCI0_IO_BASE 0xf0000000 … … 72 120 #define CONFIGURE_INTERRUPT_STACK_MEMORY (16 * 1024) 73 121 74 122 /* uart.c uses out_8 instead of outb */ 75 #define BSP_UART_IOBASE_COM1 GT64 260_DEV1_BASE + 0x2000076 #define BSP_UART_IOBASE_COM2 GT64 260_DEV1_BASE + 0x21000123 #define BSP_UART_IOBASE_COM1 GT64x60_DEV1_BASE + 0x20000 124 #define BSP_UART_IOBASE_COM2 GT64x60_DEV1_BASE + 0x21000 77 125 78 126 #define BSP_CONSOLE_PORT BSP_UART_COM1 /* console */ 79 127 #define BSP_UART_BAUD_BASE 115200 80 128 81 129 /* 82 * Vital Board data Start using DATA RESIDUAL83 */84 /*85 130 * Total memory using RESIDUAL DATA 86 131 */ 87 132 extern unsigned int BSP_mem_size; … … 120 165 #define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_i82544EI_driver_attach 121 166 #endif 122 167 123 extern int 124 RTEMS_BSP_NETWORK_DRIVER_ATTACH(/* struct rtems_bsdnet_ifconfig * */); 168 extern int RTEMS_BSP_NETWORK_DRIVER_ATTACH(); 125 169 126 /* As per Linux, This should be in the ppc/system.h */ 170 #define gccMemBar() RTEMS_COMPILER_MEMORY_BARRIER() 127 171 172 static inline void lwmemBar() 173 { 174 asm volatile("lwsync":::"memory"); 175 } 176 177 static inline void io_flush() 178 { 179 asm volatile("isync":::"memory"); 180 } 128 181 static inline void memBar() 129 182 { 130 183 asm volatile("sync":::"memory"); 131 184 } 132 133 185 static inline void ioBar() 134 186 { 135 asm volatile("eieio" );187 asm volatile("eieio":::"memory"); 136 188 } 137 189 138 190 #endif -
irq/BSP_irq.c
diff -Naur mvme5500.orig/irq/BSP_irq.c mvme5500/irq/BSP_irq.c
old new 1 /* BSP_irq.c 2 * 3 * This file contains the implementation of the function described in irq.h 4 * 5 * Copyright (C) 1998, 1999 valette@crf.canon.fr 6 * 7 * The license and distribution terms for this file may be 8 * found in the file LICENSE in this distribution or at 9 * http://www.OARcorp.com/rtems/license.html. 10 * 11 * Copyright 2003, 2004, 2005, 2007 Shuchen Kate Feng <feng1@bnl.gov>, 12 * NSLS, Brookhaven National Laboratory. All rights reserved. 13 * 14 * 1) Used GPP Value register to monitor the cause of the level sensitive 15 * interrupts. (Copyright : NDA item) 16 * 2) The implementation of picPrioTable[] is an original work by the 17 * author to optimize the software IRQ priority scheduling because 18 * Discovery controller does not provide H/W IRQ priority schedule. 19 * It ensures the fastest/faster interrupt service to the 20 * highest/higher priority IRQ, if pendig. 21 * 3) _CPU_MSR_SET() needs RTEMS_COMPILER_MEMORY_BARRIER() 22 * 23 */ 24 25 #include <stdio.h> 26 #include <rtems/system.h> 27 #include <bsp.h> 28 #include <bsp/irq.h> 29 #include <rtems/score/thread.h> 30 #include <rtems/score/apiext.h> 31 #include <libcpu/raw_exception.h> 32 #include <rtems/rtems/intr.h> 33 #include <libcpu/io.h> 34 #include <libcpu/byteorder.h> 35 #include <bsp/vectors.h> 36 37 #include <rtems/bspIo.h> /* for printk */ 38 #include "bsp/gtreg.h" 39 40 #define HI_INT_CAUSE 0x40000000 41 42 #define MAX_IRQ_LOOP 20 43 44 #define _MSR_GET( _mask) \ 45 do { \ 46 RTEMS_COMPILER_MEMORY_BARRIER(); \ 47 _CPU_MSR_GET( _mask); \ 48 RTEMS_COMPILER_MEMORY_BARRIER(); \ 49 } while (0); 50 51 #define _MSR_SET( _mask) \ 52 do { \ 53 RTEMS_COMPILER_MEMORY_BARRIER(); \ 54 _CPU_MSR_SET( _mask); \ 55 RTEMS_COMPILER_MEMORY_BARRIER(); \ 56 } while (0); 57 58 /* #define DEBUG_IRQ*/ 59 60 /* 61 * pointer to the mask representing the additionnal irq vectors 62 * that must be disabled when a particular entry is activated. 63 * They will be dynamically computed from the table given 64 * in BSP_rtems_irq_mngt_set(); 65 * CAUTION : this table is accessed directly by interrupt routine 66 * prologue. 67 */ 68 static unsigned int BSP_irq_prio_mask_tbl[3][BSP_PIC_IRQ_NUMBER]; 69 70 /* 71 * default handler connected on each irq after bsp initialization 72 */ 73 static rtems_irq_connect_data default_rtems_entry; 74 75 /* 76 * location used to store initial tables used for interrupt 77 * management.BSP copy of the configuration 78 */ 79 static rtems_irq_global_settings BSP_config; 80 81 static volatile unsigned *BSP_irqMask_reg[3]; 82 static volatile unsigned *BSP_irqCause_reg[3]; 83 static volatile unsigned BSP_irqMask_cache[3]={0,0,0}; 84 static unsigned int BSP_GPP_mask[4]= { 1<<24, 1<<25, 1<<26, 1<<27}; 85 86 static int picPrioTblPtr=0; 87 static unsigned int GPPIrqInTbl=0; 88 static unsigned long long MainIrqInTbl=0; 89 90 /* 91 * The software developers are forbidden to setup picPrioTable[], 92 * as it is a powerful engine for the BSP to find the pending 93 * highest priority IRQ at run time. It ensures the fastest/faster 94 * interrupt service to the highest/higher priority IRQ, if pendig. 95 * 96 * The picPrioTable[96] is updated dynamically at run time 97 * based on the priority levels set at BSPirqPrioTable[96], 98 * while the BSP_enable_irq_at_pic(), and BSP_disable_irq_at_pic() 99 * commands are invoked. 100 * 101 * The picPrioTable[96] lists the enabled CPU main and GPP external interrupt 102 * numbers [0 (lowest)- 95 (highest)] starting from the highest priority 103 * one to the lowest priority one. The highest priority interrupt is 104 * located at picPrioTable[0], and the lowest priority interrupt is located 105 * at picPrioTable[picPrioTblPtr-1]. 106 * 107 * 108 */ 109 #define DynamicIsrTable 110 #ifdef DynamicIsrTable 111 /* BitNums for Main Interrupt Lo/High Cause, -1 means invalid bit */ 112 static unsigned int picPrioTable[BSP_PIC_IRQ_NUMBER]={ 113 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 114 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 115 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 116 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 117 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 118 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 119 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 120 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 121 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 122 -1, -1, -1, -1, -1, -1 }; 123 #else 124 static unsigned int picPrioTable[BSP_PIC_IRQ_NUMBER]={ 125 80, 84, 76, 77, 32, -1, -1, -1, -1, -1, 126 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 127 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 128 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 129 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 130 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 131 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 132 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 133 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 134 -1, -1, -1, -1, -1, -1 }; 135 #endif 136 137 /* 138 * Check if IRQ is a MAIN CPU internal IRQ or GPP external IRQ 139 */ 140 static inline int is_pic_irq(const rtems_irq_number irqLine) 141 { 142 return (((int) irqLine <= BSP_GPP_IRQ_MAX_OFFSET) & 143 ((int) irqLine >= BSP_MICL_IRQ_LOWEST_OFFSET) 144 ); 145 } 146 147 /* 148 * Check if IRQ is a Porcessor IRQ 149 */ 150 static inline int is_processor_irq(const rtems_irq_number irqLine) 151 { 152 return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) & 153 ((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) 154 ); 155 } 156 157 /* 158 * ------------------------ RTEMS Irq helper functions ---------------- 159 */ 160 161 /* 162 * Caution : this function assumes the variable "BSP_config" 163 * is already set and that the tables it contains are still valid 164 * and accessible. 165 */ 166 static void compute_pic_masks_from_prio() 167 { 168 int i,j, k, isGppMain; 169 unsigned long long irq_prio_mask=0; 170 171 /* 172 * Always mask at least current interrupt to prevent re-entrance 173 */ 174 for (i=0; i <BSP_PIC_IRQ_NUMBER; i++) { 175 switch(i) { 176 case BSP_MAIN_GPP7_0_IRQ: 177 case BSP_MAIN_GPP15_8_IRQ: 178 case BSP_MAIN_GPP23_16_IRQ: 179 case BSP_MAIN_GPP31_24_IRQ: 180 for (k=0; k< 3; k++) 181 BSP_irq_prio_mask_tbl[k][i]=0; 182 183 irq_prio_mask =0; 184 isGppMain =1; 185 break; 186 default : 187 isGppMain =0; 188 irq_prio_mask = (unsigned long long) (1LLU << i); 189 break; 190 } 191 if ( isGppMain) continue; 192 for (j = 0; j <BSP_MAIN_IRQ_NUMBER; j++) { 193 /* 194 * Mask interrupts at PIC level that have a lower priority 195 */ 196 if (BSP_config.irqPrioTbl [i] >= BSP_config.irqPrioTbl [j]) 197 irq_prio_mask |= (unsigned long long)(1LLU << j); 198 } 199 200 201 BSP_irq_prio_mask_tbl[0][i] = irq_prio_mask & 0xffffffff; 202 BSP_irq_prio_mask_tbl[1][i] = (irq_prio_mask>>32) & 0xffffffff; 203 #if 0 204 printk("irq_mask_prio_tbl[%d]:0x%8x%8x\n",i,BSP_irq_prio_mask_tbl[1][i], 205 BSP_irq_prio_mask_tbl[0][i]); 206 #endif 207 208 BSP_irq_prio_mask_tbl[2][i] = 1<<i; 209 /* Compute for the GPP priority interrupt mask */ 210 for (j=BSP_GPP_IRQ_LOWEST_OFFSET; j <BSP_PROCESSOR_IRQ_LOWEST_OFFSET; j++) { 211 if (BSP_config.irqPrioTbl [i] >= BSP_config.irqPrioTbl [j]) 212 BSP_irq_prio_mask_tbl[2][i] |= 1 << (j-BSP_GPP_IRQ_LOWEST_OFFSET); 213 } 214 #if 0 215 printk("GPPirq_mask_prio_tbl[%d]:0x%8x\n",i,BSP_irq_prio_mask_tbl[2][i]); 216 #endif 217 } 218 } 219 220 static void UpdateMainIrqTbl(int irqNum) 221 { 222 int i=0, j, k, shifted=0; 223 224 switch (irqNum) { 225 case BSP_MAIN_GPP7_0_IRQ: 226 case BSP_MAIN_GPP15_8_IRQ: 227 case BSP_MAIN_GPP23_16_IRQ: 228 case BSP_MAIN_GPP31_24_IRQ: 229 return; /* Do nothing, let GPP take care of it */ 230 break; 231 } 232 #ifdef SHOW_MORE_INIT_SETTINGS 233 unsigned long val2, val1; 234 #endif 235 236 /* If entry not in table*/ 237 if ( ((irqNum<BSP_GPP_IRQ_LOWEST_OFFSET) && 238 (!((unsigned long long)(1LLU << irqNum) & MainIrqInTbl))) || 239 ((irqNum>BSP_MICH_IRQ_MAX_OFFSET) && 240 (!(( 1 << (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)) & GPPIrqInTbl)))) 241 { 242 while ( picPrioTable[i]!=-1) { 243 if (BSP_config.irqPrioTbl[irqNum]>BSP_config.irqPrioTbl[picPrioTable[i]]) { 244 /* all other lower priority entries shifted right */ 245 for (j=picPrioTblPtr;j>i; j--) { 246 picPrioTable[j]=picPrioTable[j-1]; 247 } 248 picPrioTable[i]=irqNum; 249 shifted=1; 250 break; 251 } 252 i++; 253 } 254 if (!shifted) picPrioTable[picPrioTblPtr] =irqNum; 255 256 if (irqNum >BSP_MICH_IRQ_MAX_OFFSET) 257 GPPIrqInTbl |= (1<< (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)); 258 else 259 MainIrqInTbl |= (unsigned long long)(1LLU << irqNum); 260 picPrioTblPtr++; 261 } 262 #ifdef SHOW_MORE_INIT_SETTINGS 263 val2 = (MainIrqInTbl>>32) & 0xffffffff; 264 val1 = MainIrqInTbl&0xffffffff; 265 printk("irqNum %d, MainIrqInTbl 0x%x%x\n", irqNum, val2, val1); 266 BSP_printPicIsrTbl(); 267 #endif 268 269 } 270 271 272 static void CleanMainIrqTbl(int irqNum) 273 { 274 int i, j, k; 275 276 switch (irqNum) { 277 case BSP_MAIN_GPP7_0_IRQ: 278 case BSP_MAIN_GPP15_8_IRQ: 279 case BSP_MAIN_GPP23_16_IRQ: 280 case BSP_MAIN_GPP31_24_IRQ: 281 return; /* Do nothing, let GPP take care of it */ 282 break; 283 } 284 if ( ((irqNum<BSP_GPP_IRQ_LOWEST_OFFSET) && 285 ((unsigned long long)(1LLU << irqNum) & MainIrqInTbl)) || 286 ((irqNum>BSP_MICH_IRQ_MAX_OFFSET) && 287 (( 1 << (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)) & GPPIrqInTbl))) 288 { /* If entry in table*/ 289 for (i=0; i<64; i++) { 290 if (picPrioTable[i]==irqNum) {/*remove it from the entry */ 291 /* all other lower priority entries shifted left */ 292 for (j=i;j<picPrioTblPtr; j++) { 293 picPrioTable[j]=picPrioTable[j+1]; 294 } 295 if (irqNum >BSP_MICH_IRQ_MAX_OFFSET) 296 GPPIrqInTbl &= ~(1<< (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)); 297 else 298 MainIrqInTbl &= ~(1LLU << irqNum); 299 picPrioTblPtr--; 300 break; 301 } 302 } 303 } 304 } 305 306 void BSP_enable_irq_at_pic(const rtems_irq_number irqNum) 307 { 308 unsigned bitNum, regNum; 309 unsigned int level; 310 311 bitNum = (((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET)%32; 312 regNum = (((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET)>>5; 313 314 rtems_interrupt_disable(level); 315 316 #ifdef DynamicIsrTable 317 UpdateMainIrqTbl((int) irqNum); 318 #endif 319 BSP_irqMask_cache[regNum] |= (1 << bitNum); 320 321 out_le32(BSP_irqMask_reg[regNum], BSP_irqMask_cache[regNum]); 322 while (in_le32(BSP_irqMask_reg[regNum]) != BSP_irqMask_cache[regNum]); 323 324 memBar(); 325 rtems_interrupt_enable(level); 326 } 327 328 void BSP_disable_irq_at_pic(const rtems_irq_number irqNum) 329 { 330 unsigned bitNum, regNum; 331 unsigned int level; 332 333 bitNum = (((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET)%32; 334 regNum = (((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET)>>5; 335 336 rtems_interrupt_disable(level); 337 338 #ifdef DynamicIsrTable 339 CleanMainIrqTbl((int) irqNum); 340 #endif 341 BSP_irqMask_cache[regNum] &= ~(1 << bitNum); 342 343 out_le32(BSP_irqMask_reg[regNum], BSP_irqMask_cache[regNum]); 344 while (in_le32(BSP_irqMask_reg[regNum]) != BSP_irqMask_cache[regNum]); 345 memBar(); 346 rtems_interrupt_enable(level); 347 } 348 349 /* Use shared/irq : 2008 */ 350 int BSP_setup_the_pic(rtems_irq_global_settings* config) 351 { 352 int i; 353 354 BSP_config = *config; 355 356 switch(BSP_getDiscoveryChipVersion()) { 357 case GT64260B: 358 case GT64260A: 359 /* Get ready for discovery BSP */ 360 BSP_irqMask_reg[0]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_CPU_INT_MASK_LO); 361 BSP_irqMask_reg[1]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_CPU_INT_MASK_HI); 362 BSP_irqCause_reg[0]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_MAIN_INT_CAUSE_LO); 363 BSP_irqCause_reg[1]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_MAIN_INT_CAUSE_HI); 364 break; 365 default: 366 printk("Not supported by this BSP yet\n"); 367 return(0); 368 break; 369 } 370 371 BSP_irqMask_reg[2]= (volatile unsigned int *) (GT64x60_REG_BASE + GT_GPP_Interrupt_Mask); 372 BSP_irqCause_reg[2]= (volatile unsigned int *) (GT64x60_REG_BASE + GT_GPP_Value); 373 374 /* Page 401, Table 598: 375 * Comm Unit Arbiter Control register : 376 * bit 10:GPP interrupts as level sensitive(1) or edge sensitive(0). 377 * MOTload default is set as level sensitive(1). Set it agin to make sure. 378 */ 379 outl((inl(GT_CommUnitArb_Ctrl)| (1<<10)), GT_CommUnitArb_Ctrl); 380 381 #if 0 382 printk("BSP_irqMask_reg[0] = 0x%x, BSP_irqCause_reg[0] 0x%x\n", 383 in_le32(BSP_irqMask_reg[0]), 384 in_le32(BSP_irqCause_reg[0])); 385 printk("BSP_irqMask_reg[1] = 0x%x, BSP_irqCause_reg[1] 0x%x\n", 386 in_le32(BSP_irqMask_reg[1]), 387 in_le32(BSP_irqCause_reg[1])); 388 printk("BSP_irqMask_reg[2] = 0x%x, BSP_irqCause_reg[2] 0x%x\n", 389 in_le32(BSP_irqMask_reg[2]), 390 in_le32(BSP_irqCause_reg[2])); 391 #endif 392 393 /* Initialize the interrupt related registers */ 394 for (i=0; i<3; i++) { 395 out_le32(BSP_irqCause_reg[i], 0); 396 out_le32(BSP_irqMask_reg[i], 0); 397 } 398 in_le32(BSP_irqMask_reg[2]); 399 compute_pic_masks_from_prio(); 400 401 #if 0 402 printk("BSP_irqMask_reg[0] = 0x%x, BSP_irqCause_reg[0] 0x%x\n", 403 in_le32(BSP_irqMask_reg[0]), 404 in_le32(BSP_irqCause_reg[0])); 405 printk("BSP_irqMask_reg[1] = 0x%x, BSP_irqCause_reg[1] 0x%x\n", 406 in_le32(BSP_irqMask_reg[1]), 407 in_le32(BSP_irqCause_reg[1])); 408 printk("BSP_irqMask_reg[2] = 0x%x, BSP_irqCause_reg[2] 0x%x\n", 409 in_le32(BSP_irqMask_reg[2]), 410 in_le32(BSP_irqCause_reg[2])); 411 #endif 412 413 /* 414 * 415 */ 416 for (i=BSP_MICL_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET ; i++) { 417 if ( BSP_config.irqHdlTbl[i].hdl != BSP_config.defaultEntry.hdl) { 418 BSP_enable_irq_at_pic(i); 419 BSP_config.irqHdlTbl[i].on(&BSP_config.irqHdlTbl[i]); 420 } 421 else { 422 BSP_config.irqHdlTbl[i].off(&BSP_config.irqHdlTbl[i]); 423 BSP_disable_irq_at_pic(i); 424 } 425 } 426 for (i= BSP_MAIN_GPP7_0_IRQ; i < BSP_MAIN_GPP31_24_IRQ; i++) 427 BSP_enable_irq_at_pic(i); 428 429 return(1); 430 } 431 432 /* 433 * High level IRQ handler called from shared_raw_irq_code_entry 434 */ 435 436 void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) 437 { 438 register unsigned msr, new_msr; 439 unsigned long irqCause[3]={0, 0,0}; 440 unsigned oldMask[3]={0,0,0}; 441 int loop=0, wloop=0, i=0, j; 442 register irq=0, group=0; 443 444 if (excNum == ASM_DEC_VECTOR) { 445 _MSR_GET(msr); 446 new_msr = msr | MSR_EE; 447 _MSR_SET(new_msr); 448 449 BSP_config.irqHdlTbl[BSP_DECREMENTER].hdl(BSP_config.irqHdlTbl[BSP_DECREMENTER].handle); 450 _MSR_SET(msr); 451 return; 452 453 } 454 455 for (j=0; j<3; j++ ) oldMask[j] = BSP_irqMask_cache[j]; 456 for (j=0; j<3; j++) irqCause[j] = in_le32(BSP_irqCause_reg[j]) & in_le32(BSP_irqMask_reg[j]); 457 458 while (((irq = picPrioTable[i++])!=-1)&& (loop++ < MAX_IRQ_LOOP)) 459 { 460 if (irqCause[group= irq/32] & ( 1<<(irq % 32))) { 461 for (j=0; j<3; j++) 462 BSP_irqMask_cache[j] &= (~ BSP_irq_prio_mask_tbl[j][irq]); 463 464 out_le32(BSP_irqMask_reg[0], BSP_irqMask_cache[0]); 465 out_le32(BSP_irqMask_reg[1], BSP_irqMask_cache[1]); 466 out_le32(BSP_irqMask_reg[2], BSP_irqMask_cache[2]); 467 in_le32(BSP_irqMask_reg[2]); 468 469 _MSR_GET(msr); 470 new_msr = msr | MSR_EE; 471 _MSR_SET(new_msr); 472 /* handler */ 473 #ifdef BSP_SHARED_HANDLER_SUPPORT 474 { 475 rtems_irq_connect_data* vchain; 476 for( vchain = &BSP_config.irqHdlTbl[irq]; 477 (vchain->hdl != BSP_config.defaultEntry.hdl && ((int)vchain != -1) ); 478 vchain = (rtems_irq_connect_data*)vchain->next_handler ) 479 { 480 vchain->hdl(vchain->handle); 481 } 482 } 483 #else 484 BSP_config.irqHdlTbl[irq].hdl(BSP_config.irqHdlTbl[irq].handle); 485 #endif 486 _MSR_SET(msr); 487 488 for (j=0; j<3; j++ ) BSP_irqMask_cache[j] = oldMask[j]; 489 490 out_le32(BSP_irqMask_reg[0], oldMask[0]); 491 out_le32(BSP_irqMask_reg[1], oldMask[1]); 492 out_le32(BSP_irqMask_reg[2], oldMask[2]); 493 in_le32(BSP_irqMask_reg[2]); 494 } 495 } 496 } 497 498 /* Only print part of the entries for now */ 499 void BSP_printPicIsrTbl() 500 { 501 int i; 502 503 printf("picPrioTable[12]={ irq# :"); 504 for (i=0; i<12; i++) 505 printf("%d,", picPrioTable[i]); 506 printf("}\n"); 507 508 printf("GPPIrqInTbl: 0x%x :\n", GPPIrqInTbl); 509 } -
irq/irq.c
diff -Naur mvme5500.orig/irq/irq.c mvme5500/irq/irq.c
old new 1 /* irq.c2 *3 * This file contains the implementation of the function described in irq.h4 *5 * Copyright (C) 1998, 1999 valette@crf.canon.fr6 *7 * The license and distribution terms for this file may be8 * found in the file LICENSE in this distribution or at9 * http://www.OARcorp.com/rtems/license.html.10 *11 * Acknowledgement May 2004 : to Till Straumann <strauman@slac.stanford.edu>12 * for some inputs.13 *14 * Copyright 2003, 2004, 2005, 2007 Shuchen Kate Feng <feng1@bnl.gov>,15 * NSLS,Brookhaven National Laboratory16 * 1) Modified and added support for the MVME5500 board.17 * 2) The implementation of picIsrTable[] is an original work by the18 * author to optimize the software IRQ priority scheduling because19 * Discovery controller does not provide H/W IRQ priority schedule.20 * It ensures the fastest/faster interrupt service to the21 * highest/higher priority IRQ, if pendig.22 * 3) _CPU_MSR_SET() needs RTEMS_COMPILER_MEMORY_BARRIER()23 *24 */25 26 #include <rtems/system.h>27 #include <bsp.h>28 #include <bsp/irq.h>29 #include <rtems/score/thread.h>30 #include <rtems/score/apiext.h>31 #include <libcpu/raw_exception.h>32 #include <rtems/rtems/intr.h>33 #include <libcpu/io.h>34 #include <libcpu/byteorder.h>35 #include <bsp/vectors.h>36 37 #include <rtems/bspIo.h> /* for printk */38 #include "bsp/gtreg.h"39 40 #define HI_INT_CAUSE 0x4000000041 42 #define MAX_IRQ_LOOP 3043 44 #define EDGE_TRIGGER45 46 #define _MSR_GET( _mask) \47 do { \48 RTEMS_COMPILER_MEMORY_BARRIER(); \49 _CPU_MSR_GET( _mask); \50 RTEMS_COMPILER_MEMORY_BARRIER(); \51 } while (0);52 53 #define _MSR_SET( _mask) \54 do { \55 RTEMS_COMPILER_MEMORY_BARRIER(); \56 _CPU_MSR_SET( _mask); \57 RTEMS_COMPILER_MEMORY_BARRIER(); \58 } while (0);59 60 /* #define DEBUG_IRQ*/61 62 /*63 * pointer to the mask representing the additionnal irq vectors64 * that must be disabled when a particular entry is activated.65 * They will be dynamically computed from the table given66 * in BSP_rtems_irq_mngt_set();67 * CAUTION : this table is accessed directly by interrupt routine68 * prologue.69 */70 static unsigned int BSP_irq_prio_mask_tbl[3][BSP_PIC_IRQ_NUMBER];71 72 /*73 * default handler connected on each irq after bsp initialization74 */75 static rtems_irq_connect_data default_rtems_entry;76 77 /*78 * location used to store initial tables used for interrupt79 * management.80 */81 static rtems_irq_global_settings* internal_config;82 static rtems_irq_connect_data* rtems_hdl_tbl;83 84 static volatile unsigned *BSP_irqMask_reg[3];85 static volatile unsigned *BSP_irqCause_reg[3];86 static volatile unsigned BSP_irqMask_cache[3]={0,0,0};87 88 89 static int picIsrTblPtr=0;90 static unsigned int GPPIrqInTbl=0;91 static unsigned long long MainIrqInTbl=0;92 93 /*94 * The software developers are forbidden to setup picIsrTable[],95 * as it is a powerful engine for the BSP to find the pending96 * highest priority IRQ at run time. It ensures the fastest/faster97 * interrupt service to the highest/higher priority IRQ, if pendig.98 *99 * The picIsrTable[96] is updated dynamically at run time100 * based on the priority levels set at BSPirqPrioTable[96],101 * while the BSP_enable_pic_irq(), and BSP_disable_pic_irq()102 * commands are invoked.103 *104 * The picIsrTable[96] lists the enabled CPU main and GPP external interrupt105 * numbers [0 (lowest)- 95 (highest)] starting from the highest priority106 * one to the lowest priority one. The highest priority interrupt is107 * located at picIsrTable[0], and the lowest priority interrupt is located108 * at picIsrTable[picIsrTblPtr-1].109 *110 *111 */112 /* BitNums for Main Interrupt Lo/High Cause and GPP, -1 means invalid bit */113 static unsigned int picIsrTable[BSP_PIC_IRQ_NUMBER]={114 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,115 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,116 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,117 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,118 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,119 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,120 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,121 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,122 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,123 -1, -1, -1, -1, -1, -1 };124 125 126 /*127 * Check if IRQ is a MAIN CPU internal IRQ or GPP external IRQ128 */129 static inline int is_pic_irq(const rtems_irq_number irqLine)130 {131 return (((int) irqLine <= BSP_GPP_IRQ_MAX_OFFSET) &132 ((int) irqLine >= BSP_MICL_IRQ_LOWEST_OFFSET)133 );134 }135 136 /*137 * Check if IRQ is a Porcessor IRQ138 */139 static inline int is_processor_irq(const rtems_irq_number irqLine)140 {141 return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) &142 ((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET)143 );144 }145 146 static inline unsigned int divIrq32(unsigned irq)147 {148 return(irq/32);149 }150 151 static inline unsigned int modIrq32(unsigned irq)152 {153 return(irq%32);154 }155 156 /*157 * ------------------------ RTEMS Irq helper functions ----------------158 */159 160 /*161 * Caution : this function assumes the variable "internal_config"162 * is already set and that the tables it contains are still valid163 * and accessible.164 */165 static void compute_pic_masks_from_prio()166 {167 int i,j, k;168 unsigned long long irq_prio_mask=0;169 170 /*171 * Always mask at least current interrupt to prevent re-entrance172 */173 for (i=0; i <BSP_PIC_IRQ_NUMBER; i++) {174 switch(i) {175 case BSP_MAIN_GPP7_0_IRQ:176 case BSP_MAIN_GPP15_8_IRQ:177 case BSP_MAIN_GPP23_16_IRQ:178 case BSP_MAIN_GPP31_24_IRQ:179 for (k=0; k< 3; k++)180 BSP_irq_prio_mask_tbl[k][i]=0;181 182 irq_prio_mask =0;183 break;184 default :185 irq_prio_mask = (unsigned long long) (1LLU << i);186 break;187 }188 189 if (irq_prio_mask) {190 for (j = 0; j <BSP_MAIN_IRQ_NUMBER; j++) {191 /*192 * Mask interrupts at PIC level that have a lower priority193 * or <Till Straumann> a equal priority.194 */195 if (internal_config->irqPrioTbl [i] >= internal_config->irqPrioTbl [j])196 irq_prio_mask |= (unsigned long long)(1LLU << j);197 }198 199 200 BSP_irq_prio_mask_tbl[0][i] = irq_prio_mask & 0xffffffff;201 BSP_irq_prio_mask_tbl[1][i] = (irq_prio_mask>>32) & 0xffffffff;202 #ifdef DEBUG203 printk("irq_mask_prio_tbl[%d]:0x%8x%8x\n",i,BSP_irq_prio_mask_tbl[1][i],204 BSP_irq_prio_mask_tbl[0][i]);205 #endif206 207 BSP_irq_prio_mask_tbl[2][i] = 1<<i;208 /* Compute for the GPP priority interrupt mask */209 for (j=BSP_GPP_IRQ_LOWEST_OFFSET; j <BSP_PROCESSOR_IRQ_LOWEST_OFFSET; j++) {210 if (internal_config->irqPrioTbl [i] >= internal_config->irqPrioTbl [j])211 BSP_irq_prio_mask_tbl[2][i] |= 1 << (j-BSP_GPP_IRQ_LOWEST_OFFSET);212 }213 }214 }215 }216 217 218 static void UpdateMainIrqTbl(int irqNum)219 {220 int i=0, j, shifted=0;221 222 switch (irqNum) {223 case BSP_MAIN_GPP7_0_IRQ:224 case BSP_MAIN_GPP15_8_IRQ:225 case BSP_MAIN_GPP23_16_IRQ:226 case BSP_MAIN_GPP31_24_IRQ:227 return; /* Do nothing, let GPP take care of it */228 break;229 }230 #ifdef SHOW_MORE_INIT_SETTINGS231 unsigned long val2, val1;232 #endif233 234 /* If entry not in table*/235 if ( ((irqNum<BSP_GPP_IRQ_LOWEST_OFFSET) &&236 (!((unsigned long long)(1LLU << irqNum) & MainIrqInTbl))) ||237 ((irqNum>BSP_MICH_IRQ_MAX_OFFSET) &&238 (!(( 1 << (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)) & GPPIrqInTbl))))239 {240 while ( picIsrTable[i]!=-1) {241 if (internal_config->irqPrioTbl[irqNum]>internal_config->irqPrioTbl[picIsrTable[i]]) {242 /* all other lower priority entries shifted right */243 for (j=picIsrTblPtr;j>i; j--)244 picIsrTable[j]=picIsrTable[j-1];245 picIsrTable[i]=irqNum;246 shifted=1;247 break;248 }249 i++;250 }251 if (!shifted) picIsrTable[picIsrTblPtr]=irqNum;252 if (irqNum >BSP_MICH_IRQ_MAX_OFFSET)253 GPPIrqInTbl |= (1<< (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET));254 else255 MainIrqInTbl |= (unsigned long long)(1LLU << irqNum);256 picIsrTblPtr++;257 }258 #ifdef SHOW_MORE_INIT_SETTINGS259 val2 = (MainIrqInTbl>>32) & 0xffffffff;260 val1 = MainIrqInTbl&0xffffffff;261 printk("irqNum %d, MainIrqInTbl 0x%x%x\n", irqNum, val2, val1);262 BSP_printPicIsrTbl();263 #endif264 265 }266 267 268 static void CleanMainIrqTbl(int irqNum)269 {270 int i, j;271 272 switch (irqNum) {273 case BSP_MAIN_GPP7_0_IRQ:274 case BSP_MAIN_GPP15_8_IRQ:275 case BSP_MAIN_GPP23_16_IRQ:276 case BSP_MAIN_GPP31_24_IRQ:277 return; /* Do nothing, let GPP take care of it */278 break;279 }280 if ( ((irqNum<BSP_GPP_IRQ_LOWEST_OFFSET) &&281 ((unsigned long long)(1LLU << irqNum) & MainIrqInTbl)) ||282 ((irqNum>BSP_MICH_IRQ_MAX_OFFSET) &&283 (( 1 << (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)) & GPPIrqInTbl)))284 { /* If entry in table*/285 for (i=0; i<64; i++) {286 if (picIsrTable[i]==irqNum) {/*remove it from the entry */287 /* all other lower priority entries shifted left */288 for (j=i;j<picIsrTblPtr; j++)289 picIsrTable[j]=picIsrTable[j+1];290 if (irqNum >BSP_MICH_IRQ_MAX_OFFSET)291 GPPIrqInTbl &= ~(1<< (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET));292 else293 MainIrqInTbl &= ~(1LLU << irqNum);294 picIsrTblPtr--;295 break;296 }297 }298 }299 }300 301 void BSP_enable_pic_irq(const rtems_irq_number irqNum)302 {303 unsigned bitNum, regNum;304 unsigned int level;305 306 bitNum = modIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET);307 regNum = divIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET);308 309 rtems_interrupt_disable(level);310 311 UpdateMainIrqTbl((int) irqNum);312 BSP_irqMask_cache[regNum] |= (1 << bitNum);313 314 out_le32(BSP_irqMask_reg[regNum], BSP_irqMask_cache[regNum]);315 while (in_le32(BSP_irqMask_reg[regNum]) != BSP_irqMask_cache[regNum]);316 317 rtems_interrupt_enable(level);318 }319 320 void BSP_disable_pic_irq(const rtems_irq_number irqNum)321 {322 unsigned bitNum, regNum;323 unsigned int level;324 325 bitNum = modIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET);326 regNum = divIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET);327 328 rtems_interrupt_disable(level);329 330 CleanMainIrqTbl((int) irqNum);331 BSP_irqMask_cache[regNum] &= ~(1 << bitNum);332 333 out_le32(BSP_irqMask_reg[regNum], BSP_irqMask_cache[regNum]);334 while (in_le32(BSP_irqMask_reg[regNum]) != BSP_irqMask_cache[regNum]);335 336 rtems_interrupt_enable(level);337 }338 339 int BSP_setup_the_pic() /* adapt the same name as shared/irq */340 {341 int i;342 343 /* Get ready for discovery BSP */344 BSP_irqMask_reg[0]= (volatile unsigned int *) (GT64260_REG_BASE + GT_CPU_INT_MASK_LO);345 BSP_irqMask_reg[1]= (volatile unsigned int *) (GT64260_REG_BASE + GT_CPU_INT_MASK_HI);346 BSP_irqMask_reg[2]= (volatile unsigned int *) (GT64260_REG_BASE + GT_GPP_Interrupt_Mask);347 348 BSP_irqCause_reg[0]= (volatile unsigned int *) (GT64260_REG_BASE + GT_MAIN_INT_CAUSE_LO);349 BSP_irqCause_reg[1]= (volatile unsigned int *) (GT64260_REG_BASE + GT_MAIN_INT_CAUSE_HI);350 BSP_irqCause_reg[2]= (volatile unsigned int *) (GT64260_REG_BASE + GT_GPP_Interrupt_Cause);351 352 #ifdef EDGE_TRIGGER353 354 /* Page 401, Table 598:355 * Comm Unit Arbiter Control register :356 * bit 10:GPP interrupts as level sensitive(1) or edge sensitive(0).357 * We set the GPP interrupts to be edge sensitive.358 * MOTload default is set as level sensitive(1).359 */360 outl((inl(GT_CommUnitArb_Ctrl)& (~(1<<10))), GT_CommUnitArb_Ctrl);361 #else362 outl((inl(GT_CommUnitArb_Ctrl)| (1<<10)), GT_CommUnitArb_Ctrl);363 #endif364 365 #if 0366 printk("BSP_irqMask_reg[0] = 0x%x, BSP_irqCause_reg[0] 0x%x\n",367 in_le32(BSP_irqMask_reg[0]),368 in_le32(BSP_irqCause_reg[0]));369 printk("BSP_irqMask_reg[1] = 0x%x, BSP_irqCause_reg[1] 0x%x\n",370 in_le32(BSP_irqMask_reg[1]),371 in_le32(BSP_irqCause_reg[1]));372 printk("BSP_irqMask_reg[2] = 0x%x, BSP_irqCause_reg[2] 0x%x\n",373 in_le32(BSP_irqMask_reg[2]),374 in_le32(BSP_irqCause_reg[2]));375 #endif376 377 /* Initialize the interrupt related GT64260 registers */378 for (i=0; i<3; i++) {379 out_le32(BSP_irqCause_reg[i], 0);380 out_le32(BSP_irqMask_reg[i], 0);381 }382 in_le32(BSP_irqMask_reg[2]);383 compute_pic_masks_from_prio();384 385 #if 0386 printk("BSP_irqMask_reg[0] = 0x%x, BSP_irqCause_reg[0] 0x%x\n",387 in_le32(BSP_irqMask_reg[0]),388 in_le32(BSP_irqCause_reg[0]));389 printk("BSP_irqMask_reg[1] = 0x%x, BSP_irqCause_reg[1] 0x%x\n",390 in_le32(BSP_irqMask_reg[1]),391 in_le32(BSP_irqCause_reg[1]));392 printk("BSP_irqMask_reg[2] = 0x%x, BSP_irqCause_reg[2] 0x%x\n",393 in_le32(BSP_irqMask_reg[2]),394 in_le32(BSP_irqCause_reg[2]));395 #endif396 397 /*398 *399 */400 for (i=BSP_MICL_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET ; i++) {401 if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {402 BSP_enable_pic_irq(i);403 rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);404 }405 else {406 rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);407 BSP_disable_pic_irq(i);408 }409 }410 411 return(1);412 }413 414 /*415 * This function check that the value given for the irq line416 * is valid.417 */418 419 static int isValidInterrupt(int irq)420 {421 if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET))422 return 0;423 return 1;424 }425 426 /*427 * ------------------------ RTEMS Single Irq Handler Mngt Routines ----------------428 */429 430 int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)431 {432 unsigned int level;433 434 if (!isValidInterrupt(irq->name)) {435 printk("Invalid interrupt vector %d\n",irq->name);436 return 0;437 }438 /*439 * Check if default handler is actually connected. If not issue an error.440 * You must first get the current handler via i386_get_current_idt_entry441 * and then disconnect it using i386_delete_idt_entry.442 * RATIONALE : to always have the same transition by forcing the user443 * to get the previous handler before accepting to disconnect.444 */445 rtems_interrupt_disable(level);446 if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) {447 rtems_interrupt_enable(level);448 printk("IRQ vector %d already connected\n",irq->name);449 return 0;450 }451 452 /*453 * store the data provided by user454 */455 rtems_hdl_tbl[irq->name] = *irq;456 #ifdef BSP_SHARED_HANDLER_SUPPORT457 rtems_hdl_tbl[irq->name].next_handler = (void *)-1;458 #endif459 460 if (is_pic_irq(irq->name)) {461 /*462 * Enable PIC irq : Main Interrupt Cause Low and High & GPP external463 */464 #ifdef DEBUG_IRQ465 printk("PIC irq %d\n",irq->name);466 #endif467 BSP_enable_pic_irq(irq->name);468 }469 else {470 if (is_processor_irq(irq->name)) {471 /*472 * Enable exception at processor level473 */474 475 }476 }477 /*478 * Enable interrupt on device479 */480 irq->on(irq);481 482 rtems_interrupt_enable(level);483 484 return 1;485 }486 487 488 int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* irq)489 {490 if (!isValidInterrupt(irq->name)) {491 return 0;492 }493 *irq = rtems_hdl_tbl[irq->name];494 return 1;495 }496 497 int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)498 {499 unsigned int level;500 501 if (!isValidInterrupt(irq->name)) {502 return 0;503 }504 /*505 * Check if default handler is actually connected. If not issue an error.506 * You must first get the current handler via i386_get_current_idt_entry507 * and then disconnect it using i386_delete_idt_entry.508 * RATIONALE : to always have the same transition by forcing the user509 * to get the previous handler before accepting to disconnect.510 */511 if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) {512 return 0;513 }514 rtems_interrupt_disable(level);515 516 /*517 * disable PIC interrupt518 */519 if (is_pic_irq(irq->name))520 BSP_disable_pic_irq(irq->name);521 else {522 if (is_processor_irq(irq->name)) {523 /*524 * disable exception at processor level525 */526 }527 }528 529 /*530 * Disable interrupt on device531 */532 irq->off(irq);533 534 /*535 * restore the default irq value536 */537 rtems_hdl_tbl[irq->name] = default_rtems_entry;538 539 540 rtems_interrupt_enable(level);541 542 return 1;543 }544 545 /*546 * ------------------------ RTEMS Global Irq Handler Mngt Routines ----------------547 */548 549 int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)550 {551 unsigned int level;552 int i;553 554 /*555 * Store various code accelerators556 */557 internal_config = config;558 default_rtems_entry = config->defaultEntry;559 rtems_hdl_tbl = config->irqHdlTbl;560 561 rtems_interrupt_disable(level);562 563 if ( !BSP_setup_the_pic() ) {564 printk("PIC setup failed; leaving IRQs OFF\n");565 return 0;566 }567 568 for (i= BSP_MAIN_GPP7_0_IRQ; i <= BSP_MAIN_GPP31_24_IRQ; i++)569 BSP_enable_pic_irq(i);570 571 rtems_interrupt_enable(level);572 return 1;573 }574 575 int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config)576 {577 *config = internal_config;578 return 0;579 }580 581 /*582 * High level IRQ handler called from shared_raw_irq_code_entry583 */584 585 void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)586 {587 register unsigned msr, new_msr;588 unsigned long irqCause[3]={0, 0,0};589 register unsigned long selectCause;590 unsigned oldMask[3]={0,0,0};591 register unsigned i=0, j, irq=0, bitmask=0, group=0;592 593 if (excNum == ASM_DEC_VECTOR) {594 _MSR_GET(msr);595 new_msr = msr | MSR_EE;596 _MSR_SET(new_msr);597 598 rtems_hdl_tbl[BSP_DECREMENTER].hdl(rtems_hdl_tbl[BSP_DECREMENTER].handle);599 600 _MSR_SET(msr);601 return;602 603 }604 605 for (j=0; j<3; j++ ) oldMask[j] = BSP_irqMask_cache[j];606 607 if ((selectCause= in_le32((volatile unsigned *)0xf1000c70)) & HI_INT_CAUSE ){608 irqCause[1] = (selectCause & BSP_irqMask_cache[1]);609 irqCause[2] = in_le32(BSP_irqCause_reg[2]) & BSP_irqMask_cache[2];610 }611 else {612 irqCause[0] = (selectCause & BSP_irqMask_cache[0]);613 if ((irqCause[1] =(in_le32((volatile unsigned *)0xf1000c68)&BSP_irqMask_cache[1])))614 irqCause[2] = in_le32(BSP_irqCause_reg[2]) & BSP_irqMask_cache[2];615 }616 617 while ((irq = picIsrTable[i++])!=-1)618 {619 if (irqCause[group=(irq/32)] && (irqCause[group]&(bitmask=(1<<(irq % 32))))) {620 for (j=0; j<3; j++)621 BSP_irqMask_cache[j] &= (~ BSP_irq_prio_mask_tbl[j][irq]);622 623 RTEMS_COMPILER_MEMORY_BARRIER();624 out_le32((volatile unsigned *)0xf1000c1c, BSP_irqMask_cache[0]);625 out_le32((volatile unsigned *)0xf1000c6c, BSP_irqMask_cache[1]);626 out_le32((volatile unsigned *)0xf100f10c, BSP_irqMask_cache[2]);627 in_le32((volatile unsigned *)0xf100f10c);628 629 #ifdef EDGE_TRIGGER630 if (irq > BSP_MICH_IRQ_MAX_OFFSET)631 out_le32(BSP_irqCause_reg[2], ~bitmask);/* Till Straumann: Ack the edge triggered GPP IRQ */632 #endif633 634 _MSR_GET(msr);635 new_msr = msr | MSR_EE;636 _MSR_SET(new_msr);637 rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle);638 _MSR_SET(msr);639 640 for (j=0; j<3; j++ ) BSP_irqMask_cache[j] = oldMask[j];641 break;642 }643 }644 645 out_le32((volatile unsigned *)0xf1000c1c, oldMask[0]);646 out_le32((volatile unsigned *)0xf1000c6c, oldMask[1]);647 out_le32((volatile unsigned *)0xf100f10c, oldMask[2]);648 in_le32((volatile unsigned *)0xf100f10c);649 }650 651 void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx)652 {653 /*654 * Process pending signals that have not already been655 * processed by _Thread_Displatch. This happens quite656 * unfrequently : the ISR must have posted an action657 * to the current running thread.658 */659 if ( _Thread_Do_post_task_switch_extension ||660 _Thread_Executing->do_post_task_switch_extension ) {661 _Thread_Executing->do_post_task_switch_extension = FALSE;662 _API_extensions_Run_postswitch();663 }664 /*665 * I plan to process other thread related events here.666 * This will include DEBUG session requested from keyboard...667 */668 }669 670 /* Only print part of the entries for now */671 void BSP_printPicIsrTbl()672 {673 int i;674 675 printk("picIsrTable[12]={");676 for (i=0; i<12; i++)677 printk("%d,", picIsrTable[i]);678 printk("}\n");679 680 printk("GPPIrqInTbl: 0x%x :\n", GPPIrqInTbl);681 } -
irq/irq.h
diff -Naur mvme5500.orig/irq/irq.h mvme5500/irq/irq.h
old new 29 29 #ifndef LIBBSP_POWERPC_MVME5500_IRQ_IRQ_H 30 30 #define LIBBSP_POWERPC_MVME5500_IRQ_IRQ_H 31 31 32 /*#define BSP_SHARED_HANDLER_SUPPORT 1*/ 32 #define BSP_SHARED_HANDLER_SUPPORT 1 33 33 34 #include <rtems/irq.h> 34 35 35 36 #define BSP_ASM_IRQ_VECTOR_BASE 0x0 … … 84 85 /* 85 86 * Summary 86 87 */ 87 #define BSP_IRQ_NUMBER (BSP_ MISC_IRQ_MAX_OFFSET + 1)88 #define BSP_IRQ_NUMBER (BSP_PIC_IRQ_NUMBER + BSP_PROCESSOR_IRQ_NUMBER) 88 89 #define BSP_MAIN_IRQ_NUMBER (64) 89 90 #define BSP_PIC_IRQ_NUMBER (96) 90 #define BSP_LOWEST_OFFSET ( BSP_MICL_IRQ_LOWEST_OFFSET)91 #define BSP_MAX_OFFSET (BSP_ MISC_IRQ_MAX_OFFSET)91 #define BSP_LOWEST_OFFSET (0) 92 #define BSP_MAX_OFFSET (BSP_LOWEST_OFFSET + BSP_IRQ_NUMBER - 1) 92 93 93 94 /* Main CPU interrupt cause (Low) */ 94 95 #define BSP_MAIN_TIMER0_1_IRQ (BSP_MICL_IRQ_LOWEST_OFFSET+8) -
irq/irq_init.c
diff -Naur mvme5500.orig/irq/irq_init.c mvme5500/irq/irq_init.c
old new 41 41 42 42 static rtems_irq_connect_data rtemsIrq[BSP_IRQ_NUMBER]; 43 43 static rtems_irq_global_settings initial_config; 44 45 #ifdef BSP_SHARED_HANDLER_SUPPORT 46 static rtems_irq_connect_data defaultIrq = { 47 /* vectorIdex, hdl ,handle , on , off , isOn ,next_handler, */ 48 0, nop_func , NULL , nop_func , nop_func , not_connected, 0 49 }; 50 #else 44 51 static rtems_irq_connect_data defaultIrq = { 45 52 /* vectorIdex, hdl , handle , on , off , isOn */ 46 53 0, nop_func , NULL , nop_func , nop_func , not_connected 47 54 }; 55 #endif 48 56 49 57 rtems_irq_prio BSPirqPrioTable[BSP_PIC_IRQ_NUMBER]={ 50 58 /* … … 140 148 printk("Done setup irq mngt configuration\n"); 141 149 #endif 142 150 143 /*144 * We must connect the raw irq handler for the two145 * expected interrupt sources : decrementer and external interrupts.146 */147 vectorDesc.exceptIndex = ASM_DEC_VECTOR;148 vectorDesc.hdl.vector = ASM_DEC_VECTOR;149 vectorDesc.hdl.raw_hdl = decrementer_exception_vector_prolog_code;150 vectorDesc.hdl.raw_hdl_size = (unsigned) decrementer_exception_vector_prolog_code_size;151 vectorDesc.on = nop_func;152 vectorDesc.off = nop_func;153 vectorDesc.isOn = connected;154 if (!ppc_set_exception (&vectorDesc)) {155 BSP_panic("Unable to initialize RTEMS decrementer raw exception\n");156 }157 vectorDesc.exceptIndex = ASM_EXT_VECTOR;158 vectorDesc.hdl.vector = ASM_EXT_VECTOR;159 vectorDesc.hdl.raw_hdl = external_exception_vector_prolog_code;160 vectorDesc.hdl.raw_hdl_size = (unsigned) external_exception_vector_prolog_code_size;161 if (!ppc_set_exception (&vectorDesc)) {162 BSP_panic("Unable to initialize RTEMS external raw exception\n");163 }164 151 #ifdef TRACE_IRQ_INIT 165 152 printk("RTEMS IRQ management is now operationnal\n"); 166 153 #endif -
Makefile.am
diff -Naur mvme5500.orig/Makefile.am mvme5500/Makefile.am
old new 35 35 ../../powerpc/shared/startup/pretaskinghook.c \ 36 36 ../../powerpc/shared/startup/sbrk.c ../../shared/bootcard.c \ 37 37 startup/bspclean.c ../../shared/bsplibc.c ../../shared/bsppost.c \ 38 ../../shared/gnatinstallhandler.c startup/reboot.c 38 ../../shared/gnatinstallhandler.c startup/reboot.c \ 39 ../../powerpc/shared/startup/probeMemEnd.c 39 40 startup_rel_CPPFLAGS = $(AM_CPPFLAGS) 40 41 startup_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) 41 42 … … 68 69 include_bsp_HEADERS += irq/irq.h 69 70 70 71 noinst_PROGRAMS += irq.rel 71 irq_rel_SOURCES = irq/irq_init.c irq/ irq.c \72 ../../powerpc/shared/irq/irq_asm.S72 irq_rel_SOURCES = irq/irq_init.c irq/BSP_irq.c \ 73 ../../powerpc/shared/irq/irq.c ../../powerpc/shared/irq/irq_asm.S 73 74 irq_rel_CPPFLAGS = $(AM_CPPFLAGS) 74 75 irq_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) 75 76 … … 108 109 109 110 network_CPPFLAGS = -D_KERNEL 110 111 noinst_PROGRAMS += network.rel 111 network_rel_SOURCES = network/if_100MHz/GT64260eth.c \ 112 network/if_1GHz/if_wm.c network/if_1GHz/pci_map.c 112 network_rel_SOURCES = network/if_100MHz/GT64260eth.c network/if_1GHz/if_wm.c \ 113 network/if_1GHz/pci_map.c 114 113 115 network_rel_CPPFLAGS = $(AM_CPPFLAGS) $(network_CPPFLAGS) 114 116 network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) 115 117 endif … … 123 125 124 126 noinst_PROGRAMS += vme.rel 125 127 vme_rel_SOURCES = ../../shared/vmeUniverse/vmeUniverse.c\ 126 ../shared/vme/vmeconfig.c ../../shared/vmeUniverse/bspVmeDmaList.c\127 ../shared/vme/vme_universe .c ../shared/vme/vme_universe_dma.c128 vme/vmeconfig.c ../../shared/vmeUniverse/bspVmeDmaList.c\ 129 ../shared/vme/vme_universe_dma.c 128 130 129 131 vme_rel_CPPFLAGS = $(AM_CPPFLAGS) 130 132 vme_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) -
network/if_100MHz/CVS/Entries
diff -Naur mvme5500.orig/network/if_100MHz/CVS/Entries mvme5500/network/if_100MHz/CVS/Entries
old new 1 /GT64260eth.c/1.8/Thu May 12 18:25:29 2005// 2 /GT64260eth.h/1.1/Wed Oct 20 15:21:05 2004// 3 /GT64260ethreg.h/1.2/Wed Oct 20 18:28:00 2004// 4 D -
network/if_100MHz/CVS/Repository
diff -Naur mvme5500.orig/network/if_100MHz/CVS/Repository mvme5500/network/if_100MHz/CVS/Repository
old new 1 rtems/c/src/lib/libbsp/powerpc/mvme5500/network -
network/if_100MHz/CVS/Root
diff -Naur mvme5500.orig/network/if_100MHz/CVS/Root mvme5500/network/if_100MHz/CVS/Root
old new 1 :pserver:anoncvs@www.rtems.com:/usr1/CVS -
network/if_100MHz/GT64260eth.c
diff -Naur mvme5500.orig/network/if_100MHz/GT64260eth.c mvme5500/network/if_100MHz/GT64260eth.c
old new 2 2 * 3 3 * Copyright (c) 2003,2004 Brookhaven National Laboratory 4 4 * S. Kate Feng <feng1@bnl.gov> 5 * All rights reserved5 * All rights reserved 6 6 * 7 7 * Acknowledgements: 8 8 * netBSD : Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. 9 9 * Marvell : NDA document for the discovery system controller 10 * The author referenced two RTEMS network drivers of other NICs.11 * rtems : 1) dec21140.c, a network driver for for TULIP based Ethernet Controller12 * (C) 1999 Emmanuel Raguet. raguet@crf.canon.fr13 *14 * 2) yellowfin.c, a network driver for the SVGM5 BSP.15 * Stanford Linear Accelerator Center, Till Straumann16 10 * 17 11 * Some notes from the author, S. Kate Feng : 18 12 * 19 13 * 1) Mvme5500 uses Eth0 (controller 0) of the GT64260 to implement 20 * the 10/100 BaseT Ethernet with PCI Master Data Byte Swap\ 21 * control. 14 * the 10/100 BaseT Ethernet with PCI Master Data Byte Swap control. 22 15 * 2) Implemented hardware snoop instead of software snoop 23 16 * to ensure SDRAM cache coherency. (Copyright : NDA item) 24 17 * 3) Added S/W support for multi mbuf. (TODO : Let the H/W do it) … … 55 48 #include <sys/sockio.h> /* SIOCADDMULTI, SIOC... */ 56 49 #include <net/if.h> 57 50 #include <net/if_dl.h> 51 #include <net/ethernet.h> 58 52 #include <netinet/in.h> 59 53 #include <netinet/if_ether.h> 60 54 … … 110 104 111 105 #define ET_MINLEN 64 /* minimum message length */ 112 106 113 static int GTeth_ifioctl(struct ifnet *ifp, u_longcmd, caddr_t data);107 static int GTeth_ifioctl(struct ifnet *ifp, ioctl_command_t cmd, caddr_t data); 114 108 static void GTeth_ifstart (struct ifnet *); 115 109 static void GTeth_ifchange(struct GTeth_softc *sc); 116 110 static void GTeth_init_rx_ring(struct GTeth_softc *sc); … … 169 163 outl( ~cause,ETH0_EICR); /* clear the ICR */ 170 164 171 165 if ( (!cause) || (cause & 0x803d00)) { 172 sc->i ntr_errsts[sc->intr_err_ptr2++]=cause;173 sc->intr_err_ptr2 %=INTR_ERR_SIZE; /* Till Straumann */166 sc->if_errsts[sc->if_err_ptr2++]=cause; 167 if (sc->if_err_ptr2 == IF_ERR_BUFSZE) sc->if_err_ptr2=0; 174 168 events |= ERR_EVENT; 175 169 } 176 170 … … 201 195 static rtems_irq_connect_data GT64260ethIrqData={ 202 196 BSP_MAIN_ETH0_IRQ, 203 197 (rtems_irq_hdl) GT64260eth_isr, 204 NULL,198 (rtems_irq_hdl_param) NULL, 205 199 (rtems_irq_enable) GT64260eth_irq_on, 206 200 (rtems_irq_disable) GT64260eth_irq_off, 207 201 (rtems_irq_is_enabled) GT64260eth_irq_is_on, … … 330 324 GTeth_hash_fill(sc); 331 325 #endif 332 326 333 sc->i ntr_err_ptr1=0;334 sc->i ntr_err_ptr2=0;335 for (i=0; i< I NTR_ERR_SIZE; i++) sc->intr_errsts[i]=0;327 sc->if_err_ptr1=0; 328 sc->if_err_ptr2=0; 329 for (i=0; i< IF_ERR_BUFSZE; i++) sc->if_errsts[i]=0; 336 330 337 331 /* initialize the hardware (we are holding the network semaphore at this point) */ 338 332 (void)GT64260eth_init_hw(sc); 339 333 340 334 /* launch network daemon */ 341 342 /* NOTE: 343 * in ss-20011025 (and later) any task created by 'bsdnet_newproc' is 344 * wrapped by code which acquires the network semaphore... 345 */ 346 sc->daemonTid = rtems_bsdnet_newproc(GT_ETH_TASK_NAME,4096,GT64260eth_daemon,arg); 335 sc->daemonTid = rtems_bsdnet_newproc(GT_ETH_TASK_NAME,4096,GT64260eth_daemon,arg); 347 336 348 337 /* Tell the world that we're running */ 349 338 sc->arpcom.ac_if.if_flags |= IFF_RUNNING; … … 364 353 365 354 unit = rtems_bsdnet_parse_driver_name(config, &name); 366 355 if (unit < 0) return 0; 367 368 printk("\nEthernet driver name %s unit %d \n",name, unit); 369 printk("(c) 2004, Brookhaven National Lab. <feng1@bnl.gov> (RTEMS/mvme5500 port)\n"); 356 if ( !strncmp((const char *)name,"autoz",5)) 357 memcpy(name,"gtMHz",5); 358 359 printk("\nAttaching GT64260 built-in 10/100 MHz NIC%d\n", unit); 360 printk("RTEMS-mvme5500 BSP Copyright (c) 2004, Brookhaven National Lab., Shuchen Kate Feng\n"); 370 361 371 362 /* Make certain elements e.g. descriptor lists are aligned. */ 372 363 softc_mem = rtems_bsdnet_malloc(sizeof(*sc) + SOFTC_ALIGN, M_FREE, M_NOWAIT); … … 388 379 /* try to read HW address from the device if not overridden 389 380 * by config 390 381 */ 391 if (config->hardware_address) { 392 memcpy(hwaddr, config->hardware_address, ETHER_ADDR_LEN); 393 } else { 394 printk("Read EEPROM "); 395 for (i = 0; i < 6; i++) 396 hwaddr[i] = ConfVPD_buff[VPD_ENET0_OFFSET+i]; 397 } 382 if (config->hardware_address) 383 memcpy((void *)sc->arpcom.ac_enaddr,(const void *) config->hardware_address, ETHER_ADDR_LEN); 384 else 385 memcpy((void *)sc->arpcom.ac_enaddr, (const void *) &ConfVPD_buff[VPD_ENET0_OFFSET], ETHER_ADDR_LEN); 398 386 399 387 #ifdef GT_DEBUG 400 388 printk("using MAC addr from device:"); 401 for (i = 0; i < ETHER_ADDR_LEN; i++) printk("%x:", hwaddr[i]);389 for (i = 0; i < ETHER_ADDR_LEN; i++) printk("%x:", sc->arpcom.ac_enaddr[i]); 402 390 printk("\n"); 403 391 #endif 404 392 405 memcpy(sc->arpcom.ac_enaddr, hwaddr, ETHER_ADDR_LEN);406 407 393 ifp = &sc->arpcom.ac_if; 408 394 409 395 sc->sc_pcr = inl(ETH0_EPCR); 410 396 sc->sc_pcxr = inl(ETH0_EPCXR); 411 397 sc->sc_intrmask = inl(ETH0_EIMR) | ETH_IR_MIIPhySTC; 412 398 413 printk("address %s\n", ether_sprintf(hwaddr));414 415 399 #ifdef GT_DEBUG 400 printk("address %s\n", ether_sprintf(hwaddr)); 416 401 printk(", pcr %x, pcxr %x ", sc->sc_pcr, sc->sc_pcxr); 417 402 #endif 418 403 … … 511 496 { 512 497 struct ifnet *ifp = &sc->arpcom.ac_if; 513 498 514 #if 0515 499 printf(" Rx Interrupts:%-8lu\n", sc->stats.rxInterrupts); 516 500 printf(" Receive Packets:%-8lu\n", ifp->if_ipackets); 517 501 printf(" Receive errors:%-8lu\n", ifp->if_ierrors); … … 520 504 printf(" Oversized Frames:%-8lu\n", sc->stats.length_errors); 521 505 printf(" Active Rxqs:%-8u\n", sc->rxq_active); 522 506 printf(" Tx Interrupts:%-8lu\n", sc->stats.txInterrupts); 523 #endif524 printf("Multi-BuffTx Packets:%-8lu\n", sc->stats.txMultiBuffPacket);525 printf("Multi-BuffTx max len:%-8lu\n", sc->stats.txMultiMaxLen);526 printf("SingleBuffTx max len:%-8lu\n", sc->stats.txSinglMaxLen);527 printf("Multi-BuffTx maxloop:%-8lu\n", sc->stats.txMultiMaxLoop);528 printf("Tx buffer max len :%-8lu\n", sc->stats.txBuffMaxLen);529 #if 0530 507 printf(" Transmitt Packets:%-8lu\n", ifp->if_opackets); 531 508 printf(" Transmitt errors:%-8lu\n", ifp->if_oerrors); 532 509 printf(" Tx/Rx collisions:%-8lu\n", ifp->if_collisions); 533 510 printf(" Active Txqs:%-8u\n", sc->txq_nactive); 534 #endif535 511 } 536 512 537 513 void GT64260eth_printStats() … … 539 515 GT64260eth_stats(root_GT64260eth_dev); 540 516 } 541 517 542 static int GTeth_ifioctl(struct ifnet *ifp, u_longcmd, caddr_t data)518 static int GTeth_ifioctl(struct ifnet *ifp, ioctl_command_t cmd, caddr_t data) 543 519 { 544 520 struct GTeth_softc *sc = ifp->if_softc; 545 521 struct ifreq *ifr = (struct ifreq *) data; … … 585 561 if (error == ENETRESET) { 586 562 if (ifp->if_flags & IFF_RUNNING) 587 563 GTeth_ifchange(sc); 588 564 else 589 565 error = 0; 590 566 } 591 567 break; … … 862 838 --sc->txq_nactive; 863 839 } 864 840 841 #if 0 865 842 static int txq_high_limit(struct GTeth_softc *sc) 866 843 { 867 844 /* … … 901 878 } /* end if ( TX_RING_SIZE == sc->txq_nactive + TXQ_HiLmt_OFF) */ 902 879 return 0; 903 880 } 881 #endif 904 882 905 883 static int GT64260eth_sendpacket(struct GTeth_softc *sc,struct mbuf *m) 906 884 { … … 916 894 */ 917 895 intrmask = sc->sc_intrmask; 918 896 919 if ( !(m->m_next)) {/* single buffer packet */897 if ( !(m->m_next)) /* single buffer packet */ 920 898 sc->txq_mbuf[index]= m; 921 sc->stats.txSinglMaxLen= MAX(m->m_len, sc->stats.txSinglMaxLen);922 }923 899 else /* multiple mbufs in this packet */ 924 900 { 925 901 struct mbuf *mtp, *mdest; … … 947 923 printk("%d ",mtp->m_len); 948 924 #endif 949 925 len += mtp->m_len; 950 sc->stats.txBuffMaxLen=MAX(mtp->m_len,sc->stats.txBuffMaxLen);951 926 } 952 sc->stats.txMultiMaxLoop=MAX(loop, sc->stats.txMultiMaxLoop);953 927 #if 0 954 928 printk("\n"); 955 929 #endif … … 957 931 /* free old mbuf chain */ 958 932 m_freem(m); 959 933 sc->txq_mbuf[index] = m = mdest; 960 sc->stats.txMultiBuffPacket++;961 sc->stats.txMultiMaxLen= MAX(m->m_len, sc->stats.txMultiMaxLen);962 934 } 963 935 if (m->m_len < ET_MINLEN) m->m_len = ET_MINLEN; 964 936 … … 1137 1109 sc->arpcom.ac_if.if_timer = 0; 1138 1110 } 1139 1111 1140 /* TOCHECK : Should it be about rx or tx ? */1141 1112 static void GTeth_ifchange(struct GTeth_softc *sc) 1142 1113 { 1143 1114 if (GTeth_debug>0) printk("GTeth_ifchange("); 1144 1115 if (GTeth_debug>5) printk("(pcr=%#x,imr=%#x)",inl(ETH0_EPCR),inl(ETH0_EIMR)); 1145 /* printk("SIOCADDMULTI (SIOCDELMULTI): is it about rx or tx ?\n");*/1146 1116 outl(sc->sc_pcr | ETH_EPCR_EN, ETH0_EPCR); 1147 1117 outl(sc->sc_intrmask, ETH0_EIMR); 1148 1118 GTeth_ifstart(&sc->arpcom.ac_if); … … 1445 1415 #endif 1446 1416 } 1447 1417 1418 #ifdef GT64260eth_DEBUG 1448 1419 static void GT64260eth_error(struct GTeth_softc *sc) 1449 1420 { 1450 1421 struct ifnet *ifp = &sc->arpcom.ac_if; 1451 unsigned int intr_status= sc->i ntr_errsts[sc->intr_err_ptr1];1422 unsigned int intr_status= sc->if_errsts[sc->if_err_ptr1]; 1452 1423 1453 1424 /* read and reset the status; because this is written 1454 1425 * by the ISR, we must disable interrupts here … … 1471 1442 else 1472 1443 printk("%s%d: Ghost interrupt ?\n",ifp->if_name, 1473 1444 ifp->if_unit); 1474 sc->i ntr_errsts[sc->intr_err_ptr1++]=0;1475 sc->intr_err_ptr1 %= INTR_ERR_SIZE; /* Till Straumann */1445 sc->if_errsts[sc->if_err_ptr1++]=0; 1446 if (sc->if_err_ptr1 == IF_ERR_BUFSZE) sc->if_err_ptr1=0; 1476 1447 } 1477 1448 #endif 1478 1449 1479 1450 /* The daemon does all of the work; RX, TX and cleaning up buffers/descriptors */ 1480 1451 static void GT64260eth_daemon(void *arg) … … 1484 1455 struct mbuf *m=0; 1485 1456 struct ifnet *ifp=&sc->arpcom.ac_if; 1486 1457 1487 #if 01488 /* see comments in GT64260eth_init(); in newer versions of1489 * rtems, we hold the network semaphore at this point1490 */1491 rtems_semaphore_release(sc->daemonSync);1492 #endif1493 1494 1458 /* NOTE: our creator possibly holds the bsdnet_semaphore. 1495 1459 * since that has PRIORITY_INVERSION enabled, our 1496 1460 * subsequent call to bsdnet_event_receive() will … … 1548 1512 ifp->if_flags &= ~IFF_OACTIVE; 1549 1513 1550 1514 /* Log errors and other uncommon events. */ 1551 if (events & ERR_EVENT) GT64260eth_error(sc); 1515 #ifdef GT64260eth_DEBUG 1516 if (events & ERR_EVENT) GT64260eth_error(sc); 1517 #endif 1552 1518 } /* end for(;;) { rtems_bsdnet_event_receive() .....*/ 1553 1519 1554 1520 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); -
network/if_100MHz/GT64260eth.h
diff -Naur mvme5500.orig/network/if_100MHz/GT64260eth.h mvme5500/network/if_100MHz/GT64260eth.h
old new 4 4 * All rights reserved. 5 5 * 6 6 * RTEMS/Mvme5500 port 2004 by S. Kate Feng, <feng1@bnl.gov>, 7 * under the Deaprtment of Energy contract DE-AC02-98CH10886 7 8 * All rights reserved. 8 9 * 9 10 * Redistribution and use in source and binary forms, with or without … … 50 51 #define RX_RING_SIZE 16 51 52 #define HASH_TABLE_SIZE 16 52 53 #define HASH_DRAM_SIZE HASH_TABLE_SIZE*1024 /* size of DRAM for hash table */ 53 #define I NTR_ERR_SIZE 1654 #define IF_ERR_BUFSZE 16 54 55 55 56 enum GTeth_txprio { 56 57 GE_TXPRIO_HI=1, … … 70 71 struct mbuf* txq_mbuf[TX_RING_SIZE]; /* transmit buffer memory */ 71 72 struct mbuf* rxq_mbuf[RX_RING_SIZE]; /* receive buffer memory */ 72 73 struct GTeth_softc *next_module; 73 volatile unsigned int i ntr_errsts[INTR_ERR_SIZE]; /* capture the right intr_status */74 unsigned int i ntr_err_ptr1; /* ptr used in GTeth_error() */75 unsigned int i ntr_err_ptr2; /* ptr used in ISR */74 volatile unsigned int if_errsts[IF_ERR_BUFSZE]; /* capture the right intr_status */ 75 unsigned int if_err_ptr1; /* ptr used in GTeth_error() */ 76 unsigned int if_err_ptr2; /* ptr used in ISR */ 76 77 struct ifqueue txq_pendq; /* these are ready to go to the GT */ 77 78 unsigned int txq_pending; 78 79 unsigned int txq_lo; /* next to be given to GT DMA */ … … 125 126 /* statistics */ 126 127 struct { 127 128 volatile unsigned long rxInterrupts; 128 129 129 volatile unsigned long txInterrupts; 130 unsigned long txMultiBuffPacket;131 unsigned long txMultiMaxLen;132 unsigned long txSinglMaxLen;133 unsigned long txMultiMaxLoop;134 unsigned long txBuffMaxLen;135 130 unsigned long length_errors; 136 131 unsigned long frame_errors; 137 132 unsigned long crc_errors; -
network/if_100MHz/GT64260ethreg.h
diff -Naur mvme5500.orig/network/if_100MHz/GT64260ethreg.h mvme5500/network/if_100MHz/GT64260ethreg.h
old new 1 1 /* $NetBSD: GT64260ethreg.h,v 1.2 2003/03/17 16:41:16 matt Exp $ */ 2 /* $Id: GT64260ethreg.h,v 1. 1 2007/09/13 14:26:24joel Exp $ */2 /* $Id: GT64260ethreg.h,v 1.2 2004/10/20 18:28:00 joel Exp $ */ 3 3 4 4 /* 5 5 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc. -
network/if_1GHz/if_wm.c
diff -Naur mvme5500.orig/network/if_1GHz/if_wm.c mvme5500/network/if_1GHz/if_wm.c
old new 1 1 /* 2 * Copyright (c) 2004,2005 RTEMS/Mvme5500 port by S. Kate Feng <feng1@bnl.gov> 2 * Copyright (c) 2004,2005, 2008 RTEMS/Mvme5500 port by S. Kate Feng <feng1@bnl.gov> 3 * under the Deaprtment of Energy contract DE-AC02-98CH10886 3 4 * Brookhaven National Laboratory, All rights reserved 4 5 * 5 6 * Acknowledgements: … … 25 26 * hardware auto-neg. state machine disabled. PCI control "snoop 26 27 * to WB region", MII mode (PHY) instead of TBI mode. 27 28 * 6) We currently only use 32-bit (instead of 64-bit) DMA addressing. 28 * 7) Support for checksum offloading and TCP segmentation offload will 29 * be available for releasing in 2008, upon request, if I still believe. 29 * 7) Implementation for Jumbo Frame and TCP checksum is not yet completed. 30 30 * 31 31 */ 32 32 … … 34 34 35 35 #define INET 36 36 37 /*#define RTEMS_ETHERMTU_JUMBO*/ 38 37 39 #include <rtems.h> 38 40 #include <rtems/bspIo.h> /* printk */ 41 39 42 #include <stdio.h> /* printf for statistics */ 40 43 #include <string.h> 41 44 … … 64 67 #include <net/if_dl.h> 65 68 #include <netinet/in.h> 66 69 #include <netinet/if_ether.h> 70 #include <net/ethernet.h> 67 71 68 72 #ifdef INET 69 73 #include <netinet/in_var.h> … … 82 86 #define i82544EI_TASK_NAME "IGHZ" 83 87 #define SOFTC_ALIGN 4095 84 88 85 #define I NTR_ERR_SIZE 1689 #define IF_ERR_BUFSZE 16 86 90 87 91 /*#define WM_DEBUG*/ 88 92 #ifdef WM_DEBUG … … 109 113 110 114 #define ALL_EVENTS (KILL_EVENT|START_TRANSMIT_EVENT|RX_EVENT|TX_EVENT|ERR_EVENT|INIT_EVENT) 111 115 112 113 #define NTXDESC 128116 /* <skf> used 64 in 4.8.0, TOD; try 4096 */ 117 #define NTXDESC 256 114 118 #define NTXDESC_MASK (NTXDESC - 1) 115 119 #define WM_NEXTTX(x) (((x) + 1) & NTXDESC_MASK) 116 120 117 #define NRXDESC 64121 #define NRXDESC 256 118 122 #define NRXDESC_MASK (NRXDESC - 1) 119 123 #define WM_NEXTRX(x) (((x) + 1) & NRXDESC_MASK) 120 124 #define WM_PREVRX(x) (((x) - 1) & NRXDESC_MASK) … … 123 127 #define WM_CDTXOFF(x) WM_CDOFF(sc_txdescs[(x)]) 124 128 #define WM_CDRXOFF(x) WM_CDOFF(sc_rxdescs[(x)]) 125 129 126 #define TXQ_HiLmt_OFF 64130 #define TXQ_HiLmt_OFF 32 127 131 128 132 static uint32_t TxDescCmd; 133 static unsigned BSP_1GHz_membase; 129 134 130 135 /* 131 136 * Software state per device. … … 136 141 struct mbuf *txs_mbuf[NTXDESC]; /* transmit buffer memory */ 137 142 struct mbuf *rxs_mbuf[NRXDESC]; /* receive buffer memory */ 138 143 struct wm_softc *next_module; 139 volatile unsigned int i ntr_errsts[INTR_ERR_SIZE]; /* intr_status */140 unsigned int i ntr_err_ptr1; /* ptr used in i82544EI_error() */141 unsigned int i ntr_err_ptr2; /* ptr used in ISR */144 volatile unsigned int if_errsts[IF_ERR_BUFSZE]; /* intr_status */ 145 unsigned int if_err_ptr1; /* ptr used in i82544EI_error() */ 146 unsigned int if_err_ptr2; /* ptr used in ISR */ 142 147 int txs_firstdesc; /* first descriptor in packet */ 143 148 int txs_lastdesc; /* last descriptor in packet */ 144 149 int txs_ndesc; /* # of descriptors used */ … … 168 173 int sc_rxptr; /* next ready Rx descriptor/queue ent */ 169 174 int sc_rxdiscard; 170 175 int sc_rxlen; 176 171 177 uint32_t sc_ctrl; /* prototype CTRL register */ 172 #if 0173 178 uint32_t sc_ctrl_ext; /* prototype CTRL_EXT register */ 174 #endif 179 175 180 uint32_t sc_icr; /* prototype interrupt bits */ 176 181 uint32_t sc_tctl; /* prototype TCTL register */ 177 182 uint32_t sc_rctl; /* prototype RCTL register */ 178 183 uint32_t sc_tipg; /* prototype TIPG register */ 179 184 uint32_t sc_fcrtl; /* prototype FCRTL register */ 185 uint32_t sc_pba; /* prototype PBA register */ 180 186 181 187 int sc_mchash_type; /* multicast filter offset */ 182 188 … … 184 190 struct { 185 191 volatile unsigned long rxInterrupts; 186 192 volatile unsigned long txInterrupts; 187 unsigned long txMultiBuffPacket;188 unsigned long txMultiMaxLen;189 unsigned long txSinglMaxLen;190 unsigned long txMultiMaxLoop;191 unsigned long txBuffMaxLen;192 193 unsigned long linkInterrupts; 193 194 unsigned long length_errors; 194 195 unsigned long frame_errors; … … 224 225 static struct wm_softc *root_i82544EI_dev = NULL; 225 226 226 227 static void i82544EI_ifstart(struct ifnet *ifp); 227 static int wm_ioctl(struct ifnet *ifp, u_long cmd,uint32_t data);228 static int wm_ioctl(struct ifnet *ifp, ioctl_command_t cmd,caddr_t data); 228 229 static void i82544EI_ifinit(void *arg); 229 230 static void wm_stop(struct ifnet *ifp, int disable); 231 static void wm_gmii_mediainit(struct wm_softc *sc); 230 232 231 233 static void wm_rxdrain(struct wm_softc *sc); 232 234 static int wm_add_rxbuf(struct wm_softc *sc, int idx); 233 235 static int wm_read_eeprom(struct wm_softc *sc,int word,int wordcnt, uint16_t *data); 234 236 static void i82544EI_daemon(void *arg); 235 237 static void wm_set_filter(struct wm_softc *sc); 236 237 static void i82544EI_isr( );238 static void i82544EI_rx(struct wm_softc *sc); 239 static void i82544EI_isr(rtems_irq_hdl_param handle); 238 240 static void i82544EI_sendpacket(struct wm_softc *sc, struct mbuf *m); 239 241 extern int pci_mem_find(), pci_io_find(), pci_get_capability(); 240 extern char * ether_sprintf1();241 242 242 243 static void i82544EI_irq_on(const rtems_irq_connect_data *irq) 243 244 { … … 269 270 static rtems_irq_connect_data i82544IrqData={ 270 271 BSP_GPP_82544_IRQ, 271 272 (rtems_irq_hdl) i82544EI_isr, 273 (rtems_irq_hdl_param) NULL, 272 274 (rtems_irq_enable) i82544EI_irq_on, 273 275 (rtems_irq_disable) i82544EI_irq_off, 274 276 (rtems_irq_is_enabled) i82544EI_irq_is_on, … … 288 290 289 291 unit = rtems_bsdnet_parse_driver_name(config, &name); 290 292 if (unit < 0) return 0; 291 292 printk("\nEthernet driver name %s unit %d \n",name, unit); 293 printk("Copyright (c) 2004,2005 S. Kate Feng <feng1@bnl.gov> (RTEMS/mvme5500 port)\n"); 293 294 if ( !strncmp((const char *)name,"autoz",5)) 295 memcpy(name,"gtGHz",5); 296 297 printk("\nAttaching MVME5500 1GHz NIC%d\n", unit); 298 printk("RTEMS-mvme5500 BSP Copyright (c) 2004,2005,2008 Shuchen Kate Feng \n"); 294 299 295 300 /* Make sure certain elements e.g. descriptor lists are aligned.*/ 296 301 softc_mem = rtems_bsdnet_malloc(sizeof(*sc) + SOFTC_ALIGN, M_FREE, M_NOWAIT); … … 316 321 if ( pci_mem_find(b,d,f,PCI_MAPREG_START, &sc->sc_membase, &sc->sc_memsize)) 317 322 rtems_panic("i82544EI: unable to map memory space\n"); 318 323 324 printk("Memory base addr 0x%x\n", sc->sc_membase); 325 BSP_1GHz_membase= sc->sc_membase; 326 319 327 #ifdef WM_DEBUG 320 328 printk("Memory base addr 0x%x\n", sc->sc_membase); 321 329 printk("txdesc[0] addr:0x%x, rxdesc[0] addr:0x%x, sizeof sc %d\n",&sc->sc_txdescs[0], &sc->sc_rxdescs[0], sizeof(*sc)); 322 330 #endif 323 331 324 332 325 sc->sc_ctrl |=CSR_READ(sc,WMREG_CTRL);333 sc->sc_ctrl=CSR_READ(sc,WMREG_CTRL); 326 334 /* 327 335 * Determine a few things about the bus we're connected to. 328 336 */ … … 360 368 enaddr[4] = myea[2] & 0xff; 361 369 enaddr[5] = myea[2] >> 8; 362 370 363 364 371 memcpy(sc->arpcom.ac_enaddr, enaddr, ETHER_ADDR_LEN); 365 372 #ifdef WM_DEBUG 366 373 printk("%s: Ethernet address %s\n", sc->dv_xname, 367 ether_sprintf 1(enaddr));374 ether_sprintf(enaddr)); 368 375 #endif 369 376 370 377 /* … … 395 402 CSR_WRITE(sc,WMREG_CTRL_EXT, sc->sc_ctrl_ext); 396 403 #endif 397 404 405 /* 406 * Determine if we're TBI or GMII mode, and initialize the 407 * media structures accordingly. 408 */ 409 if ((CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) { 410 /* 1000BASE-X : fiber (TBI mode) 411 wm_tbi_mediainit(sc); */ 412 } else { /* 1000BASE-T : copper (internal PHY mode), for the mvme5500 */ 413 wm_gmii_mediainit(sc); 414 } 415 398 416 ifp = &sc->arpcom.ac_if; 399 417 /* set this interface's name and unit */ 400 418 ifp->if_unit = unit; 401 419 ifp->if_name = name; 402 420 ifp->if_softc = sc; 403 421 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 422 #ifdef RTEMS_ETHERMTU_JUMBO 423 sc->arpcom.ec_capabilities |= ETHERCAP_JUMBO_MTU; 424 ifp->if_mtu = config->mtu ? config->mtu : ETHERMTU_JUMBO; 425 #else 404 426 ifp->if_mtu = config->mtu ? config->mtu : ETHERMTU; 427 #endif 428 #ifdef RTEMS_CKSUM_OFFLOAD 429 /* < skf> The following is really not related to jumbo frame 430 sc->arpcom.ec_capabilities |= ETHERCAP_VLAN_MTU;*/ 431 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 432 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 433 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 434 IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx | 435 IFCAP_TSOv4; /* TCP segmentation offload. */ 436 #endif 437 405 438 ifp->if_ioctl = wm_ioctl; 406 439 ifp->if_start = i82544EI_ifstart; 407 440 /* ifp->if_watchdog = wm_watchdog;*/ … … 416 449 rtems_build_name('I','G','H','Z'),0,0,0,&sc->daemonSync)) 417 450 rtems_panic("i82544EI: semaphore creation failed"); 418 451 419 sc->next_module = root_i82544EI_dev; 452 i82544IrqData.handle= (rtems_irq_hdl_param) sc; 453 /* sc->next_module = root_i82544EI_dev;*/ 420 454 root_i82544EI_dev = sc; 421 455 422 456 /* Attach the interface. */ … … 430 464 } 431 465 432 466 /* 467 * wm_reset: 468 * 469 * Reset the i82544 chip. 470 */ 471 static void wm_reset(struct wm_softc *sc) 472 { 473 int i; 474 475 sc->sc_pba = sc->arpcom.ac_if.if_mtu > 8192 ? PBA_40K : PBA_48K; 476 CSR_WRITE(sc, WMREG_PBA, sc->sc_pba); 477 478 /* device reset */ 479 CSR_WRITE(sc, WMREG_CTRL, CTRL_RST); 480 rtems_bsp_delay(10000); 481 482 for (i = 0; i < 1000; i++) { 483 if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0) 484 break; 485 rtems_bsp_delay(20); 486 } 487 if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST) 488 printk("Intel 82544 1GHz reset failed to complete\n"); 489 490 sc->sc_ctrl_ext = CSR_READ(sc,WMREG_CTRL_EXT); 491 sc->sc_ctrl_ext |= CTRL_EXT_EE_RST; 492 CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 493 CSR_READ(sc, WMREG_STATUS); 494 /* Wait for EEPROM reload */ 495 rtems_bsp_delay(2000); 496 sc->sc_ctrl= CSR_READ(sc, WMREG_CTRL); 497 } 498 499 /* 433 500 * i82544EI_ifstart: [ifnet interface function] 434 501 * 435 502 * Start packet transmission on the interface. … … 461 528 { 462 529 struct ifnet *ifp = &sc->arpcom.ac_if; 463 530 464 printf(" Rx Interrupts:%-8u\n", sc->stats.rxInterrupts); 531 printf(" Ghost Interrupts:%-8lu\n", sc->stats.ghostInterrupts); 532 printf(" Rx Interrupts:%-8lu\n", sc->stats.rxInterrupts); 465 533 printf(" Receive Packets:%-8u\n", CSR_READ(sc,WMREG_GPRC)); 466 printf(" Receive Overrun:%-8 u\n", sc->stats.rxOvrRunInterrupts);534 printf(" Receive Overrun:%-8lu\n", sc->stats.rxOvrRunInterrupts); 467 535 printf(" Receive errors:%-8u\n", CSR_READ(sc,WMREG_RXERRC)); 468 printf(" Rx sequence error:%-8 u\n", sc->stats.rxSeqErr);469 printf(" Rx /C/ ordered:%-8 u\n", sc->stats.rxC_ordered);536 printf(" Rx sequence error:%-8lu\n", sc->stats.rxSeqErr); 537 printf(" Rx /C/ ordered:%-8lu\n", sc->stats.rxC_ordered); 470 538 printf(" Rx Length Errors:%-8u\n", CSR_READ(sc,WMREG_RLEC)); 471 printf(" Tx Interrupts:%-8u\n", sc->stats.txInterrupts); 472 #if 0 473 printf("Multi-BuffTx Packets:%-8u\n", sc->stats.txMultiBuffPacket); 474 printf("Multi-BuffTx max len:%-8u\n", sc->stats.txMultiMaxLen); 475 printf("SingleBuffTx max len:%-8u\n", sc->stats.txSinglMaxLen); 476 printf("Multi-BuffTx maxloop:%-8u\n", sc->stats.txMultiMaxLoop); 477 printf("Tx buffer max len :%-8u\n", sc->stats.txBuffMaxLen); 478 #endif 539 printf(" Tx Interrupts:%-8lu\n", sc->stats.txInterrupts); 479 540 printf(" Transmitt Packets:%-8u\n", CSR_READ(sc,WMREG_GPTC)); 480 printf(" Transmitt errors:%-8 u\n", ifp->if_oerrors);481 printf(" Active Txqs:%-8 u\n", sc->txq_nactive);541 printf(" Transmitt errors:%-8lu\n", ifp->if_oerrors); 542 printf(" Active Txqs:%-8lu\n", sc->txq_nactive); 482 543 printf(" collisions:%-8u\n", CSR_READ(sc,WMREG_COLC)); 483 544 printf(" Crc Errors:%-8u\n", CSR_READ(sc,WMREG_CRCERRS)); 484 printf(" Link Status Change:%-8 u\n", sc->stats.linkStatusChng);545 printf(" Link Status Change:%-8lu\n", sc->stats.linkStatusChng); 485 546 } 486 547 487 548 /* … … 489 550 * 490 551 * Handle control requests from the operator. 491 552 */ 492 static int wm_ioctl(struct ifnet *ifp, u_long cmd,uint32_t data)553 static int wm_ioctl(struct ifnet *ifp, ioctl_command_t cmd,caddr_t data) 493 554 { 494 555 struct wm_softc *sc = ifp->if_softc; 495 556 int error=0; … … 521 582 * 522 583 * Interrupt service routine. 523 584 */ 524 static void i82544EI_isr( )585 static void i82544EI_isr(rtems_irq_hdl_param handle) 525 586 { 526 volatile struct wm_softc *sc = root_i82544EI_dev;587 volatile struct wm_softc *sc = (struct wm_softc *) handle; 527 588 uint32_t icr; 528 589 rtems_event_set events=0; 529 590 … … 547 608 events |= INIT_EVENT; 548 609 } 549 610 if (icr & ICR_RXSEQ) /* framing error */ { 550 sc->i ntr_errsts[sc->intr_err_ptr2++]=icr;551 sc->intr_err_ptr2 %=INTR_ERR_SIZE; /* Till Straumann */611 sc->if_errsts[sc->if_err_ptr2++]=icr; 612 if ( sc->if_err_ptr2 ==IF_ERR_BUFSZE) sc->if_err_ptr2=0; 552 613 events |= ERR_EVENT; 553 614 sc->stats.rxSeqErr++; 554 615 } … … 606 667 * The other way is effective for packets < 2K 607 668 */ 608 669 if ( ((y=(len+mtp->m_len)) > sizeof(union mcluster))) { 609 printk(" >2048, use next descriptor\n");670 printk(" >%d, use next descriptor\n", sizeof(union mcluster)); 610 671 break; 611 672 } 612 673 memcpy((void *)pt,(char *)mtp->m_data, mtp->m_len); 613 674 pt += mtp->m_len; 614 675 len += mtp->m_len; 615 #if 0616 sc->stats.txSinglMaxLen= MAX(mtp->m_len, sc->stats.txSinglMaxLen);617 #endif618 676 } /* end for loop */ 619 677 mdest->m_len=len; 620 678 sc->txs_mbuf[sc->txq_next] = mdest; … … 628 686 sc->txq_free--; 629 687 else 630 688 rtems_panic("i8254EI : no more free descriptors"); 631 #if 0632 sc->stats.txMultiMaxLen= MAX(mdest->m_len, sc->stats.txMultiMaxLen);633 sc->stats.txMultiBuffPacket++;634 #endif635 689 } /* end for while */ 636 690 /* free old mbuf chain */ 637 #if 0638 sc->stats.txMultiMaxLoop=MAX(loop, sc->stats.txMultiMaxLoop);639 #endif640 691 m_freem(m); 641 692 m=0; 642 693 } /* end multiple mbufs */ … … 742 793 sc->dv_xname, i)); 743 794 744 795 status = sc->sc_rxdescs[i].wrx_status; 796 if ((status & WRX_ST_DD) == 0) break; /* descriptor not done */ 797 745 798 errors = sc->sc_rxdescs[i].wrx_errors; 746 799 len = le16toh(sc->sc_rxdescs[i].wrx_len); 747 800 m = sc->rxs_mbuf[i]; 748 749 if ((status & WRX_ST_DD) == 0) break; /* descriptor not done */750 751 801 if (sc->sc_rxdiscard) { 752 802 printk("RX: discarding contents of descriptor %d\n", i); 753 803 wm_init_rxdesc(sc, i); … … 819 869 int i,error; 820 870 uint8_t cksumfields; 821 871 872 #if 0 873 /* KATETODO : sc_align_tweak */ 874 /* 875 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set. 876 * There is a small but measurable benefit to avoiding the adjusment 877 * of the descriptor so that the headers are aligned, for normal mtu, 878 * on such platforms. One possibility is that the DMA itself is 879 * slightly more efficient if the front of the entire packet (instead 880 * of the front of the headers) is aligned. 881 * 882 * Note we must always set align_tweak to 0 if we are using 883 * jumbo frames. 884 */ 885 #ifdef __NO_STRICT_ALIGNMENT 886 sc->sc_align_tweak = 0; 887 #else 888 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2)) 889 sc->sc_align_tweak = 0; 890 else 891 sc->sc_align_tweak = 2; 892 #endif /* __NO_STRICT_ALIGNMENT */ 893 #endif 894 822 895 /* Cancel any pending I/O. */ 823 896 wm_stop(ifp, 0); 824 897 898 /* update statistics before reset */ 899 ifp->if_collisions += CSR_READ(sc, WMREG_COLC); 900 ifp->if_ierrors += CSR_READ(sc, WMREG_RXERRC); 901 902 /* Reset the chip to a known state. */ 903 wm_reset(sc); 904 825 905 /* Initialize the error buffer ring */ 826 sc->i ntr_err_ptr1=0;827 sc->i ntr_err_ptr2=0;828 for (i=0; i< I NTR_ERR_SIZE; i++) sc->intr_errsts[i]=0;906 sc->if_err_ptr1=0; 907 sc->if_err_ptr2=0; 908 for (i=0; i< IF_ERR_BUFSZE; i++) sc->if_errsts[i]=0; 829 909 830 910 /* Initialize the transmit descriptor ring. */ 831 memset( sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));911 memset( (void *) sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 832 912 sc->txq_free = NTXDESC; 833 913 sc->txq_next = 0; 834 914 sc->txs_lastdesc = 0; … … 847 927 CSR_WRITE(sc,WMREG_TDLEN, sizeof(sc->sc_txdescs)); 848 928 CSR_WRITE(sc,WMREG_TDH, 0); 849 929 CSR_WRITE(sc,WMREG_TDT, 0); 850 CSR_WRITE(sc,WMREG_TIDV, 64);851 CSR_WRITE(sc,WMREG_TADV, 128);930 CSR_WRITE(sc,WMREG_TIDV, 0 ); 931 /* CSR_WRITE(sc,WMREG_TADV, 128); not for 82544 */ 852 932 853 933 CSR_WRITE(sc,WMREG_TXDCTL, TXDCTL_PTHRESH(0) | 854 934 TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0)); … … 862 942 * Set up checksum offload parameters for 863 943 * this packet. 864 944 */ 865 #ifdef CKSUM_OFFLOAD 866 if (m0->m_pkthdr.csum_flags & 867 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) { 868 if (wm_tx_cksum(sc, txs, &TxDescCmd,&cksumfields) != 0) { 945 #ifdef RTEMS_CKSUM_OFFLOAD 946 if (m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4|M_CSUM_TSOv6| 947 M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4| 948 M_CSUM_TCPv6|M_CSUM_UDPv6)) { 949 if (wm_tx_offload(sc, txs, &TxDescCmd,&cksumfields) != 0) { 869 950 /* Error message already displayed. */ 870 951 continue; 871 952 } … … 873 954 #endif 874 955 TxDescCmd = 0; 875 956 cksumfields = 0; 876 #ifdef CKSUM_OFFLOAD957 #ifdef RTEMS_CKSUM_OFFLOAD 877 958 } 878 959 #endif 879 960 … … 892 973 * Initialize the receive descriptor and receive job 893 974 * descriptor rings. 894 975 */ 895 memset( sc->sc_rxdescs, 0, sizeof(sc->sc_rxdescs));976 memset( (void *) sc->sc_rxdescs, 0, sizeof(sc->sc_rxdescs)); 896 977 CSR_WRITE(sc,WMREG_RDBAH, 0); 897 978 CSR_WRITE(sc,WMREG_RDBAL, WM_CDRXADDR(sc)); 898 979 CSR_WRITE(sc,WMREG_RDLEN, sizeof(sc->sc_rxdescs)); 899 980 CSR_WRITE(sc,WMREG_RDH, 0); 900 981 CSR_WRITE(sc,WMREG_RDT, 0); 901 982 CSR_WRITE(sc,WMREG_RDTR, 0 |RDTR_FPD); 902 CSR_WRITE(sc, WMREG_RADV, 256);983 /* CSR_WRITE(sc, WMREG_RADV, 256); not for 82544. */ 903 984 904 985 for (i = 0; i < NRXDESC; i++) { 905 986 if (sc->rxs_mbuf[i] == NULL) { … … 943 1024 944 1025 CSR_WRITE(sc,WMREG_FCRTH, FCRTH_DFLT); 945 1026 CSR_WRITE(sc,WMREG_FCRTL, sc->sc_fcrtl); 946 CSR_WRITE(sc,WMREG_FCTTV, FCTTV_DFLT); 1027 /*KATETO CSR_WRITE(sc,WMREG_FCTTV, FCTTV_DFLT);*/ 1028 CSR_WRITE(sc,WMREG_FCTTV, 0x100); 947 1029 948 1030 sc->sc_ctrl &= ~CTRL_VME; 949 /* sc->sc_ctrl |= CTRL_TFCE | CTRL_RFCE;*/950 /* enable Big Endian Mode for the powerPC951 sc->sc_ctrl |= CTRL_BEM;*/1031 /* KATETODo : not here. 1032 Configures flow control settings after link is established 1033 sc->sc_ctrl |= CTRL_TFCE | CTRL_RFCE; */ 952 1034 953 1035 /* Write the control registers. */ 954 1036 CSR_WRITE(sc,WMREG_CTRL, sc->sc_ctrl); … … 956 1038 CSR_WRITE(sc,WMREG_CTRL_EXT, sc->sc_ctrl_ext); 957 1039 #endif 958 1040 959 /* MOTLoad : WMREG_RXCSUM (0x5000)= 0, no Rx checksum offloading */ 1041 /* MOTLoad : WMREG_RXCSUM (0x5000)= 0, no Rx checksum offloading */ 1042 #ifdef RTEMS_CKSUM_OFFLOAD 1043 /* 1044 * Set up checksum offload parameters. 1045 */ 1046 reg = CSR_READ(sc, WMREG_RXCSUM); 1047 reg &= ~(RXCSUM_IPOFL | RXCSUM_IPV6OFL | RXCSUM_TUOFL); 1048 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1049 reg |= RXCSUM_IPOFL; 1050 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 1051 reg |= RXCSUM_IPOFL | RXCSUM_TUOFL; 1052 if (ifp->if_capenable & (IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx)) 1053 reg |= RXCSUM_IPV6OFL | RXCSUM_TUOFL; 1054 CSR_WRITE(sc, WMREG_RXCSUM, reg); 1055 #endif 960 1056 961 1057 /* 962 1058 * Set up the interrupt registers. … … 985 1081 * we resolve the media type. 986 1082 */ 987 1083 sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) | 988 TCTL_COLD(TX_COLLISION_DISTANCE_FDX) | TCTL_RTLC; /*transmitter enable*/ 1084 TCTL_COLD(TX_COLLISION_DISTANCE_FDX) | 1085 TCTL_RTLC /* transmit on late collision */; 989 1086 990 1087 /* 991 1088 * Set up the receive control register; we actually program … … 993 1090 * address offset type 0. 994 1091 * 995 1092 * Only the i82544 has the ability to strip the incoming 996 * CRC, so we don't enable that feature. (TODO )1093 * CRC, so we don't enable that feature. (TODO: |RCTL_SECRC) 997 1094 */ 998 1095 sc->sc_mchash_type = 0; 999 1096 sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_LPE | 1000 RCTL_DPF | RCTL_MO(sc->sc_mchash_type);1097 RCTL_DPF | RCTL_MO(sc->sc_mchash_type)|RCTL_SECRC; 1001 1098 1002 /* (MCLBYTES == 2048) */ 1003 sc->sc_rctl |= RCTL_2k; 1099 if (MCLBYTES == 2048) { 1100 sc->sc_rctl |= RCTL_2k; 1101 } else { 1102 switch(MCLBYTES) { 1103 case 4096: 1104 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k; 1105 break; 1106 case 8192: 1107 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k; 1108 break; 1109 case 16384: 1110 sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k; 1111 break; 1112 default: 1113 rtems_panic("wm_init: MCLBYTES %d unsupported", 1114 MCLBYTES); 1115 break; 1116 } 1117 } 1004 1118 1005 1119 #ifdef WM_DEBUG 1006 1120 printk("RDBAL 0x%x,RDLEN %d, RDT %d\n",CSR_READ(sc,WMREG_RDBAL),CSR_READ(sc,WMREG_RDLEN), CSR_READ(sc,WMREG_RDT)); … … 1018 1132 return(0); 1019 1133 } 1020 1134 1135 void BSP_rdTIDV() 1136 { 1137 printf("Reg TIDV: 0x%x\n", in_le32((volatile unsigned *) (BSP_1GHz_membase+WMREG_TIDV))); 1138 } 1139 void BSP_rdRDTR() 1140 { 1141 printf("Reg RDTR: 0x%x\n", in_le32((volatile unsigned *) (BSP_1GHz_membase+WMREG_RDTR))); 1142 } 1143 1144 void BSP_setTIDV(int val) 1145 { 1146 out_le32((volatile unsigned *) (BSP_1GHz_membase+WMREG_TIDV), val); 1147 } 1148 1149 void BSP_setRDTR(int val) 1150 { 1151 out_le32((volatile unsigned *) (BSP_1GHz_membase+WMREG_RDTR), val); 1152 } 1021 1153 /* 1022 1154 * i82544EI_ifinit: [ifnet interface function] 1023 1155 * … … 1233 1365 return (0); 1234 1366 } 1235 1367 1368 #if 0 1236 1369 /* 1237 1370 * wm_acquire_eeprom: 1238 1371 * … … 1264 1397 1265 1398 return (0); 1266 1399 } 1400 #endif 1267 1401 1268 1402 /* 1269 1403 * wm_read_eeprom: … … 1368 1502 mta_reg = WMREG_CORDOVA_MTA; 1369 1503 sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE); 1370 1504 1371 /* if (ifp->if_flags & IFF_BROADCAST)*/1505 if (ifp->if_flags & IFF_BROADCAST) 1372 1506 sc->sc_rctl |= RCTL_BAM; 1373 1507 if (ifp->if_flags & IFF_PROMISC) { 1374 1508 sc->sc_rctl |= RCTL_UPE; … … 1438 1572 static void i82544EI_error(struct wm_softc *sc) 1439 1573 { 1440 1574 struct ifnet *ifp = &sc->arpcom.ac_if; 1441 unsigned long intr_status= sc->i ntr_errsts[sc->intr_err_ptr1++];1575 unsigned long intr_status= sc->if_errsts[sc->if_err_ptr1]; 1442 1576 1443 1577 /* read and reset the status; because this is written 1444 1578 * by the ISR, we must disable interrupts here 1445 1579 */ 1446 sc->intr_err_ptr1 %=INTR_ERR_SIZE; /* Till Straumann */1447 1580 if (intr_status) { 1448 1581 printk("Error %s%d:", ifp->if_name, ifp->if_unit); 1449 1582 if (intr_status & ICR_RXSEQ) { … … 1453 1586 } 1454 1587 else 1455 1588 printk("%s%d: Ghost interrupt ?\n",ifp->if_name,ifp->if_unit); 1589 sc->if_errsts[sc->if_err_ptr1++]=0; 1590 if (sc->if_err_ptr1 == IF_ERR_BUFSZE) sc->if_err_ptr1=0; 1456 1591 } 1457 1592 1458 1593 void i82544EI_printStats() … … 1493 1628 &events); 1494 1629 if (KILL_EVENT & events) break; 1495 1630 1496 if (events & RX_EVENT) i82544EI_rx(sc); 1631 if (events & RX_EVENT) i82544EI_rx(sc); /* in ISR instead */ 1497 1632 1498 1633 /* clean up and try sending packets */ 1499 1634 do { … … 1501 1636 1502 1637 while (sc->txq_free>0) { 1503 1638 if (sc->txq_free>TXQ_HiLmt_OFF) { 1639 m=0; 1504 1640 IF_DEQUEUE(&ifp->if_snd,m); 1505 1641 if (m==0) break; 1506 1642 i82544EI_sendpacket(sc, m); … … 1509 1645 i82544EI_txq_done(sc); 1510 1646 break; 1511 1647 } 1512 if (events & RX_EVENT) i82544EI_rx(sc);1513 1648 } 1514 1649 /* we leave this loop 1515 1650 * - either because there's no free buffer … … 1517 1652 * - or there's nothing to send (IF_DEQUEUE 1518 1653 * returned 0 1519 1654 */ 1520 } while (m && sc->txq_free);1655 } while (m); 1521 1656 1522 1657 ifp->if_flags &= ~IFF_OACTIVE; 1523 1658 … … 1554 1689 */ 1555 1690 rtems_task_delete(RTEMS_SELF); 1556 1691 } 1692 1693 /* 1694 * wm_gmii_reset: 1695 * 1696 * Reset the PHY. 1697 */ 1698 static void wm_gmii_reset(struct wm_softc *sc) 1699 { 1700 1701 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET); 1702 rtems_bsp_delay(20000); 1703 1704 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 1705 rtems_bsp_delay(20000); 1706 1707 } 1708 1709 /* 1710 * wm_gmii_mediainit: 1711 * 1712 * Initialize media for use on 1000BASE-T devices. 1713 */ 1714 static void wm_gmii_mediainit(struct wm_softc *sc) 1715 { 1716 /* struct ifnet *ifp = &sc->arpcom.ac_if;*/ 1717 1718 /* We have MII. */ 1719 sc->sc_flags |= WM_F_HAS_MII; 1720 1721 sc->sc_tipg = TIPG_1000T_DFLT; /* 0x602008 */ 1722 1723 /* 1724 * Let the chip set speed/duplex on its own based on 1725 * signals from the PHY. 1726 * XXXbouyer - I'm not sure this is right for the 80003, 1727 * the em driver only sets CTRL_SLU here - but it seems to work. 1728 */ 1729 sc->sc_ctrl |= CTRL_SLU; 1730 CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl); 1731 1732 wm_gmii_reset(sc); 1733 1734 #if 0 1735 /* Initialize our media structures and probe the GMII. */ 1736 sc->sc_mii.mii_ifp = ifp; 1737 1738 sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg; 1739 sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg; 1740 sc->sc_mii.mii_statchg = wm_gmii_statchg; 1741 1742 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange, 1743 wm_gmii_mediastatus); 1744 1745 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1746 MII_OFFSET_ANY, MIIF_DOPAUSE); 1747 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1748 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1749 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1750 } else 1751 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1752 #endif 1753 } -
network/if_1GHz/if_wmreg.h
diff -Naur mvme5500.orig/network/if_1GHz/if_wmreg.h mvme5500/network/if_1GHz/if_wmreg.h
old new 5 5 * All rights reserved. 6 6 * 7 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * Some are added by Shuchen Kate Feng <feng1@bnl.gov>, 9 * NSLS, Brookhaven National Laboratory. All rights reserved. 10 * under the Deaprtment of Energy contract DE-AC02-98CH10886 8 11 * 9 12 * Redistribution and use in source and binary forms, with or without 10 13 * modification, are permitted provided that the following conditions … … 56 59 * The receive descriptor ring must be aligned to a 4K boundary, 57 60 * and there must be an even multiple of 8 descriptors in the ring. 58 61 */ 59 typedef struct wiseman_rxdesc {62 typedef volatile struct wiseman_rxdesc { 60 63 wiseman_addr_t wrx_addr; /* buffer address */ 61 64 62 65 uint16_t wrx_len; /* buffer length */ … … 103 106 uint8_t wtxu_options; /* options */ 104 107 uint16_t wtxu_vlan; /* VLAN info */ 105 108 } __attribute__((__packed__)) wiseman_txfields_t; 106 typedef struct wiseman_txdesc {109 typedef volatile struct wiseman_txdesc { 107 110 wiseman_addr_t wtx_addr; /* buffer address */ 108 111 uint32_t wtx_cmdlen; /* command and length */ 109 112 wiseman_txfields_t wtx_fields; /* fields; see below */ -
network/if_1GHz/pci_map.c
diff -Naur mvme5500.orig/network/if_1GHz/pci_map.c mvme5500/network/if_1GHz/pci_map.c
old new 3 3 /*- 4 4 * Copyright (c) 2004, 2005 Brookhaven National Laboratory 5 5 * S. Kate Feng <feng1@bnl.gov> 6 * under the Deaprtment of Energy contract DE-AC02-98CH10886 6 7 * 7 8 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 8 9 * All rights reserved. -
network/if_1GHz/pcireg.h
diff -Naur mvme5500.orig/network/if_1GHz/pcireg.h mvme5500/network/if_1GHz/pcireg.h
old new 4 4 * Copyright (c) 1995, 1996, 1999, 2000 5 5 * Christopher G. Demetriou. All rights reserved. 6 6 * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved. 7 * Copyright (C) 2007 Brookhaven National Laboratory, Shuchen Kate Feng 7 8 * 8 9 * Redistribution and use in source and binary forms, with or without 9 10 * modification, are permitted provided that the following conditions … … 30 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 33 */ 34 #include <bsp.h> 33 35 34 36 /* 35 37 * PCI Class and Revision Register; defines type and revision of device. … … 305 307 #define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL 306 308 307 309 #define PCI_MAPREG_IO_ADDR(mr) \ 308 ((mr ) & PCI_MAPREG_IO_ADDR_MASK)310 ((mr+PCI0_IO_BASE) & PCI_MAPREG_IO_ADDR_MASK) 309 311 #define PCI_MAPREG_IO_SIZE(mr) \ 310 312 (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) 311 313 #define PCI_MAPREG_IO_ADDR_MASK 0xfffffffc -
network/if_1GHz/POSSIBLEBUG
diff -Naur mvme5500.orig/network/if_1GHz/POSSIBLEBUG mvme5500/network/if_1GHz/POSSIBLEBUG
old new 1 S. Kate Feng <feng1@bnl.gov>, Sept. 06, 20072 3 This driver boots smoothly with the 1GHZ media.4 It might not boot with the 10/100MHZ media. -
pci/CVS/Entries
diff -Naur mvme5500.orig/pci/CVS/Entries mvme5500/pci/CVS/Entries
old new 1 /detect_host_bridge.c/1.2/Thu May 12 18:25:29 2005// 2 /gtpcireg.h/1.2/Thu May 12 18:25:29 2005// 3 /pci.c/1.7/Thu May 12 18:25:29 2005// 4 /pci.h/1.6/Thu May 12 18:25:29 2005// 5 /pci_interface.c/1.2/Thu May 12 18:25:29 2005// 6 /pcifinddevice.c/1.3/Thu May 12 18:25:29 2005// 7 D -
pci/CVS/Repository
diff -Naur mvme5500.orig/pci/CVS/Repository mvme5500/pci/CVS/Repository
old new 1 rtems/c/src/lib/libbsp/powerpc/mvme5500/pci -
pci/CVS/Root
diff -Naur mvme5500.orig/pci/CVS/Root mvme5500/pci/CVS/Root
old new 1 :pserver:anoncvs@www.rtems.com:/usr1/CVS -
pci/detect_host_bridge.c
diff -Naur mvme5500.orig/pci/detect_host_bridge.c mvme5500/pci/detect_host_bridge.c
old new 6 6 * Copyright (C) 2001, 2003 Till Straumann <strauman@slac.stanford.edu> 7 7 * 8 8 * Copyright (C) 2004 S. Kate Feng, <feng1@bnl.gov> 9 * wrote it to support the MVME5500 board. 9 * wrote it to support the MVME5500 board, 10 * under the Deaprtment of Energy contract DE-AC02-98CH10886. 10 11 * 11 12 */ 12 13 #include <libcpu/io.h> … … 23 24 24 25 #define PCI_INVALID_VENDORDEVICEID 0xffffffff 25 26 #define PCI_MULTI_FUNCTION 0x80 26 #define HOSTBRIDGET_ERROR 0xf000000027 27 28 28 unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet) 29 29 { 30 unsigned int pcidata, pcidata1; 31 int PciLocal, busNumber=0; 30 unsigned long pcidata=0; 31 unsigned short val; 32 int PciLocal, busNumber=0, loop; 32 33 33 34 /* On the mvme5500 board, the GT64260B system controller had the MCP 34 35 * signal pulled up high. Thus, the MCP signal is not used as it is 35 36 * on other boards such as mvme2307. 36 37 */ 37 38 if (enableMCP) return(-1); 38 for (PciLocal=0; PciLocal<1; PciLocal++ ) { 39 pci_read_config_dword(busNumber, 40 0, 41 0, 42 PCI_COMMAND, 43 &pcidata); 44 45 if (!quiet) 46 printk("Before _BSP_clear_hostbridge_errors(): 0x%x, cause 0x%x\n", 47 pcidata, inl(0x1d58)); 48 49 outl(0,0x1d58); 50 51 /* Clear the error on the host bridge */ 52 pcidata1= pcidata; 53 pcidata1 |= PCI_STATUS_CLRERR_MASK; 54 pcidata1 |= 0x140; 55 pci_write_config_dword(busNumber, 39 for (PciLocal=0; PciLocal<2; PciLocal++ ) { 40 pci_read_config_word(busNumber, 41 0, 42 0, 43 PCI_STATUS, 44 &val); 45 if ( (val & PCI_STATUS_CLRERR_MASK) && (!quiet)) 46 printk("Before _BSP_clear_hostbridge_errors(): PCI %d sts was 0x%x\n", 47 PciLocal, val); 48 if (!busNumber) 49 pcidata |= val; 50 else 51 pcidata |= (val <<16); 52 53 for ( loop=0; loop < 10; loop++) { 54 /* Clear the error on the host bridge */ 55 pci_write_config_word(busNumber, 56 56 0, 57 57 0, 58 PCI_ COMMAND,59 pcidata1);58 PCI_STATUS, 59 PCI_STATUS_CLRERR_MASK); 60 60 61 pci_read_config_dword(busNumber,61 pci_read_config_word(busNumber, 62 62 0, 63 63 0, 64 PCI_COMMAND, 65 &pcidata1); 66 67 if (!quiet) printk("After _BSP_clear_hostbridge_errors(): sts 0x%x\n", 68 pcidata1); 69 if (pcidata1 & HOSTBRIDGET_ERROR) printk("BSP_clear_hostbridge_errors(): unable to clear pending hostbridge errors\n"); 70 busNumber += BSP_MAX_PCI_BUS_ON_PCI0; 64 PCI_STATUS, 65 &val); 66 if ( !(val & PCI_STATUS_CLRERR_MASK)) 67 break; 68 else { 69 if (loop==9) 70 printk("BSP_clear_hostbridge_errors(): unable to clear pending hostbridge errors\n"); 71 } 72 } 73 busNumber += BSP_MAX_PCI_BUS_ON_PCI0; 71 74 } 72 return(pcidata & HOSTBRIDGET_ERROR);75 return(pcidata); 73 76 } -
pci/gtpcireg.h
diff -Naur mvme5500.orig/pci/gtpcireg.h mvme5500/pci/gtpcireg.h
old new 46 46 47 47 #define PCI_IO_BASE_ADDR PCI_BASE_ADDRESS_5 48 48 49 #define PCI_STATUS_CLRERR_MASK 0xf900 0000/* <SKF> */49 #define PCI_STATUS_CLRERR_MASK 0xf900 /* <SKF> */ 50 50 51 51 #define PCI_BARE_IntMemEn 0x200 52 52 -
pci/pci.c
diff -Naur mvme5500.orig/pci/pci.c mvme5500/pci/pci.c
old new 16 16 * pci.c,v 1.2 2002/05/14 17:10:16 joel Exp 17 17 * 18 18 * Copyright 2004, Brookhaven National Laboratory and 19 * Shuchen K. Feng, <feng1@bnl.gov>, 2004 20 * - modified and added support for MVME5500 board21 * - added 2nd PCI support for the mvme5500/GT64260 PCI bridge22 * - added bus support for the expansion of PMCSpan, thanks to23 * Peter Dufault (dufault@hda.com) for inputs.19 * Shuchen K. Feng, <feng1@bnl.gov>, 2004, 2008 20 * 21 * - to be consistent with the original pci.c written by Eric Valette 22 * - added 2nd PCI support for discovery based PCI bridge (e.g. mvme5500/mvme6100) 23 * - added bus support for the expansion of PMCSpan as per request by Peter 24 24 */ 25 25 #define PCI_MAIN 26 26 27 27 #include <libcpu/io.h> 28 28 #include <rtems/bspIo.h> /* printk */ 29 29 30 #include <bsp/irq.h> 30 31 #include <bsp/pci.h> 31 32 #include <bsp/gtreg.h> 32 33 #include <bsp/gtpcireg.h> 34 #include <bsp.h> 33 35 34 36 #include <stdio.h> 35 37 #include <string.h> 36 38 37 39 #define PCI_DEBUG 0 38 #define PCI_PRINT 040 #define PCI_PRINT 1 39 41 40 42 /* allow for overriding these definitions */ 41 43 #ifndef PCI_CONFIG_ADDR … … 56 58 #define PCI_MULTI_FUNCTION 0x80 57 59 #define HOSTBRIDGET_ERROR 0xf0000000 58 60 59 /* define a shortcut */ 60 #define pci BSP_pci_configuration 61 #define GT64x60_PCI_CONFIG_ADDR GT64x60_REG_BASE + PCI_CONFIG_ADDR 62 #define GT64x60_PCI_CONFIG_DATA GT64x60_REG_BASE + PCI_CONFIG_DATA 63 64 #define GT64x60_PCI1_CONFIG_ADDR GT64x60_REG_BASE + PCI1_CONFIG_ADDR 65 #define GT64x60_PCI1_CONFIG_DATA GT64x60_REG_BASE + PCI1_CONFIG_DATA 66 67 static int numPCIDevs=0; 68 static DiscoveryChipVersion BSP_sysControllerVersion = 0; 69 static BSP_VMEchipTypes BSP_VMEinterface = 0; 70 static pci_config BSP_pci[2]={ 71 {(volatile unsigned char*) (GT64x60_PCI_CONFIG_ADDR), 72 (volatile unsigned char*) (GT64x60_PCI_CONFIG_DATA), 73 0 /* defined at BSP_pci_configuration */}, 74 {(volatile unsigned char*) (GT64x60_PCI1_CONFIG_ADDR), 75 (volatile unsigned char*) (GT64x60_PCI1_CONFIG_DATA), 76 0 /* defined at BSP_pci_configuration */} 77 }; 61 78 62 static int numPCIDevs=0;63 79 extern void pci_interface(); 64 80 65 81 /* Pack RegNum,FuncNum,DevNum,BusNum,and ConfigEnable for 66 82 * PCI Configuration Address Register 67 83 */ 68 84 #define pciConfigPack(bus,dev,func,offset)\ 69 (( (func&7)<<8)|((dev&0x1f )<<11)|(( bus&0xff)<<16)|(offset&0xfc))|0x8000000085 ((offset&~3)<<24)|(PCI_DEVFN(dev,func)<<16)|(bus<<8)|0x80 70 86 71 87 /* 72 88 * Bit encode for PCI_CONFIG_HEADER_TYPE register … … 75 91 76 92 /* Please note that PCI0 and PCI1 does not correlate with the busNum 0 and 1. 77 93 */ 78 static int direct_pci_read_config_byte(unsigned char bus,unsigned char dev,unsigned char func,94 static int indirect_pci_read_config_byte(unsigned char bus,unsigned char dev,unsigned char func, 79 95 unsigned char offset,unsigned char *val) 80 96 { 81 volatile unsigned char *config_addr, *config_data;97 int n=0; 82 98 83 99 if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { 84 100 bus-=BSP_MAX_PCI_BUS_ON_PCI0; 85 config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR; 86 config_data = (volatile unsigned char*) PCI1_CONFIG_DATA; 87 } 88 else { 89 config_addr = pci.pci_config_addr; 90 config_data = pci.pci_config_data; 101 n=1; 91 102 } 103 92 104 *val = 0xff; 93 105 if (offset & ~0xff) return PCIBIOS_BAD_REGISTER_NUMBER; 94 106 #if 0 95 printk("addr %x, data %x, pack %x \n", config_addr,96 config_data,pciConfigPack(bus,dev,func,offset));107 printk("addr %x, data %x, pack %x \n", BSP_pci[n].pci_config_addr), 108 BSP_pci[n].config_data,pciConfigPack(bus,dev,func,offset)); 97 109 #endif 98 outl(pciConfigPack(bus,dev,func,offset),config_addr); 99 *val = inb(config_data + (offset&3)); 110 111 out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); 112 *val = in_8(BSP_pci[n].pci_config_data + (offset&3)); 100 113 return PCIBIOS_SUCCESSFUL; 101 114 } 102 115 103 static int direct_pci_read_config_word(unsigned char bus, unsigned char dev,116 static int indirect_pci_read_config_word(unsigned char bus, unsigned char dev, 104 117 unsigned char func, unsigned char offset, unsigned short *val) 105 118 { 106 volatile unsigned char *config_addr, *config_data;119 int n=0; 107 120 108 121 if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { 109 122 bus-=BSP_MAX_PCI_BUS_ON_PCI0; 110 config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR; 111 config_data = (volatile unsigned char*) PCI1_CONFIG_DATA; 112 } 113 else { 114 config_addr = (volatile unsigned char*) pci.pci_config_addr; 115 config_data = (volatile unsigned char*) pci.pci_config_data; 123 n=1; 116 124 } 117 125 118 126 *val = 0xffff; … … 121 129 printk("addr %x, data %x, pack %x \n", config_addr, 122 130 config_data,pciConfigPack(bus,dev,func,offset)); 123 131 #endif 124 out l(pciConfigPack(bus,dev,func,offset),config_addr);125 *val = in w(config_data + (offset&2));132 out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); 133 *val = in_le16(BSP_pci[n].pci_config_data + (offset&2)); 126 134 return PCIBIOS_SUCCESSFUL; 127 135 } 128 136 129 static int direct_pci_read_config_dword(unsigned char bus, unsigned char dev,137 static int indirect_pci_read_config_dword(unsigned char bus, unsigned char dev, 130 138 unsigned char func, unsigned char offset, unsigned int *val) 131 139 { 132 volatile unsigned char *config_addr, *config_data;140 int n=0; 133 141 134 142 if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { 135 143 bus-=BSP_MAX_PCI_BUS_ON_PCI0; 136 config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR; 137 config_data = (volatile unsigned char*) PCI1_CONFIG_DATA; 138 } 139 else { 140 config_addr = (volatile unsigned char*) pci.pci_config_addr; 141 config_data = (volatile unsigned char*) pci.pci_config_data; 144 n=1; 142 145 } 143 146 144 147 *val = 0xffffffff; 145 148 if ((offset&3)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER; 146 #if 0 147 printk("addr %x, data %x, pack %x \n", config_addr, 148 pci.pci_config_data,pciConfigPack(bus,dev,func,offset)); 149 #endif 150 outl(pciConfigPack(bus,dev,func,offset),config_addr); 151 *val = inl(config_data); 149 150 out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); 151 *val = in_le32(BSP_pci[n].pci_config_data); 152 152 return PCIBIOS_SUCCESSFUL; 153 153 } 154 154 155 static int direct_pci_write_config_byte(unsigned char bus, unsigned char dev,unsigned char func, unsigned char offset, unsigned char val)155 static int indirect_pci_write_config_byte(unsigned char bus, unsigned char dev,unsigned char func, unsigned char offset, unsigned char val) 156 156 { 157 volatile unsigned char *config_addr, *config_data;157 int n=0; 158 158 159 159 if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { 160 160 bus-=BSP_MAX_PCI_BUS_ON_PCI0; 161 config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR; 162 config_data = (volatile unsigned char*) PCI1_CONFIG_DATA; 163 } 164 else { 165 config_addr = pci.pci_config_addr; 166 config_data = pci.pci_config_data; 161 n=1; 167 162 } 168 163 169 164 if (offset & ~0xff) return PCIBIOS_BAD_REGISTER_NUMBER; 170 #if 0171 printk("addr %x, data %x, pack %x \n", config_addr,172 config_data,pciConfigPack(bus,dev,func,offset));173 #endif174 165 175 out l(pciConfigPack(bus,dev,func,offset), config_addr);176 out b(val, config_data + (offset&3));166 out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); 167 out_8(BSP_pci[n].pci_config_data + (offset&3), val); 177 168 return PCIBIOS_SUCCESSFUL; 178 169 } 179 170 180 static int direct_pci_write_config_word(unsigned char bus, unsigned char dev,unsigned char func, unsigned char offset, unsigned short val)171 static int indirect_pci_write_config_word(unsigned char bus, unsigned char dev,unsigned char func, unsigned char offset, unsigned short val) 181 172 { 182 volatile unsigned char *config_addr, *config_data;173 int n=0; 183 174 184 175 if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { 185 176 bus-=BSP_MAX_PCI_BUS_ON_PCI0; 186 config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR; 187 config_data = (volatile unsigned char*) PCI1_CONFIG_DATA; 188 } 189 else { 190 config_addr = (volatile unsigned char*) pci.pci_config_addr; 191 config_data = (volatile unsigned char*) pci.pci_config_data; 177 n=1; 192 178 } 193 179 194 180 if ((offset&1)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER; 195 #if 0 196 printk("addr %x, data %x, pack %x \n", config_addr, 197 config_data,pciConfigPack(bus,dev,func,offset)); 198 #endif 199 outl(pciConfigPack(bus,dev,func,offset),config_addr); 200 outw(val, config_data + (offset&3)); 181 182 out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); 183 out_le16(BSP_pci[n].pci_config_data + (offset&3), val); 201 184 return PCIBIOS_SUCCESSFUL; 202 185 } 203 186 204 static int direct_pci_write_config_dword(unsigned char bus,unsigned char dev,unsigned char func, unsigned char offset, unsigned int val)187 static int indirect_pci_write_config_dword(unsigned char bus,unsigned char dev,unsigned char func, unsigned char offset, unsigned int val) 205 188 { 206 volatile unsigned char *config_addr, *config_data;189 int n=0; 207 190 208 191 if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) { 209 192 bus-=BSP_MAX_PCI_BUS_ON_PCI0; 210 config_addr = (volatile unsigned char *) PCI1_CONFIG_ADDR; 211 config_data = (volatile unsigned char *) PCI1_CONFIG_DATA; 212 } 213 else { 214 config_addr = (volatile unsigned char*) pci.pci_config_addr; 215 config_data = (volatile unsigned char*) pci.pci_config_data; 193 n=1; 216 194 } 217 195 218 196 if ((offset&3)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER; 219 #if 0 220 printk("addr %x, data %x, pack %x \n", config_addr, 221 config_data,pciConfigPack(bus,dev,func,offset)); 222 #endif 223 outl(pciConfigPack(bus,dev,func,offset),config_addr); 224 outl(val,config_data); 197 198 out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset)); 199 out_le32(BSP_pci[n].pci_config_data, val); 225 200 return PCIBIOS_SUCCESSFUL; 226 201 } 227 202 228 const pci_config_access_functions pci_ direct_functions = {229 direct_pci_read_config_byte,230 direct_pci_read_config_word,231 direct_pci_read_config_dword,232 direct_pci_write_config_byte,233 direct_pci_write_config_word,234 direct_pci_write_config_dword203 const pci_config_access_functions pci_indirect_functions = { 204 indirect_pci_read_config_byte, 205 indirect_pci_read_config_word, 206 indirect_pci_read_config_dword, 207 indirect_pci_write_config_byte, 208 indirect_pci_write_config_word, 209 indirect_pci_write_config_dword 235 210 }; 236 211 237 212 238 pci_config BSP_pci_configuration = {(volatile unsigned char*) PCI_CONFIG_ADDR, 239 (volatile unsigned char*)PCI_CONFIG_DATA, 240 &pci_direct_functions}; 213 pci_config BSP_pci_configuration = { 214 (volatile unsigned char*) (GT64x60_PCI_CONFIG_ADDR), 215 (volatile unsigned char*) (GT64x60_PCI_CONFIG_DATA), 216 &pci_indirect_functions}; 217 218 DiscoveryChipVersion BSP_getDiscoveryChipVersion() 219 { 220 return(BSP_sysControllerVersion); 221 } 222 223 BSP_VMEchipTypes BSP_getVMEchipType() 224 { 225 return(BSP_VMEinterface); 226 } 241 227 242 228 /* 243 229 * This routine determines the maximum bus number in the system. … … 248 234 int pci_initialize() 249 235 { 250 236 int deviceFound; 251 unsigned char ucBusNumber, ucSlotNumber, ucFnNumber, ucNumFuncs; 252 unsigned int ulHeader; 253 unsigned int pcidata, ulClass, ulDeviceID; 237 unsigned char ucBusNumber, ucSlotNumber, ucFnNumber, ucNumFuncs, data8; 238 uint32_t ulHeader, ulClass, ulDeviceID; 239 #if PCI_DEBUG 240 uint32_t pcidata; 241 #endif 254 242 255 pci_interface();256 257 243 /* 258 244 * Scan PCI0 and PCI1 buses 259 245 */ … … 279 265 if (!deviceFound) deviceFound=1; 280 266 switch(ulDeviceID) { 281 267 case (PCI_VENDOR_ID_MARVELL+(PCI_DEVICE_ID_MARVELL_GT6426xAB<<16)): 268 pci_read_config_byte(0,0,0,PCI_REVISION_ID, &data8); 269 switch(data8) { 270 case 0x10: 271 BSP_sysControllerVersion = GT64260A; 272 #if PCI_PRINT 273 printk("Marvell GT64260A (Discovery I) hostbridge detected at bus%d slot%d\n", 274 ucBusNumber,ucSlotNumber); 275 #endif 276 break; 277 case 0x20: 278 BSP_sysControllerVersion = GT64260B; 279 #if PCI_PRINT 280 printk("Marvell GT64260B (Discovery I) hostbridge detected at bus%d slot%d\n", 281 ucBusNumber,ucSlotNumber); 282 #endif 283 break; 284 default: 285 printk("Undefined revsion of GT64260 chip\n"); 286 break; 287 } 288 break; 289 case (PCI_VENDOR_ID_MARVELL+(PCI_DEVICE_ID_MARVELL_GT64360<<16)): 290 BSP_sysControllerVersion = MV64360; 282 291 #if PCI_PRINT 283 printk("Marvell GT64 26xA/Bhostbridge detected at bus%d slot%d\n",292 printk("Marvell GT64360 (Discovery II) hostbridge detected at bus%d slot%d\n", 284 293 ucBusNumber,ucSlotNumber); 285 294 #endif 286 295 break; 287 296 case (PCI_VENDOR_ID_PLX2+(PCI_DEVICE_ID_PLX2_PCI6154_HB2<<16)): 297 BSP_VMEinterface = UNIVERSE2; 288 298 #if PCI_PRINT 289 299 printk("PLX PCI6154 PCI-PCI bridge detected at bus%d slot%d\n", 290 300 ucBusNumber,ucSlotNumber); … … 296 306 ucBusNumber,ucSlotNumber); 297 307 #endif 298 308 break; 309 case (PCI_VENDOR_ID_TUNDRA+(PCI_DEVICE_ID_TUNDRA_TSI148<<16)): 310 BSP_VMEinterface = TSI148; 311 #if PCI_PRINT 312 printk("TUNDRA Tsi148 PCI/X-VME bridge detected at bus%d slot%d\n", 313 ucBusNumber,ucSlotNumber); 314 #endif 315 break; 299 316 case (PCI_VENDOR_ID_INTEL+(PCI_DEVICE_INTEL_82544EI_COPPER<<16)): 300 317 #if PCI_PRINT 301 318 printk("INTEL 82544EI COPPER network controller detected at bus%d slot%d\n", … … 303 320 #endif 304 321 break; 305 322 case (PCI_VENDOR_ID_DEC+(PCI_DEVICE_ID_DEC_21150<<16)): 306 323 #if PCI_PRINT 307 324 printk("DEC21150 PCI-PCI bridge detected at bus%d slot%d\n", 308 325 ucBusNumber,ucSlotNumber); 309 326 #endif 310 327 break; 311 328 default : 329 #if PCI_PRINT 312 330 printk("BSP unlisted vendor, Bus%d Slot%d DeviceID 0x%x \n", 313 331 ucBusNumber,ucSlotNumber, ulDeviceID); 332 #endif 333 /* Kate Feng : device not supported by BSP needs to remap the IRQ line on mvme5500/mvme6100 */ 334 pci_read_config_byte(ucBusNumber,ucSlotNumber,0,PCI_INTERRUPT_LINE,&data8); 335 if (data8 < BSP_GPP_IRQ_LOWEST_OFFSET) pci_write_config_byte(ucBusNumber, 336 ucSlotNumber,0,PCI_INTERRUPT_LINE,BSP_GPP_IRQ_LOWEST_OFFSET+data8); 337 314 338 break; 315 339 } 316 340 … … 403 427 #endif 404 428 405 429 } 406 407 pci_read_config_dword(ucBusNumber,408 ucSlotNumber,409 0,410 PCI_COMMAND,411 &pcidata);412 #if PCI_DEBUG413 printk("MOTLoad command staus 0x%x, ", pcidata);414 #endif415 /* Clear the error on the host bridge */416 if ( (ucBusNumber==0) && (ucSlotNumber==0))417 pcidata |= PCI_STATUS_CLRERR_MASK;418 /* Enable bus,I/O and memory master access. */419 pcidata |= (PCI_COMMAND_MASTER|PCI_COMMAND_IO|PCI_COMMAND_MEMORY);420 pci_write_config_dword(ucBusNumber,421 ucSlotNumber,422 0,423 PCI_COMMAND,424 pcidata);425 426 pci_read_config_dword(ucBusNumber,427 ucSlotNumber,428 0,429 PCI_COMMAND,430 &pcidata);431 #if PCI_DEBUG432 printk("Now command/staus 0x%x\n", pcidata);433 #endif434 430 } 435 431 if (deviceFound) ucMaxPCIBus++; 436 432 } /* for (ucBusNumber=0; ucBusNumber<BSP_MAX_PCI_BUS; ... */ … … 438 434 printk("number of PCI buses: %d, numPCIDevs %d\n", 439 435 pci_bus_count(), numPCIDevs); 440 436 #endif 437 pci_interface(BSP_sysControllerVersion); 441 438 return(0); 442 439 } 443 440 -
pci/pcifinddevice.c
diff -Naur mvme5500.orig/pci/pcifinddevice.c mvme5500/pci/pcifinddevice.c
old new 7 7 * 8 8 * 9 9 * Kate Feng <feng1@bnl.gov>, modified it to support the mvme5500 board. 10 * 10 * Under the Deaprtment of Energy contract DE-AC02-98CH10886. 11 11 */ 12 12 13 13 #define PCI_INVALID_VENDORDEVICEID 0xffffffff -
pci/pci.h
diff -Naur mvme5500.orig/pci/pci.h mvme5500/pci/pci.h
old new 14 14 * 15 15 * pci.h,v 1.2 2002/05/14 17:10:16 joel Exp 16 16 * 17 * S. Kate Feng : Added support for Marvell and PLX. 3/5/2004. 18 17 * S. Kate Feng : Added support for Marvell and PLX. 2004, 2007. 19 18 */ 20 19 21 20 #ifndef RTEMS_PCI_H … … 23 22 24 23 #include <rtems/pci.h> 25 24 26 #define PCI_CAPABILITY_LIST_POINTER 0x34 /* <SKF> */ 25 /************ Beginning of added by Kate Feng **********************/ 26 #define PCI_CAPABILITY_LIST_POINTER 0x34 27 27 28 28 /* Device classes and subclasses */ 29 #define PCI_CLASS_GT6426xAB_BRIDGE_PCI 0x0580 /* <SKF> */29 #define PCI_CLASS_GT6426xAB_BRIDGE_PCI 0x0580 30 30 31 31 /* 32 32 * Vendor and card ID's: sort these numerically according to vendor 33 33 * (and according to card ID within vendor). Send all updates to 34 34 * <linux-pcisupport@cck.uni-kl.de>. 35 35 */ 36 #define PCI_VENDOR_ID_MARVELL 0x11ab /* <SKF> */ 37 #define PCI_DEVICE_ID_MARVELL_GT6426xAB 0x6430 /* <SKF> */ 36 #define PCI_VENDOR_ID_MARVELL 0x11ab 37 #define PCI_DEVICE_ID_MARVELL_GT6426xAB 0x6430 38 #define PCI_DEVICE_ID_MARVELL_GT64360 0x6460 38 39 39 40 /* Note : The PLX Technology Inc. had the old VENDOR_ID. 40 41 * See PCI_VENDOR_ID_PLX, PCI_VENDOR_ID_PLX_9050, ..etc. 41 42 */ 42 #define PCI_VENDOR_ID_PLX2 0x3388 /* <SKF> */ 43 #define PCI_DEVICE_ID_PLX2_PCI6154_HB2 0x26 /* <SKF> */ 43 #define PCI_VENDOR_ID_PLX2 0x3388 44 #define PCI_DEVICE_ID_PLX2_PCI6154_HB2 0x26 45 46 #define PCI_DEVICE_ID_TUNDRA_TSI148 0x0148 47 #define PCI_DEVICE_INTEL_82544EI_COPPER 0x1008 44 48 45 #define PCI_DEVICE_INTEL_82544EI_COPPER 0x1008 /* <SKF>*/49 /* end of added by Kate Feng */ 46 50 47 51 struct _pin_routes 48 52 { -
pci/pci_interface.c
diff -Naur mvme5500.orig/pci/pci_interface.c mvme5500/pci/pci_interface.c
old new 7 7 * found in the file LICENSE in this distribution. 8 8 * 9 9 * 8/17/2006 : S. Kate Feng 10 * uses in_le32()/out_le32(), instead of inl()/outl() so that 11 * it is easier to be ported. 10 * uses in_le32()/out_le32(), instead of inl()/outl() for compatibility. 12 11 * 12 * 11/2008 : Enable "PCI Read Agressive Prefetch", 13 * "PCI Read Line Agressive Prefetch", and 14 * "PCI Read Multiple Agressive Prefetch" to improve the 15 * performance of the PCI based applications (e.g. 1GHz NIC). 13 16 */ 17 14 18 #include <libcpu/io.h> 15 19 #include <rtems/bspIo.h> /* printk */ 16 20 … … 19 23 #include <bsp/gtreg.h> 20 24 #include <bsp/gtpcireg.h> 21 25 22 #define REG32_READ(reg) in_le32((volatile unsigned int *)(GT64260_REG_BASE+reg))23 #define REG32_WRITE(data, reg) out_le32((volatile unsigned int *)(GT64260_REG_BASE+reg), data)24 25 26 #define PCI_DEBUG 0 26 27 27 /* Please reference the GT64260B datasheet, for the PCI interface, 28 * Synchronization Barriers and PCI ordering. 29 * 30 * Some PCI devices require Synchronization Barriers or PCI ordering 31 * for synchronization (only one mechanism allowed. See section 11.1.2). 32 * To use the former mechanism(default), one needs to call 33 * CPU0_PciEnhanceSync() or CPU1_PciEnhanceSync() to perform software 34 * synchronization between the CPU and PCI activities. 35 * 36 * To use the PCI-ordering, one can call pciToCpuSync() to trigger 37 * the PCI-to-CPU sync barrier after the out_xx(). In this mode, 38 * PCI configuration reads suffer sync barrier latency. Please reference 39 * the datasheet to explore other options. 40 * 41 * Note : If PCI_ORDERING is needed for the PCI0, while disabling the 42 * deadlock for the PCI0, one should keep the CommDLEn bit enabled 43 * for the deadlock mechanism so that the 10/100 MB ethernet will 44 * function correctly. 45 * 46 */ 47 /*#define PCI_ORDERING*/ 48 49 #define EN_SYN_BAR /* take MOTLoad default for enhanced SYN Barrier mode */ 50 51 /*#define PCI_DEADLOCK*/ 28 #if 0 29 #define CPU2PCI_ORDER 30 #define PCI2CPU_ORDER 31 #endif 52 32 53 #ifdef PCI_ORDERING 54 #define PCI_ACCCTLBASEL_VALUE 0x01009000 33 /* PCI Read Agressive Prefetch Enable (1<<16 ), 34 * PCI Read Line Agressive Prefetch Enable( 1<<17), 35 * PCI Read Multiple Agressive Prefetch Enable (1<<18). 36 */ 37 #ifdef PCI2CPU_ORDER 38 #define PCI_ACCCTLBASEL_VALUE 0x01079000 55 39 #else 56 #define PCI_ACCCTLBASEL_VALUE 0x010 0100040 #define PCI_ACCCTLBASEL_VALUE 0x01071000 57 41 #endif 58 42 43 59 44 #define ConfSBDis 0x10000000 /* 1: disable, 0: enable */ 60 45 #define IOSBDis 0x20000000 /* 1: disable, 0: enable */ 61 46 #define ConfIOSBDis 0x30000000 62 47 #define CpuPipeline 0x00002000 /* optional, 1:enable, 0:disable */ 63 48 64 #define CPU0_SYNC_TRIGGER 0xD0 /* CPU0 Sync Barrier trigger */65 #define CPU0_SYNC_VIRTUAL 0xC0 /* CPU0 Sync Barrier Virtual */66 67 #define CPU1_SYNC_TRIGGER 0xD8 /* CPU1 Sync Barrier trigger */68 #define CPU1_SYNC_VIRTUAL 0xC8 /* CPU1 Sync Barrier Virtual */69 70 71 49 /* CPU to PCI ordering register */ 72 50 #define DLOCK_ORDER_REG 0x2D0 /* Deadlock and Ordering register */ 73 51 #define PCI0OrEn 0x00000001 … … 86 64 87 65 #define ADDR_PIPELINE 0x00020000 88 66 89 void pciAccessInit( );67 void pciAccessInit(void); 90 68 91 void pci_interface( )69 void pci_interface(void) 92 70 { 93 71 94 #ifdef PCI_DEADLOCK 95 REG32_WRITE(0x07fff600, CNT_SYNC_REG); 72 #ifdef CPU2PCI_ORDER 73 /* MOTLOad deafult : 0x07ff8600 */ 74 out_le32((volatile unsigned int *)(GT64x60_REG_BASE+CNT_SYNC_REG), 0x07fff600); 96 75 #endif 97 #ifdef PCI_ORDERING 98 /* Let's leave this to be MOTLOad deafult : 0x80070000 99 REG32_WRITE(0xc0070000, DLOCK_ORDER_REG);*/ 100 /* Leave the CNT_SYNC_REG b/c MOTload default had the SyncBarMode set to 1 */ 101 #endif 102 103 /* asserts SERR upon various detection */ 104 REG32_WRITE(0x3fffff, 0xc28); 105 106 pciAccessInit(); 76 /* asserts SERR upon various detection */ 77 out_le32((volatile unsigned int *)(GT64x60_REG_BASE+0xc28), 0x3fffff); 78 pciAccessInit(); 107 79 } 108 /* Use MOTLoad default for Writeback Priority and Buffer Depth 109 */ 110 void pciAccessInit() 80 81 void pciAccessInit(void) 111 82 { 112 83 unsigned int PciLocal, data; 113 84 114 85 for (PciLocal=0; PciLocal < 2; PciLocal++) { 115 /* MOTLoad combines the two banks of SDRAM into116 * one PCI access control because the top = 0x1ff 117 */118 data = REG32_READ(GT_SCS0_Low_Decode) & 0xfff;86 data = in_le32((volatile unsigned int *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80))); 87 #if 0 88 printk("PCI%d_ACCESS_CNTL_BASE0_LOW was 0x%x\n",PciLocal,data); 89 #endif 119 90 data |= PCI_ACCCTLBASEL_VALUE; 120 91 data &= ~0x300000; 121 REG32_WRITE(data, PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80));122 #if PCI_DEBUG123 printk("PCI%d_ACCESS_CNTL_BASE0_LOW 0x%x\n",PciLocal,REG32_READ(PCI_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)));92 out_le32((volatile unsigned int *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)), data); 93 #if 0 94 printf("PCI%d_ACCESS_CNTL_BASE0_LOW now 0x%x\n",PciLocal,in_le32((volatile unsigned int *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)))); 124 95 #endif 125 126 96 } 127 97 } 128 98 129 /* Sync Barrier Trigger. A write to the CPU_SYNC_TRIGGER register triggers130 * the sync barrier process. The three bits, define which buffers should131 * be flushed.132 * Bit 0 = PCI0 slave write buffer.133 * Bit 1 = PCI1 slave write buffer.134 * Bit 2 = SDRAM snoop queue.135 */136 void CPU0_PciEnhanceSync(unsigned int syncVal)137 {138 REG32_WRITE(syncVal,CPU0_SYNC_TRIGGER);139 while (REG32_READ(CPU0_SYNC_VIRTUAL));140 }141 142 void CPU1_PciEnhanceSync(unsigned int syncVal)143 {144 REG32_WRITE(syncVal,CPU1_SYNC_TRIGGER);145 while (REG32_READ(CPU1_SYNC_VIRTUAL));146 }147 148 /* Currently, if PCI_ordering is used for synchronization, configuration149 * reads is programmed to be the PCI slave "synchronization barrier"150 * cycles.151 */152 void pciToCpuSync(int pci_num)153 {154 unsigned char data;155 unsigned char bus=0;156 157 if (pci_num) bus += BSP_MAX_PCI_BUS_ON_PCI0;158 pci_read_config_byte(bus,0,0,4, &data);159 } -
mvme5500
diff -Naur mvme5500.orig/README mvme5500/README
old new 1 1 # 2 # $Id: README,v 1. 3.1 Shuchen Kate Feng, NSLS, BNL (08/27/07)2 # $Id: README,v 1.4.1 Shuchen Kate Feng, NSLS, BNL (03/16/2009) 3 3 # 4 4 5 5 Please reference README.booting for the boot/load process. … … 7 7 For the priority setting of the Interrupt Requests (IRQs), please 8 8 reference README.irq 9 9 10 The BSP is built and tested on the 4. 7.1 and 4.7.99.2 CVSRTEMS release.10 The BSP is built and tested on the 4.8.0 RTEMS release. 11 11 12 12 I believe in valuable real-time programming, where technical neatness, 13 13 performance and truth are. I hope I still believe. Any suggestion, -
README.booting
diff -Naur mvme5500.orig/README.booting mvme5500/README.booting
old new 1 README.booting: written by S. Kate Feng <feng1@bnl.gov>, Aug. 28, 20071 README.booting: written by S. Kate Feng <feng1@bnl.gov>, March 16, 2009 2 2 3 The bootloader is adapted from Till Straumann's Generic Mini-loader, 4 which he wrote originally for the SVGM powerpc board. 5 The BSP is built and tested on the 4.7 CVS RTEMS release. 3 The BSP is built and tested on the RTEMS 4.8.0 release. 6 4 7 5 Booting requirement : 8 6 ------------------------- … … 11 9 or /etc/dhcpd.conf (DHCP) properly to boot the system. 12 10 (Note : EPICS needs a NTP server). 13 11 14 2) Please copy the prebuilt RTEMS binary (e.g. misc/rtems5500-cexp.bin) 15 and perhaps others (e.g. misc/st.sys) to the /tftpboot/epics/hostname/bin/ 16 directory or the TFTPBOOT one you specified in the 'tftpGet' 17 command of the boot script (as shown in the following example). 18 19 3) Example of the boot script setup carried out on the MOTLoad 12 2) Example of the boot script setup carried out on the MOTLoad 20 13 command line : 21 14 22 15 MVME5500> gevEdit mot-script-boot … … 32 25 Note : (cxx.xx.xx.xx is the client IP address and 33 26 sxx.xx.xx.xx is the server IP address) 34 27 35 4) Other reference web sites for mvme5500 BSP: 36 http://lansce.lanl.gov/EPICS/presentations/KateFeng%20RTEMS-mvme55001.ppt 28 3) Other reference web sites for mvme5500 BSP: 37 29 http://www.nsls.bnl.gov/facility/expsys/software/EPICS/ 38 http://www.nsls.bnl.gov/facility/expsys/software/EPICS/FAQ.txt39 30 40 5) When generating code (especially C++) for this system, one should41 use at least gcc-3.2 (preferrably a copy downloaded from the RTEMS42 site [snapshot area] )43 31 44 6) To reboot the RTEMS-MVME5500 (board reset), one can invoke the32 4) To reboot the RTEMS-MVME5500 (board reset), one can invoke the 45 33 rtemsReboot() command at Cexp> prompt. 46 34 47 7) Please reference http://www.slac.stanford.edu/~strauman/rtems 48 for the source code and installation guidance of cexp, GeSys and 49 other useful utilities such as telnet, nfs, and so on. 50 51 8) To get started with RTEMS/EPICS and to build development 35 5) To get started with RTEMS/EPICS and to build development 52 36 tools and BSP, I would recommend one to reference 53 37 http://www.aps.anl.gov/epics/base/RTEMS/tutorial/ 54 38 in additional to the RTEMS document. -
startup/bspclean.c
diff -Naur mvme5500.orig/startup/bspclean.c mvme5500/startup/bspclean.c
old new 1 /* Copyright 2003, Shuchen Kate Feng <feng1@bnl.gov>, 2 * NSLS,Brookhaven National Laboratory 3 */ 1 4 #include <bsp.h> 2 5 #include <rtems/bspIo.h> 3 6 #include <libcpu/stackTrace.h> -
startup/bspstart.c
diff -Naur mvme5500.orig/startup/bspstart.c mvme5500/startup/bspstart.c
old new 17 17 * Modified to support the Synergy VGM & Motorola PowerPC boards 18 18 * (C) by Till Straumann, <strauman@slac.stanford.edu>, 2002, 2004, 2005 19 19 * 20 * Modified to support the MVME5500 board. 21 * Also, the settings of L1, L2, and L3 caches is not necessary here. 22 * (C) by Brookhaven National Lab., S. Kate Feng <feng1@bnl.gov>, 2003, 2004, 2005 23 * 20 * Modified to support the mvme5500 BSP 21 * (C) S. Kate Feng,Brookhaven National Lab <feng1@bnl.gov>, 2003, 2004, 2005, 2008 22 * 24 23 * $Id: bspstart.c,v 1.15 2007/09/13 14:26:24 joel Exp $ 25 24 */ 26 25 … … 42 41 #include <libcpu/cpuIdent.h> 43 42 #include <bsp/vectors.h> 44 43 #include <bsp/bspException.h> 44 #include <bsp/VPD.h> 45 45 46 46 #include <rtems/bspIo.h> 47 47 #include <rtems/sptables.h> … … 50 50 #undef __RTEMS_APPLICATION__ 51 51 #endif 52 52 53 /* 54 #define SHOW_MORE_INIT_SETTINGS 53 /*efine SHOW_MORE_INIT_SETTINGS 55 54 #define SHOW_LCR1_REGISTER 56 55 #define SHOW_LCR2_REGISTER 57 56 #define SHOW_LCR3_REGISTER … … 74 73 75 74 SPR_RW(SPRG0) 76 75 SPR_RW(SPRG1) 76 extern uint32_t probeMemoryEnd(); 77 77 78 78 typedef struct CmdLineRec_ { 79 79 unsigned long size; … … 96 96 #define MAX_LOADER_ADD_PARM 80 97 97 char loaderParam[MAX_LOADER_ADD_PARM]; 98 98 99 BSP_BoardTypes BSP_boardType=0; 100 101 DiscoveryChipVersion BSP_controller_version; 102 99 103 /* 100 104 * Total memory using RESIDUAL DATA 101 105 */ … … 222 226 cmdline_buf[i]=0; 223 227 } 224 228 229 BSP_BoardTypes BSP_getBoardType() 230 { 231 return BSP_boardType; 232 } 233 225 234 /* 226 235 * bsp_start 227 236 * … … 233 242 #ifdef CONF_VPD 234 243 int i; 235 244 #endif 245 int x; 236 246 unsigned char *stack; 237 247 unsigned long *r1sp; 238 248 #ifdef SHOW_LCR1_REGISTER … … 250 260 ppc_cpu_id_t myCpu; 251 261 ppc_cpu_revision_t myCpuRevision; 252 262 Triv121PgTbl pt=0; 263 ConfVpdRec_t *pVPD = (ConfVpdRec_t *) &ConfVPD_buff[0]; 264 253 265 254 266 /* Till Straumann: 4/2005 255 267 * Need to map the system registers early, so we can printk... … … 260 272 */ 261 273 setdbat(2, PCI0_MEM_BASE, PCI0_MEM_BASE, 0x10000000, IO_PAGE); 262 274 263 /* Till Straumann: 2004 264 * map the PCI 0, 1 Domain I/O space, GT64260B registers 265 * and the reserved area so that the size is the power of 2. 275 /* map the PCI 0, 1 Domain I/O space, GT64260B registers, 276 * Flash Bank 0 and Flash Bank 2. 266 277 * 267 278 */ 268 setdbat(3,PCI0_IO_BASE, PCI0_IO_BASE, 0x 2000000, IO_PAGE);279 setdbat(3,PCI0_IO_BASE, PCI0_IO_BASE, 0x10000000, IO_PAGE); 269 280 270 281 271 282 /* … … 322 333 */ 323 334 Cpu_table.exceptions_in_RAM = TRUE; 324 335 initialize_exceptions(); 336 337 /* <SKF> pci_initialize() before BSP_rtems_irq_mng_init to identify the version of the 338 * Discovery chip. 339 */ 340 #ifdef SHOW_MORE_INIT_SETTINGS 341 printk("Going to start PCI buses scanning and initialization\n"); 342 #endif 343 pci_initialize(); 344 #ifdef SHOW_MORE_INIT_SETTINGS 345 printk("Number of PCI buses found is : %d\n", pci_bus_count()); 346 #endif 347 348 /* 349 * Initalize RTEMS IRQ system 350 */ 351 BSP_rtems_irq_mng_init(0); 352 325 353 /* 326 354 * Init MMU block address translation to enable hardware 327 355 * access 328 356 * More PCI1 memory mapping to be done after BSP_pgtbl_activate. 329 357 */ 330 358 printk("-----------------------------------------\n"); 331 printk("Welcome to %s on MVME5500 -0163\n", _RTEMS_version );359 printk("Welcome to %s on MVME5500\n", _RTEMS_version ); 332 360 printk("-----------------------------------------\n"); 333 361 334 362 #ifdef TEST_RETURN_TO_PPCBUG … … 353 381 __asm__ __volatile ("sc"); 354 382 #endif 355 383 356 BSP_mem_size = _512M; 357 /* TODO: calculate the BSP_bus_frequency using the REF_CLK bit of System Status register */ 384 BSP_mem_size = probeMemoryEnd(); 358 385 /* rtems_bsp_delay_in_bus_cycles are defined in registers.h */ 359 386 BSP_bus_frequency = 133333333; 360 387 BSP_processor_frequency = 1000000000; … … 401 428 402 429 BSP_Configuration.work_space_start = work_space_start; 403 430 404 /*405 * Initalize RTEMS IRQ system406 */407 BSP_rtems_irq_mng_init(0);408 409 431 #ifdef SHOW_LCR2_REGISTER 410 432 l2cr = get_L2CR(); 411 433 printk("Initial L2CR value = %x\n", l2cr); … … 429 451 BSP_pgtbl_activate(pt); 430 452 } 431 453 454 if ( I2Cread_eeprom(0xa8, 0,2, (void *) pVPD, sizeof(ConfVpdRec_t))) 455 printk("I2Cread_eeprom() error \n"); 456 else { 457 #ifdef CONF_VPD 458 printk("\n"); 459 for (i=0; i<150; i++) { 460 printk("%2x ", ConfVPD_buff[i]); 461 if ((i % 20)==0 ) printk("\n"); 462 } 463 #endif 464 } 465 432 466 /* 433 467 * PCI 1 domain memory space 434 468 */ 435 469 setdbat(1, PCI1_MEM_BASE, PCI1_MEM_BASE, 0x10000000, IO_PAGE); 436 470 437 438 #ifdef SHOW_MORE_INIT_SETTINGS439 printk("Going to start PCI buses scanning and initialization\n");440 #endif441 pci_initialize();442 #ifdef SHOW_MORE_INIT_SETTINGS443 printk("Number of PCI buses found is : %d\n", pci_bus_count());444 #endif445 446 471 /* Install our own exception handler (needs PCI) */ 447 472 globalExceptHdl = BSP_exceptionHandler; 448 473 474 475 #if 1 449 476 /* clear hostbridge errors. MCP signal is not used on the MVME5500 450 477 * PCI config space scanning code will trip otherwise :-( 451 478 */ 452 479 _BSP_clear_hostbridge_errors(0, 1 /*quiet*/); 453 454 /* Read Configuration Vital Product Data (VPD) */455 if ( I2Cread_eeprom(0xa8, 4,2, &ConfVPD_buff[0], 150))456 printk("I2Cread_eeprom() error \n");457 else {458 #ifdef CONF_VPD459 printk("\n");460 for (i=0; i<150; i++) {461 printk("%2x ", ConfVPD_buff[i]);462 if ((i % 20)==0 ) printk("\n");463 }464 printk("\n");465 480 #endif 466 }467 481 468 482 #ifdef SHOW_MORE_INIT_SETTINGS 469 483 printk("MSR %x \n", _read_MSR()); 470 484 printk("Exit from bspstart\n"); 471 485 #endif 472 473 486 } -
startup/CVS/Entries
diff -Naur mvme5500.orig/startup/CVS/Entries mvme5500/startup/CVS/Entries
old new 1 /bootpstuff.c/1.1/Wed Oct 20 15:21:05 2004// 2 /bspclean.c/1.2/Fri Apr 15 20:13:18 2005// 3 /bspstart.c/1.13/Thu Nov 3 21:38:36 2005// 4 /pgtbl_activate.c/1.1/Wed Oct 20 15:21:05 2004// 5 /reboot.c/1.2/Fri Apr 15 20:13:18 2005// 6 D -
startup/CVS/Repository
diff -Naur mvme5500.orig/startup/CVS/Repository mvme5500/startup/CVS/Repository
old new 1 rtems/c/src/lib/libbsp/powerpc/mvme5500/startup -
startup/CVS/Root
diff -Naur mvme5500.orig/startup/CVS/Root mvme5500/startup/CVS/Root
old new 1 :pserver:anoncvs@www.rtems.com:/usr1/CVS -
startup/pgtbl_activate.c
diff -Naur mvme5500.orig/startup/pgtbl_activate.c mvme5500/startup/pgtbl_activate.c
old new 11 11 12 12 /* Author: Till Straumann, <strauman@slac.stanford.edu>, 4/2002 13 13 * Kate Feng <feng1@bnl.gov> ported it to MVME5500, 4/2004 14 * 14 15 */ 15 16 16 17 void -
startup/reboot.c
diff -Naur mvme5500.orig/startup/reboot.c mvme5500/startup/reboot.c
old new 1 /* Copyright 2003, Shuchen Kate Feng <feng1@bnl.gov>, 2 * NSLS,Brookhaven National Laboratory 3 * 4 * Ported it from powerpc/shared/console/reboot.c for mvme5500 5 * 6 */ 1 7 #include <rtems.h> 2 8 #include <bsp.h> 3 9 #include <rtems/bspIo.h> … … 12 18 13 19 printk("RTEMS terminated; Rebooting ...\n"); 14 20 /* Mvme5500 board reset : 2004 S. Kate Feng <feng1@bnl.gov> */ 15 out_8((volatile unsigned char*) (GT64 260_DEV1_BASE +2), 0x80);21 out_8((volatile unsigned char*) (GT64x60_DEV1_BASE +2), 0x80); 16 22 } -
vme/vmeconfig.c
diff -Naur mvme5500.orig/vme/vmeconfig.c mvme5500/vme/vmeconfig.c
old new 1 /* vmeconfig.c,v 1.1.2.2 2003/03/25 16:46:01 joel Exp */ 2 3 /* Standard VME bridge configuration for PPC boards */ 4 5 /* Copyright Author: Till Straumann <strauman@slac.stanford.edu>, 3/2002 */ 6 7 /* Copyright 2004, Brookhaven National Lab. and S. Kate Feng <feng1@bnl.gov> 8 * Modified to support the MVME5500, 3/2004 9 */ 10 11 #include <bsp.h> 12 #include <bsp/VME.h> 13 #include <bsp/VMEConfig.h> 14 #include <bsp/vmeUniverse.h> 15 #include <bsp/irq.h> 16 #include <libcpu/bat.h> 17 18 /* Use a weak alias for the VME configuration. 19 * This permits individual applications to override 20 * this routine. 21 * They may even create an 'empty' 22 * 23 * void BSP_vme_config(void) {} 24 * 25 * which will avoid linking in the Universe driver 26 * at all :-). 27 */ 28 29 void BSP_vme_config(void) __attribute__ (( weak, alias("__BSP_default_vme_config") )); 30 31 /* translate through host bridge and vme master window of vme bridge */ 32 int 33 BSP_vme2local_adrs(unsigned long am, unsigned long vmeaddr, unsigned long *plocaladdr) 34 { 35 int rval=vmeUniverseXlateAddr(1,0,am,vmeaddr,plocaladdr); 36 *plocaladdr+=PCI_MEM_BASE; 37 return rval; 38 } 39 40 /* how a CPU address is mapped to the VME bus (if at all) */ 41 int 42 BSP_local2vme_adrs(unsigned long am, unsigned long localaddr, unsigned long *pvmeaddr) 43 { 44 return vmeUniverseXlateAddr(0, 0, am,localaddr+PCI_DRAM_OFFSET,pvmeaddr); 45 } 46 47 int BSP_installVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *arg) 48 { 49 return(vmeUniverseInstallISR(vector, handler, arg)); 50 } 51 52 int 53 BSP_removeVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *arg) 54 { 55 return(vmeUniverseRemoveISR(vector, handler, arg)); 56 } 57 58 /* retrieve the currently installed ISR for a given vector */ 59 BSP_VME_ISR_t BSP_getVME_isr(unsigned long vector, void **parg) 60 { 61 return(vmeUniverseISRGet(vector, parg)); 62 } 63 64 int BSP_enableVME_int_lvl(unsigned int level) 65 { 66 return(vmeUniverseIntEnable(level)); 67 } 68 69 int BSP_disableVME_int_lvl(unsigned int level) 70 { 71 return(vmeUniverseIntDisable(level)); 72 } 73 74 75 void 76 __BSP_default_vme_config(void) 77 { 78 79 vmeUniverseInit(); 80 vmeUniverseReset(); 81 82 /* setup a PCI0 area to map the VME bus */ 83 setdbat(0,_VME_A32_WIN0_ON_PCI, _VME_A32_WIN0_ON_PCI, 0x10000000, IO_PAGE); 84 85 /* map VME address ranges */ 86 vmeUniverseMasterPortCfg( 87 0, 88 VME_AM_EXT_SUP_DATA, 89 _VME_A32_WIN0_ON_VME, 90 _VME_A32_WIN0_ON_PCI, 91 0x0F000000); 92 vmeUniverseMasterPortCfg( 93 1, 94 VME_AM_STD_SUP_DATA, 95 0x00000000, 96 _VME_A24_ON_PCI, 97 0x00ff0000); 98 vmeUniverseMasterPortCfg( 99 2, 100 VME_AM_SUP_SHORT_IO, 101 0x00000000, 102 _VME_A16_ON_PCI, 103 0x00010000); 104 105 #ifdef _VME_DRAM_OFFSET 106 /* map our memory to VME */ 107 vmeUniverseSlavePortCfg( 108 0, 109 VME_AM_EXT_SUP_DATA| VME_AM_IS_MEMORY, 110 _VME_DRAM_OFFSET, 111 PCI_DRAM_OFFSET, 112 BSP_mem_size); 113 114 /* make sure the host bridge PCI master is enabled */ 115 vmeUniverseWriteReg( 116 vmeUniverseReadReg(UNIV_REGOFF_PCI_CSR) | UNIV_PCI_CSR_BM, 117 UNIV_REGOFF_PCI_CSR); 118 #endif 119 120 /* stdio is not yet initialized; the driver will revert to printk */ 121 vmeUniverseMasterPortsShow(0); 122 vmeUniverseSlavePortsShow(0); 123 124 /* install the VME insterrupt manager */ 125 vmeUniverseInstallIrqMgrAlt(1, 126 0, BSP_GPP_IRQ_LOWEST_OFFSET + 12, 127 1, BSP_GPP_IRQ_LOWEST_OFFSET + 13, 128 2, BSP_GPP_IRQ_LOWEST_OFFSET + 14, 129 3, BSP_GPP_IRQ_LOWEST_OFFSET + 15, 130 -1); 131 132 }