Ticket #1237: pr1237-46.diff
File pr1237-46.diff, 35.1 KB (added by Joel Sherrill, on 05/10/07 at 17:44:04) |
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cpukit/score/cpu/sparc/.cvsignore
RCS file: /usr1/CVS/rtems/cpukit/score/cpu/sparc/.cvsignore,v retrieving revision 1.4 retrieving revision 1.3 diff -u -r1.4 -r1.3
1 aclocal.m4 2 autom4te*.cache 3 config.cache 4 config.guess 5 config.log 6 config.status 7 config.sub 8 configure 9 depcomp 10 install-sh 1 11 Makefile 2 12 Makefile.in 13 missing 14 mkinstalldirs -
cpukit/score/cpu/sparc/ChangeLog
RCS file: /usr1/CVS/rtems/cpukit/score/cpu/sparc/ChangeLog,v retrieving revision 1.78 retrieving revision 1.35.2.9 diff -u -r1.78 -r1.35.2.9
1 2007-05- 09 Ralf Corsépius <ralf.corsepius@rtems.org>1 2007-05-10 Joel Sherrill <joel.sherrill@OARcorp.com> 2 2 3 * rtems/score/cpu.h: Remove CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES. 4 5 2007-04-17 Ralf Corsépius <ralf.corsepius@rtems.org> 6 7 * cpu.c: 8 Use Context_Control_fp* instead of void* for fp_contexts. 9 * rtems/score/cpu.h: 10 Use Context_Control_fp* instead of void* for fp_contexts. 11 Eliminate evil casts. 12 13 2006-11-17 Ralf Corsépius <ralf.corsepius@rtems.org> 14 15 * rtems/score/types.h: Remove unsigned64, signed64. 3 PR 1237/rtems 4 * cpu.c, cpu_asm.S, rtems/score/cpu.h: Add logic to prevent stack creep 5 when interrupts occur at a sufficient rate that the interrupted 6 thread never gets to clean its stack. This patch ensures that an 7 interrupted thread will not nest ISR dispatches on its stack. 16 8 17 9 2006-11-14 Jiri Gaisler <jiri@gaisler.com> 18 10 19 11 * cpu_asm.S: Properly support synchronous traps. 20 12 21 2006-01-16 Joel Sherrill <joel@OARcorp.com> 22 23 * rtems/score/cpu.h: Part of a large patch to improve Doxygen output. 24 As a side-effect, grammar and spelling errors were corrected, spacing 25 errors were address, and some variable names were improved. 26 27 2005-11-08 Ralf Corsepius <ralf.corsepius@rtems.org> 28 29 * rtems/score/types.h: Eliminate unsigned16, unsigned32. 30 31 2005-10-27 Ralf Corsepius <ralf.corsepius@rtems.org> 32 33 * rtems/asm.h: Remove private version of CONCAT macros. 34 Include <rtems/concat.h> instead. 35 36 2005-02-08 Ralf Corsepius <ralf.corsepius@rtems.org> 37 38 * Makefile.am: Split out preinstallation rules. 39 * preinstall.am: New (Split out from Makefile.am). 40 41 2005-02-04 Ralf Corsepius <ralf.corsepius@rtems.org> 42 43 PR 754/rtems 44 * rtems/asm.h: New (relocated from .). 45 * asm.h: Remove (moved to rtems/asm.h). 46 * Makefile.am: Reflect changes above. 47 48 2004-01-28 Ralf Corsepius <ralf.corsepiu@rtems.org> 49 50 * asm.h, rtems/score/cpu.h, rtems/score/sparc.h, 51 rtems/score/types.h: New header guards. 52 53 2005-01-24 Ralf Corsepius <ralf.corsepius@rtems.org> 54 55 * rtems/score/types.h: Remove signed8, signed16, signed32, 56 unsigned8, unsigned16, unsigned32. 57 58 2005-01-24 Ralf Corsepius <ralf.corsepius@rtems.org> 59 60 * rtems/score/cpu.h: *_swap_u32( uint32_t ). 61 62 2005-01-24 Ralf Corsepius <ralf.corsepius@rtems.org> 63 64 * rtems/score/types.h: #include <rtems/stdint.h>. 65 66 2005-01-22 Ralf Corsepius <ralf.corsepius@rtems.org> 67 68 * rtems/score/cpu.h: Fix broken #endif. 69 70 2005-01-07 Ralf Corsepius <ralf.corsepius@rtems.org> 71 72 * Makefile.am: Eliminate CFLAGS_OPTIMIZE_V. 73 74 2005-01-01 Ralf Corsepius <ralf.corsepius@rtems.org> 75 76 * Makefile.am: Remove build-variant support. 77 78 2004-11-21 Ralf Corsepius <ralf.corsepius@rtems.org> 79 80 * rtems/score/types.h: Use __rtems_score_types_h as preprocessor 81 guard. 82 83 2004-11-21 Ralf Corsepius <ralf.corsepius@rtems.org> 84 85 * asm.h: Add doxygen preamble. 86 87 2004-10-02 Ralf Corsepius <ralf_corsepius@rtems.org> 88 89 * rtems/score/cpu.h: Add doxygen preamble. 90 * rtems/score/sparc.h: Add doxygen preamble. 91 * rtems/score/types.h: Add doxygen preamble. 13 2006-09-07 Ken Peters <ken.peters@jpl.nasa.gov> 92 14 93 2004-04-06 Ralf Corsepius <ralf_corsepius@rtems.org> 15 PR 1173/rtems 16 * rtems/score/cpu.h: Add missing comment characters on endif. 94 17 95 * configure.ac: Remove (Merged into$(top_srcdir)/configure.ac). 96 * Makefile.am: Don't include multilib.am. 97 Reflect merging configure.ac into $(top_srcdir)/configure.ac. 98 99 2004-04-01 Ralf Corsepius <ralf_corsepius@rtems.org> 100 101 * Makefile.am: Install asm.h to $(includedir)/rtems. 102 103 2004-04-01 Ralf Corsepius <ralf_corsepius@rtems.org> 104 105 * cpu_asm.S: Include <rtems/asm.h> instead of <asm.h>. 106 107 2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org> 108 109 * cpu.c, rtems/score/cpu.h, rtems/score/sparc.h: Convert to using 110 c99 fixed size types. 111 112 2004-03-29 Ralf Corsepius <ralf_corsepius@rtems.org> 113 114 * configure.ac: RTEMS_TOP([../../../..]). 18 2005-10-05 Jiri Gaisler <jiri@gaisler.com> 19 Edvin Catovic <edvin@gaisler.com> 20 Konrad Eisele <konrad@gaisler.com> 21 22 PR 827/bsps 23 * ChangeLog, cpu.c, cpu_asm.S, rtems/score/cpu.h: Portion of large 24 update of SPARC BSPs. Includes addition of sis, leon2 and leon3 BSPs, 25 deletion of leon BSP, addition of SMC91111 NIC driver and much more. 26 27 2004-06-16 Edvin Catovic <edvin@gaisler.com> 28 29 * cpu_asm.S: Added FP context initialization routine 30 _CPU_Context_initialize_fp 31 * cpu.c: Changed FP context initialization. 32 * rtems/score/sparc.h: Defined SPARC_HAS_FPU to be 1 (Non-FP BSPs 33 erc32nfp and leon1 are removed) 115 34 116 35 2004-02-26 Andreas Karlsson <andreas.karlsson@space.se> 117 36 … … 119 38 * cpu_asm.S: Close window while restoring interrupted task state which 120 39 resulted in CWP corruption. 121 40 122 2004-01-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>123 124 * configure.ac: Move RTEMS_TOP one subdir down.125 126 2004-01-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de>127 128 * Makefile.am: Add PREINSTALL_DIRS.129 130 2004-01-14 Ralf Corsepius <corsepiu@faw.uni-ulm.de>131 132 * Makefile.am: Re-add dirstamps to PREINSTALL_FILES.133 Add PREINSTALL_FILES to CLEANFILES.134 135 2004-01-12 Ralf Corsepius <corsepiu@faw.uni-ulm.de>136 137 * configure.ac: Requires automake >= 1.8.1.138 139 2004-01-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>140 141 * Makefile.am: Include compile.am, again.142 143 2004-01-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>144 145 * Makefile.am: Convert to using automake compilation rules.146 147 2003-12-12 Ralf Corsepius <corsepiu@faw.uni-ulm.de>148 149 * Makefile.am: Use mkdir_p. Remove dirs from PREINSTALL_FILES.150 151 2003-12-12 Ralf Corsepius <corsepiu@faw.uni-ulm.de>152 153 * configure.ac: Require automake >= 1.8, autoconf >= 2.59.154 155 2003-12-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de>156 157 * Makefile.am: Remove TMPINSTALL_FILES.158 159 2003-11-30 Ralf Corsepius <corsepiu@faw.uni-ulm.de>160 161 * Makefile.am: Add $(dirstamp) to preinstallation rules.162 163 2003-11-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de>164 165 * Makefile.am: Don't use gmake rules for preinstallation.166 167 2003-10-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>168 169 * configure.ac: Remove RTEMS_CANONICAL_HOST.170 171 2003-10-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>172 173 * configure.ac: Remove RTEMS_CHECK_CPU.174 175 41 2003-09-04 Joel Sherrill <joel@OARcorp.com> 176 42 177 43 * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/sparc.h, -
cpukit/score/cpu/sparc/Makefile.am
RCS file: /usr1/CVS/rtems/cpukit/score/cpu/sparc/Makefile.am,v retrieving revision 1.39 retrieving revision 1.20 diff -u -r1.39 -r1.20
1 1 ## 2 ## $Id: Makefile.am,v 1. 39 2006/01/12 09:57:43ralf Exp $2 ## $Id: Makefile.am,v 1.20 2002/12/11 17:08:30 ralf Exp $ 3 3 ## 4 4 5 include $(top_srcdir)/automake/compile.am 5 ACLOCAL_AMFLAGS = -I ../../../aclocal 6 6 7 include_rtemsdir = $(includedir)/rtems 8 include_rtems_HEADERS = rtems/asm.h 7 include $(top_srcdir)/../../../automake/multilib.am 8 include $(top_srcdir)/../../../automake/compile.am 9 include $(top_srcdir)/../../../automake/lib.am 10 11 $(PROJECT_INCLUDE)/%.h: %.h 12 $(INSTALL_DATA) $< $@ 13 14 $(PROJECT_INCLUDE): 15 $(mkinstalldirs) $@ 16 17 $(PROJECT_INCLUDE)/rtems: 18 $(mkinstalldirs) $@ 19 20 $(PROJECT_INCLUDE)/rtems/score: 21 $(mkinstalldirs) $@ 22 23 include_HEADERS= asm.h 24 PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%) 9 25 10 26 include_rtems_scoredir = $(includedir)/rtems/score 11 include_rtems_score_HEADERS = rtems/score/sparc.h rtems/score/cpu.h \ 27 include_rtems_score_HEADERS = \ 28 rtems/score/sparc.h \ 29 rtems/score/cpu.h \ 12 30 rtems/score/types.h 31 PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \ 32 $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) 33 34 C_FILES = cpu.c 35 OBJS = $(C_FILES:%.c=$(ARCH)/%.$(OBJEXT)) 36 37 S_FILES = cpu_asm.S 38 OBJS += $(S_FILES:%.S=$(ARCH)/%.$(OBJEXT)) 39 40 LIB = $(ARCH)/libscorecpu.a 41 42 $(LIB): $(OBJS) 43 $(make-library) 44 45 all-local: $(ARCH) $(PREINSTALL_FILES) $(LIB) \ 46 $(TMPINSTALL_FILES) 13 47 14 noinst_LIBRARIES = libscorecpu.a 15 libscorecpu_a_SOURCES = cpu.c cpu_asm.S 16 libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS) 48 EXTRA_DIST = cpu.c cpu_asm.S 17 49 18 include $(srcdir)/preinstall.am 19 include $(top_srcdir)/automake/local.am 50 include $(top_srcdir)/../../../automake/local.am -
cpukit/score/cpu/sparc/cpu.c
RCS file: /usr1/CVS/rtems/cpukit/score/cpu/sparc/cpu.c,v retrieving revision 1.19 retrieving revision 1.16.2.3 diff -u -r1.19 -r1.16.2.3
8 8 * found in the file LICENSE in this distribution or at 9 9 * http://www.rtems.com/license/LICENSE. 10 10 * 11 * $Id: cpu.c,v 1.1 9 2007/04/17 04:51:28 ralfExp $11 * $Id: cpu.c,v 1.16.2.3 2007/05/10 18:41:42 joel Exp $ 12 12 */ 13 13 14 14 #include <rtems/system.h> … … 53 53 void (*thread_dispatch) /* ignored on this CPU */ 54 54 ) 55 55 { 56 #if (SPARC_HAS_FPU == 1) 57 Context_Control_fp *pointer; 56 void *pointer; 58 57 59 58 /* 60 * This seems to be the most appropriate way to obtain an initial 61 * FP context on the SPARC. The NULL fp context is copied it to 59 * FP context is initialized. The NULL fp context is copied it to 62 60 * the task's FP context during Context_Initialize. 63 61 */ 64 62 65 63 pointer = &_CPU_Null_fp_context; 66 _CPU_Context_save_fp( &pointer ); 67 #endif 64 _CPU_Context_initialize_fp(pointer); 68 65 69 66 /* 70 67 * Grab our own copy of the user's CPU table. 71 68 */ 72 69 73 70 _CPU_Table = *cpu_table; 71 72 /* 73 * Since no tasks have been created yet and no interrupts have occurred, 74 * there is no way that the currently executing thread can have an 75 * _ISR_Dispatch stack frame on its stack. 76 */ 77 _CPU_ISR_Dispatch_disable = 0; 74 78 } 75 79 76 80 /*PAGE … … 83 87 * returns the current interrupt level (PIL field of the PSR) 84 88 */ 85 89 86 u int32_t_CPU_ISR_Get_level( void )90 unsigned32 _CPU_ISR_Get_level( void ) 87 91 { 88 u int32_tlevel;92 unsigned32 level; 89 93 90 94 sparc_get_interrupt_level( level ); 91 95 … … 131 135 */ 132 136 133 137 void _CPU_ISR_install_raw_handler( 134 u int32_tvector,138 unsigned32 vector, 135 139 proc_ptr new_handler, 136 140 proc_ptr *old_handler 137 141 ) 138 142 { 139 u int32_treal_vector;143 unsigned32 real_vector; 140 144 CPU_Trap_table_entry *tbr; 141 145 CPU_Trap_table_entry *slot; 142 u int32_tu32_tbr;143 u int32_tu32_handler;146 unsigned32 u32_tbr; 147 unsigned32 u32_handler; 144 148 145 149 /* 146 150 * Get the "real" trap number for this vector ignoring the synchronous … … 187 191 188 192 *slot = _CPU_Trap_slot_template; 189 193 190 u32_handler = (u int32_t) new_handler;194 u32_handler = (unsigned32) new_handler; 191 195 192 196 slot->mov_vector_l3 |= vector; 193 197 slot->sethi_of_handler_to_l4 |= … … 218 222 */ 219 223 220 224 void _CPU_ISR_install_vector( 221 u int32_tvector,225 unsigned32 vector, 222 226 proc_ptr new_handler, 223 227 proc_ptr *old_handler 224 228 ) 225 229 { 226 u int32_treal_vector;230 unsigned32 real_vector; 227 231 proc_ptr ignored; 228 232 229 233 /* … … 273 277 274 278 void _CPU_Context_Initialize( 275 279 Context_Control *the_context, 276 u int32_t*stack_base,277 u int32_tsize,278 u int32_tnew_level,280 unsigned32 *stack_base, 281 unsigned32 size, 282 unsigned32 new_level, 279 283 void *entry_point, 280 284 boolean is_fp 281 285 ) 282 286 { 283 u int32_tstack_high; /* highest "stack aligned" address */284 u int32_tthe_size;285 u int32_ttmp_psr;287 unsigned32 stack_high; /* highest "stack aligned" address */ 288 unsigned32 the_size; 289 unsigned32 tmp_psr; 286 290 287 291 /* 288 292 * On CPUs with stacks which grow down (i.e. SPARC), we build the stack 289 293 * based on the stack_high address. 290 294 */ 291 295 292 stack_high = ((u int32_t)(stack_base) + size);296 stack_high = ((unsigned32)(stack_base) + size); 293 297 stack_high &= ~(CPU_STACK_ALIGNMENT - 1); 294 298 295 299 the_size = size & ~(CPU_STACK_ALIGNMENT - 1); … … 298 302 * See the README in this directory for a diagram of the stack. 299 303 */ 300 304 301 the_context->o7 = ((u int32_t) entry_point) - 8;305 the_context->o7 = ((unsigned32) entry_point) - 8; 302 306 the_context->o6_sp = stack_high - CPU_MINIMUM_STACK_FRAME_SIZE; 303 307 the_context->i6_fp = stack_high; 304 308 … … 316 320 tmp_psr |= (new_level << 8) & SPARC_PSR_PIL_MASK; 317 321 tmp_psr &= ~SPARC_PSR_EF_MASK; /* disabled by default */ 318 322 319 #if (SPARC_HAS_FPU == 1)320 323 /* 321 324 * If this bit is not set, then a task gets a fault when it accesses 322 325 * a floating point register. This is a nice way to detect floating … … 325 328 326 329 if ( is_fp ) 327 330 tmp_psr |= SPARC_PSR_EF_MASK; 328 #endif 331 329 332 the_context->psr = tmp_psr; 333 334 /* 335 * Since THIS thread is being created, there is no way that THIS 336 * thread can have an _ISR_Dispatch stack frame on its stack. 337 */ 338 the_context->isr_dispatch_disable = 0; 330 339 } -
cpukit/score/cpu/sparc/cpu_asm.S
RCS file: /usr1/CVS/rtems/cpukit/score/cpu/sparc/cpu_asm.S,v retrieving revision 1.12 retrieving revision 1.8.2.5 diff -u -r1.12 -r1.8.2.5
18 18 * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. 19 19 * European Space Agency. 20 20 * 21 * $Id: cpu_asm.S,v 1. 12 2006/11/14 21:44:25joel Exp $21 * $Id: cpu_asm.S,v 1.8.2.5 2007/05/10 18:41:42 joel Exp $ 22 22 */ 23 23 24 #include < rtems/asm.h>24 #include <asm.h> 25 25 26 #if (SPARC_HAS_FPU == 1) 26 /* 27 * void _CPU_Context_initialize_fp( 28 * void *fp_context_ptr 29 * ) 30 * 31 * This routine is responsible for initializing the FP context 32 * at *fp_context_ptr. All registers and FSR in the FP context 33 * are initailized to 0. 34 * 35 */ 36 37 .align 4 38 PUBLIC(_CPU_Context_initialize_fp) 39 SYM(_CPU_Context_initialize_fp): 40 set 0, %l1 41 fpcontextinit: 42 std %g0, [%o0] ! write register fields of the FP context 43 add %l1, 1, %l1 44 cmp %l1, 16 45 bne fpcontextinit 46 add %o0, 8, %o0 47 retl 48 st %g0, [%o0] ! write fsr field of the FP context 49 50 27 51 28 52 /* 29 53 * void _CPU_Context_save_fp( … … 123 147 ret 124 148 restore 125 149 126 #endif /* SPARC_HAS_FPU */127 128 150 /* 129 151 * void _CPU_Context_switch( 130 152 * Context_Control *run, … … 143 165 std %g4, [%o0 + G4_OFFSET] 144 166 std %g6, [%o0 + G6_OFFSET] 145 167 168 ! load the address of the ISR stack nesting prevention flag 169 sethi %hi(SYM(_CPU_ISR_Dispatch_disable)), %g2 170 ld [%g2 + %lo(SYM(_CPU_ISR_Dispatch_disable))], %g2 171 ! save it a bit later so we do not waste a couple of cycles 172 146 173 std %l0, [%o0 + L0_OFFSET] ! save the local registers 147 174 std %l2, [%o0 + L2_OFFSET] 148 175 std %l4, [%o0 + L4_OFFSET] 149 176 std %l6, [%o0 + L6_OFFSET] 150 177 178 ! Now actually save ISR stack nesting prevention flag 179 st %g2, [%o0 + ISR_DISPATCH_DISABLE_STACK_OFFSET] 180 151 181 std %i0, [%o0 + I0_OFFSET] ! save the input registers 152 182 std %i2, [%o0 + I2_OFFSET] 153 183 std %i4, [%o0 + I4_OFFSET] … … 270 300 ldd [%o1 + G4_OFFSET], %g4 271 301 ldd [%o1 + G6_OFFSET], %g6 272 302 303 ! Load thread specific ISR dispatch prevention flag 304 ld [%o1 + ISR_DISPATCH_DISABLE_STACK_OFFSET], %o2 305 sethi %hi(SYM(_CPU_ISR_Dispatch_disable)), %o3 306 ! Store it to memory later to use the cycles 307 273 308 ldd [%o1 + L0_OFFSET], %l0 ! restore the local registers 274 309 ldd [%o1 + L2_OFFSET], %l2 275 310 ldd [%o1 + L4_OFFSET], %l4 276 311 ldd [%o1 + L6_OFFSET], %l6 277 312 313 ! Now restore thread specific ISR dispatch prevention flag 314 st %o2,[%o3 + %lo(SYM(_CPU_ISR_Dispatch_disable))] 315 278 316 ldd [%o1 + I0_OFFSET], %i0 ! restore the output registers 279 317 ldd [%o1 + I2_OFFSET], %i2 280 318 ldd [%o1 + I4_OFFSET], %i4 … … 633 671 634 672 orcc %l6, %g0, %g0 ! Is dispatching disabled? 635 673 bnz simple_return ! Yes, then do a "simple" exit 636 nop ! delay slot 674 ! NOTE: Use the delay slot 675 sethi %hi(SYM(_CPU_ISR_Dispatch_disable)), %l6 676 677 ! Are we dispatching from a previous ISR in the interrupted thread? 678 ld [%l6 + %lo(SYM(_CPU_ISR_Dispatch_disable))], %l7 679 orcc %l7, %g0, %g0 ! Is this thread already doing an ISR? 680 bnz simple_return ! Yes, then do a "simple" exit 681 ! NOTE: Use the delay slot 682 sethi %hi(SYM(_Context_Switch_necessary)), %l4 683 637 684 638 685 /* 639 686 * If a context switch is necessary, then do fudge stack to 640 687 * return to the interrupt dispatcher. 641 688 */ 642 689 643 sethi %hi(SYM(_Context_Switch_necessary)), %l4644 690 ld [%l4 + %lo(SYM(_Context_Switch_necessary))], %l5 645 691 646 692 orcc %l5, %g0, %g0 ! Is thread switch necessary? 647 693 bnz SYM(_ISR_Dispatch) ! yes, then invoke the dispatcher 648 nop ! delay slot 694 ! NOTE: Use the delay slot 695 sethi %hi(SYM(_ISR_Signals_to_thread_executing)), %l6 649 696 650 697 /* 651 698 * Finally, check to see if signals were sent to the currently 652 699 * executing task. If so, we need to invoke the interrupt dispatcher. 653 700 */ 654 701 655 sethi %hi(SYM(_ISR_Signals_to_thread_executing)), %l6656 702 ld [%l6 + %lo(SYM(_ISR_Signals_to_thread_executing))], %l7 657 703 658 704 orcc %l7, %g0, %g0 ! Were signals sent to the currently … … 669 715 670 716 PUBLIC(_ISR_Dispatch) 671 717 SYM(_ISR_Dispatch): 718 ! Set ISR dispatch nesting prevention flag 719 mov 1,%l6 720 sethi %hi(SYM(_CPU_ISR_Dispatch_disable)), %l5 721 st %l6,[%l5 + %lo(SYM(_CPU_ISR_Dispatch_disable))] 672 722 673 723 /* 674 724 * The following subtract should get us back on the interrupted … … 684 734 nop 685 735 nop 686 736 nop 687 737 isr_dispatch: 688 738 call SYM(_Thread_Dispatch), 0 689 739 nop 690 740 … … 700 750 ta 0 ! syscall (disable interrupts) 701 751 702 752 /* 753 * While we had ISR dispatching disabled in this thread, 754 * did we miss anything. If so, then we need to do another 755 * _Thread_Dispatch before leaving this ISR Dispatch context. 756 */ 757 758 sethi %hi(SYM(_Context_Switch_necessary)), %l4 759 ld [%l4 + %lo(SYM(_Context_Switch_necessary))], %l5 760 761 ! NOTE: Use some of delay slot to start loading this 762 sethi %hi(SYM(_ISR_Signals_to_thread_executing)), %l6 763 ld [%l6 + %lo(SYM(_ISR_Signals_to_thread_executing))], %l7 764 765 orcc %l5, %g0, %g0 ! Is thread switch necessary? 766 bnz dispatchAgain ! yes, then invoke the dispatcher AGAIN 767 ! NOTE: Use the delay slot to catch the orcc below 768 769 /* 770 * Finally, check to see if signals were sent to the currently 771 * executing task. If so, we need to invoke the interrupt dispatcher. 772 */ 773 774 ! NOTE: Delay slots above were used to perform the load AND 775 ! this orcc falls into the delay slot for bnz above 776 orcc %l7, %g0, %g0 ! Were signals sent to the currently 777 ! executing thread? 778 bz allow_nest_again ! No, then clear out and return 779 ! NOTE: use the delay slot from the bz to load 3 into %g1 780 781 ! Yes, then invoke the dispatcher 782 dispatchAgain: 783 mov 3,%g1 ! syscall (enable interrupts) 784 ta 0 ! syscall (enable interrupts) 785 ba isr_dispatch 786 nop 787 788 allow_nest_again: 789 790 ! Zero out ISR stack nesting prevention flag 791 sethi %hi(SYM(_CPU_ISR_Dispatch_disable)), %l5 792 st %g0,[%l5 + %lo(SYM(_CPU_ISR_Dispatch_disable))] 793 794 /* 703 795 * The CWP in place at this point may be different from 704 796 * that which was in effect at the beginning of the ISR if we 705 797 * have been context switched between the beginning of this invocation -
cpukit/score/cpu/sparc/rtems/score/cpu.h
RCS file: /usr1/CVS/rtems/cpukit/score/cpu/sparc/rtems/score/cpu.h,v retrieving revision 1.22 retrieving revision 1.13.2.4 diff -u -r1.22 -r1.13.2.4
1 /** 2 * @file rtems/score/cpu.h 3 */ 4 5 /* 1 /* cpu.h 2 * 6 3 * This include file contains information pertaining to the port of 7 4 * the executive to the SPARC processor. 8 5 * 9 * COPYRIGHT (c) 1989- 2006.6 * COPYRIGHT (c) 1989-1999. 10 7 * On-Line Applications Research Corporation (OAR). 11 8 * 12 9 * The license and distribution terms for this file may be 13 10 * found in the file LICENSE in this distribution or at 14 11 * http://www.rtems.com/license/LICENSE. 15 12 * 16 * $Id: cpu.h,v 1. 22 2007/05/09 15:28:49 ralfExp $13 * $Id: cpu.h,v 1.13.2.4 2007/05/10 18:41:42 joel Exp $ 17 14 */ 18 15 19 #ifndef _ RTEMS_SCORE_CPU_H20 #define _ RTEMS_SCORE_CPU_H16 #ifndef __CPU_h 17 #define __CPU_h 21 18 22 19 #ifdef __cplusplus 23 20 extern "C" { … … 157 154 * not provide one. 158 155 */ 159 156 160 #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE157 #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE 161 158 162 159 /* 163 160 * Does the stack grow up (toward higher addresses) or down … … 189 186 * routines are handled. 190 187 */ 191 188 189 #define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE 192 190 #define CPU_BIG_ENDIAN TRUE 193 191 #define CPU_LITTLE_ENDIAN FALSE 194 192 … … 212 210 #ifndef ASM 213 211 214 212 typedef struct { 215 u int32_tl0;216 u int32_tl1;217 u int32_tl2;218 u int32_tl3;219 u int32_tl4;220 u int32_tl5;221 u int32_tl6;222 u int32_tl7;223 u int32_ti0;224 u int32_ti1;225 u int32_ti2;226 u int32_ti3;227 u int32_ti4;228 u int32_ti5;229 u int32_ti6_fp;230 u int32_ti7;213 unsigned32 l0; 214 unsigned32 l1; 215 unsigned32 l2; 216 unsigned32 l3; 217 unsigned32 l4; 218 unsigned32 l5; 219 unsigned32 l6; 220 unsigned32 l7; 221 unsigned32 i0; 222 unsigned32 i1; 223 unsigned32 i2; 224 unsigned32 i3; 225 unsigned32 i4; 226 unsigned32 i5; 227 unsigned32 i6_fp; 228 unsigned32 i7; 231 229 void *structure_return_address; 232 230 /* 233 231 * The following are for the callee to save the register arguments in 234 232 * should this be necessary. 235 233 */ 236 u int32_tsaved_arg0;237 u int32_tsaved_arg1;238 u int32_tsaved_arg2;239 u int32_tsaved_arg3;240 u int32_tsaved_arg4;241 u int32_tsaved_arg5;242 u int32_tpad0;234 unsigned32 saved_arg0; 235 unsigned32 saved_arg1; 236 unsigned32 saved_arg2; 237 unsigned32 saved_arg3; 238 unsigned32 saved_arg4; 239 unsigned32 saved_arg5; 240 unsigned32 pad0; 243 241 } CPU_Minimum_stack_frame; 244 242 245 243 #endif /* ASM */ … … 298 296 * and stores safely in the context switch. 299 297 */ 300 298 double g0_g1; 301 u int32_tg2;302 u int32_tg3;303 u int32_tg4;304 u int32_tg5;305 u int32_tg6;306 u int32_tg7;307 308 u int32_tl0;309 u int32_tl1;310 u int32_tl2;311 u int32_tl3;312 u int32_tl4;313 u int32_tl5;314 u int32_tl6;315 u int32_tl7;316 317 u int32_ti0;318 u int32_ti1;319 u int32_ti2;320 u int32_ti3;321 u int32_ti4;322 u int32_ti5;323 u int32_ti6_fp;324 u int32_ti7;325 326 u int32_to0;327 u int32_to1;328 u int32_to2;329 u int32_to3;330 u int32_to4;331 u int32_to5;332 u int32_to6_sp;333 u int32_to7;299 unsigned32 g2; 300 unsigned32 g3; 301 unsigned32 g4; 302 unsigned32 g5; 303 unsigned32 g6; 304 unsigned32 g7; 305 306 unsigned32 l0; 307 unsigned32 l1; 308 unsigned32 l2; 309 unsigned32 l3; 310 unsigned32 l4; 311 unsigned32 l5; 312 unsigned32 l6; 313 unsigned32 l7; 314 315 unsigned32 i0; 316 unsigned32 i1; 317 unsigned32 i2; 318 unsigned32 i3; 319 unsigned32 i4; 320 unsigned32 i5; 321 unsigned32 i6_fp; 322 unsigned32 i7; 323 324 unsigned32 o0; 325 unsigned32 o1; 326 unsigned32 o2; 327 unsigned32 o3; 328 unsigned32 o4; 329 unsigned32 o5; 330 unsigned32 o6_sp; 331 unsigned32 o7; 334 332 335 uint32_t psr; 333 unsigned32 psr; 334 unsigned32 isr_dispatch_disable; 336 335 } Context_Control; 337 336 338 337 #endif /* ASM */ … … 378 377 #define O7_OFFSET 0x7C 379 378 380 379 #define PSR_OFFSET 0x80 380 #define ISR_DISPATCH_DISABLE_STACK_OFFSET 0x84 381 381 382 #define CONTEXT_CONTROL_SIZE 0x8 4382 #define CONTEXT_CONTROL_SIZE 0x88 383 383 384 384 /* 385 385 * The floating point context area. … … 404 404 double f26_f27; 405 405 double f28_f29; 406 406 double f30_f31; 407 u int32_tfsr;407 unsigned32 fsr; 408 408 } Context_Control_fp; 409 409 410 410 #endif /* ASM */ … … 444 444 445 445 typedef struct { 446 446 CPU_Minimum_stack_frame Stack_frame; 447 u int32_tpsr;448 u int32_tpc;449 u int32_tnpc;450 u int32_tg1;451 u int32_tg2;452 u int32_tg3;453 u int32_tg4;454 u int32_tg5;455 u int32_tg6;456 u int32_tg7;457 u int32_ti0;458 u int32_ti1;459 u int32_ti2;460 u int32_ti3;461 u int32_ti4;462 u int32_ti5;463 u int32_ti6_fp;464 u int32_ti7;465 u int32_ty;466 u int32_ttpc;447 unsigned32 psr; 448 unsigned32 pc; 449 unsigned32 npc; 450 unsigned32 g1; 451 unsigned32 g2; 452 unsigned32 g3; 453 unsigned32 g4; 454 unsigned32 g5; 455 unsigned32 g6; 456 unsigned32 g7; 457 unsigned32 i0; 458 unsigned32 i1; 459 unsigned32 i2; 460 unsigned32 i3; 461 unsigned32 i4; 462 unsigned32 i5; 463 unsigned32 i6_fp; 464 unsigned32 i7; 465 unsigned32 y; 466 unsigned32 tpc; 467 467 } CPU_Interrupt_frame; 468 468 469 469 #endif /* ASM */ … … 508 508 void (*postdriver_hook)( void ); 509 509 void (*idle_task)( void ); 510 510 boolean do_zero_of_workspace; 511 u int32_tidle_task_stack_size;512 u int32_tinterrupt_stack_size;513 u int32_textra_mpci_receive_server_stack;514 void * (*stack_allocate_hook)( u int32_t);511 unsigned32 idle_task_stack_size; 512 unsigned32 interrupt_stack_size; 513 unsigned32 extra_mpci_receive_server_stack; 514 void * (*stack_allocate_hook)( unsigned32 ); 515 515 void (*stack_free_hook)( void* ); 516 516 /* end of fields required on all CPUs */ 517 517 … … 553 553 SCORE_EXTERN void *_CPU_Interrupt_stack_high; 554 554 555 555 /* 556 * This flag is context switched with each thread. It indicates 557 * that THIS thread has an _ISR_Dispatch stack frame on its stack. 558 * By using this flag, we can avoid nesting more interrupt dispatching 559 * attempts on a previously interrupted thread's stack. 560 */ 561 562 SCORE_EXTERN volatile uint32_t _CPU_ISR_Dispatch_disable; 563 564 /* 556 565 * The following type defines an entry in the SPARC's trap table. 557 566 * 558 567 * NOTE: The instructions chosen are RTEMS dependent although one is … … 562 571 */ 563 572 564 573 typedef struct { 565 u int32_tmov_psr_l0; /* mov %psr, %l0 */566 u int32_tsethi_of_handler_to_l4; /* sethi %hi(_handler), %l4 */567 u int32_tjmp_to_low_of_handler_plus_l4; /* jmp %l4 + %lo(_handler) */568 u int32_tmov_vector_l3; /* mov _vector, %l3 */574 unsigned32 mov_psr_l0; /* mov %psr, %l0 */ 575 unsigned32 sethi_of_handler_to_l4; /* sethi %hi(_handler), %l4 */ 576 unsigned32 jmp_to_low_of_handler_plus_l4; /* jmp %l4 + %lo(_handler) */ 577 unsigned32 mov_vector_l3; /* mov _vector, %l3 */ 569 578 } CPU_Trap_table_entry; 570 579 571 580 /* … … 637 646 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE 638 647 639 648 /* 640 * Should be large enough to run all tests. This ensures649 * Should be large enough to run all tests. This insures 641 650 * that a "reasonable" small application should not have any problems. 642 651 * 643 652 * This appears to be a fairly generous number for the SPARC since … … 750 759 #define _CPU_ISR_Set_level( _newlevel ) \ 751 760 sparc_enable_interrupts( _newlevel << 8) 752 761 753 u int32_t_CPU_ISR_Get_level( void );762 unsigned32 _CPU_ISR_Get_level( void ); 754 763 755 764 /* end of ISR handler macros */ 756 765 … … 772 781 773 782 void _CPU_Context_Initialize( 774 783 Context_Control *the_context, 775 u int32_t*stack_base,776 u int32_tsize,777 u int32_tnew_level,784 unsigned32 *stack_base, 785 unsigned32 size, 786 unsigned32 new_level, 778 787 void *entry_point, 779 788 boolean is_fp 780 789 ); … … 810 819 811 820 #define _CPU_Context_Initialize_fp( _destination ) \ 812 821 do { \ 813 *( *(_destination)) = _CPU_Null_fp_context; \822 *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \ 814 823 } while (0) 815 824 816 825 /* end of Context handler macros */ … … 825 834 826 835 #define _CPU_Fatal_halt( _error ) \ 827 836 do { \ 828 u int32_tlevel; \837 unsigned32 level; \ 829 838 \ 830 839 level = sparc_disable_interrupts(); \ 831 840 asm volatile ( "mov %0, %%g1 " : "=r" (level) : "0" (level) ); \ … … 884 893 */ 885 894 886 895 void _CPU_ISR_install_raw_handler( 887 u int32_tvector,896 unsigned32 vector, 888 897 proc_ptr new_handler, 889 898 proc_ptr *old_handler 890 899 ); … … 896 905 */ 897 906 898 907 void _CPU_ISR_install_vector( 899 u int32_tvector,908 unsigned32 vector, 900 909 proc_ptr new_handler, 901 910 proc_ptr *old_handler 902 911 ); … … 943 952 */ 944 953 945 954 void _CPU_Context_save_fp( 946 Context_Control_fp**fp_context_ptr955 void **fp_context_ptr 947 956 ); 948 957 949 958 /* … … 953 962 */ 954 963 955 964 void _CPU_Context_restore_fp( 956 Context_Control_fp**fp_context_ptr965 void **fp_context_ptr 957 966 ); 958 967 959 968 /* … … 975 984 * following code at optimization level four (i.e. -O4). 976 985 */ 977 986 978 static inline u int32_t CPU_swap_u32(979 u int32_t value987 static inline unsigned int CPU_swap_u32( 988 unsigned int value 980 989 ) 981 990 { 982 u int32_tbyte1, byte2, byte3, byte4, swapped;991 unsigned32 byte1, byte2, byte3, byte4, swapped; 983 992 984 993 byte4 = (value >> 24) & 0xff; 985 994 byte3 = (value >> 16) & 0xff; -
cpukit/score/cpu/sparc/rtems/score/sparc.h
RCS file: /usr1/CVS/rtems/cpukit/score/cpu/sparc/rtems/score/sparc.h,v retrieving revision 1.12 retrieving revision 1.6.4.1 diff -u -r1.12 -r1.6.4.1
1 /** 2 * @file rtems/score/sparc.h 3 */ 4 5 /* 1 /* sparc.h 2 * 6 3 * This include file contains information pertaining to the SPARC 7 4 * processor family. 8 5 * … … 13 10 * found in the file LICENSE in this distribution or at 14 11 * http://www.rtems.com/license/LICENSE. 15 12 * 16 * $Id: sparc.h,v 1. 12 2005/02/04 05:40:52 ralfExp $13 * $Id: sparc.h,v 1.6.4.1 2003/09/04 18:47:40 joel Exp $ 17 14 */ 18 15 19 #ifndef _ RTEMS_SCORE_SPARC_H20 #define _ RTEMS_SCORE_SPARC_H16 #ifndef _INCLUDE_SPARC_h 17 #define _INCLUDE_SPARC_h 21 18 22 19 #ifdef __cplusplus 23 20 extern "C" { … … 231 228 232 229 #define sparc_flash_interrupts( _level ) \ 233 230 do { \ 234 register u int32_t_ignored = 0; \231 register unsigned32 _ignored = 0; \ 235 232 \ 236 233 sparc_enable_interrupts( (_level) ); \ 237 234 sparc_disable_interrupts( _ignored ); \ … … 240 237 /* 241 238 #define sparc_set_interrupt_level( _new_level ) \ 242 239 do { \ 243 register u int32_t_new_psr_level = 0; \240 register unsigned32 _new_psr_level = 0; \ 244 241 \ 245 242 sparc_get_psr( _new_psr_level ); \ 246 243 _new_psr_level &= ~SPARC_PSR_PIL_MASK; \ … … 252 249 253 250 #define sparc_get_interrupt_level( _level ) \ 254 251 do { \ 255 register u int32_t_psr_level = 0; \252 register unsigned32 _psr_level = 0; \ 256 253 \ 257 254 sparc_get_psr( _psr_level ); \ 258 255 (_level) = \ … … 265 262 } 266 263 #endif 267 264 268 #endif /* _RTEMS_SCORE_SPARC_H */ 265 #endif /* ! _INCLUDE_SPARC_h */ 266 /* end of include file */ -
cpukit/score/cpu/sparc/rtems/score/types.h
RCS file: /usr1/CVS/rtems/cpukit/score/cpu/sparc/rtems/score/types.h,v retrieving revision 1.12 retrieving revision 1.3.2.1 diff -u -r1.12 -r1.3.2.1
1 /** 2 * @file rtems/score/types.h 3 */ 4 5 /* 1 /* sparctypes.h 2 * 6 3 * This include file contains type definitions pertaining to the 7 4 * SPARC processor family. 8 5 * … … 13 10 * found in the file LICENSE in this distribution or at 14 11 * http://www.rtems.com/license/LICENSE. 15 12 * 16 * $Id: types.h,v 1. 12 2006/11/17 05:58:03 ralfExp $13 * $Id: types.h,v 1.3.2.1 2003/09/04 18:47:40 joel Exp $ 17 14 */ 18 15 19 #ifndef _ RTEMS_SCORE_TYPES_H20 #define _ RTEMS_SCORE_TYPES_H16 #ifndef __SPARC_TYPES_h 17 #define __SPARC_TYPES_h 21 18 22 19 #ifndef ASM 23 20 24 #include <rtems/stdint.h>25 26 21 #ifdef __cplusplus 27 22 extern "C" { 28 23 #endif … … 31 26 * This section defines the basic types for this processor. 32 27 */ 33 28 34 typedef uint16_t Priority_Bit_map_control; 29 typedef unsigned char unsigned8; /* unsigned 8-bit integer */ 30 typedef unsigned short unsigned16; /* unsigned 16-bit integer */ 31 typedef unsigned int unsigned32; /* unsigned 32-bit integer */ 32 typedef unsigned long long unsigned64; /* unsigned 64-bit integer */ 33 34 typedef unsigned16 Priority_Bit_map_control; 35 36 typedef signed char signed8; /* 8-bit signed integer */ 37 typedef signed short signed16; /* 16-bit signed integer */ 38 typedef signed int signed32; /* 32-bit signed integer */ 39 typedef signed long long signed64; /* 64 bit signed integer */ 35 40 36 typedef u int32_tboolean; /* Boolean value */41 typedef unsigned32 boolean; /* Boolean value */ 37 42 38 43 typedef float single_precision; /* single precision float */ 39 44 typedef double double_precision; /* double precision float */ … … 48 53 #endif /* !ASM */ 49 54 50 55 #endif 56 /* end of include file */