Ticket #1237: pr1237-46.diff

File pr1237-46.diff, 35.1 KB (added by Joel Sherrill, on May 10, 2007 at 5:44:04 PM)

slightly different patch for 4.6

  • cpukit/score/cpu/sparc/.cvsignore

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/sparc/.cvsignore,v
    retrieving revision 1.4
    retrieving revision 1.3
    diff -u -r1.4 -r1.3
     
     1aclocal.m4
     2autom4te*.cache
     3config.cache
     4config.guess
     5config.log
     6config.status
     7config.sub
     8configure
     9depcomp
     10install-sh
    111Makefile
    212Makefile.in
     13missing
     14mkinstalldirs
  • cpukit/score/cpu/sparc/ChangeLog

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/sparc/ChangeLog,v
    retrieving revision 1.78
    retrieving revision 1.35.2.9
    diff -u -r1.78 -r1.35.2.9
     
    1 2007-05-09      Ralf Corsépius <ralf.corsepius@rtems.org>
     12007-05-10      Joel Sherrill <joel.sherrill@OARcorp.com>
    22
    3         * rtems/score/cpu.h: Remove CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES.
    4 
    5 2007-04-17      Ralf Corsépius <ralf.corsepius@rtems.org>
    6 
    7         * cpu.c:
    8           Use Context_Control_fp* instead of void* for fp_contexts.
    9         * rtems/score/cpu.h:
    10           Use Context_Control_fp* instead of void* for fp_contexts.
    11           Eliminate evil casts.
    12 
    13 2006-11-17      Ralf Corsépius <ralf.corsepius@rtems.org>
    14 
    15         * rtems/score/types.h: Remove unsigned64, signed64.
     3        PR 1237/rtems
     4        * cpu.c, cpu_asm.S, rtems/score/cpu.h: Add logic to prevent stack creep
     5        when interrupts occur at a sufficient rate that the interrupted
     6        thread never gets to clean its stack. This patch ensures that an
     7        interrupted thread will not nest ISR dispatches on its stack.
    168
    1792006-11-14      Jiri Gaisler <jiri@gaisler.com>
    1810
    1911        * cpu_asm.S: Properly support synchronous traps.
    2012
    21 2006-01-16      Joel Sherrill <joel@OARcorp.com>
    22 
    23         * rtems/score/cpu.h: Part of a large patch to improve Doxygen output.
    24         As a side-effect, grammar and spelling errors were corrected, spacing
    25         errors were address, and some variable names were improved.
    26 
    27 2005-11-08      Ralf Corsepius <ralf.corsepius@rtems.org>
    28 
    29         * rtems/score/types.h: Eliminate unsigned16, unsigned32.
    30 
    31 2005-10-27      Ralf Corsepius <ralf.corsepius@rtems.org>
    32 
    33         * rtems/asm.h: Remove private version of CONCAT macros.
    34         Include <rtems/concat.h> instead.
    35 
    36 2005-02-08      Ralf Corsepius <ralf.corsepius@rtems.org>
    37 
    38         * Makefile.am: Split out preinstallation rules.
    39         * preinstall.am: New (Split out from Makefile.am).
    40 
    41 2005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
    42 
    43         PR 754/rtems
    44         * rtems/asm.h: New (relocated from .).
    45         * asm.h: Remove (moved to rtems/asm.h).
    46         * Makefile.am: Reflect changes above.
    47 
    48 2004-01-28      Ralf Corsepius <ralf.corsepiu@rtems.org>
    49 
    50         * asm.h, rtems/score/cpu.h, rtems/score/sparc.h,
    51         rtems/score/types.h: New header guards.
    52 
    53 2005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
    54 
    55         * rtems/score/types.h: Remove signed8, signed16, signed32,
    56         unsigned8, unsigned16, unsigned32.
    57 
    58 2005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
    59 
    60         * rtems/score/cpu.h: *_swap_u32( uint32_t ).
    61 
    62 2005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
    63 
    64         * rtems/score/types.h: #include <rtems/stdint.h>.
    65 
    66 2005-01-22      Ralf Corsepius <ralf.corsepius@rtems.org>
    67 
    68         * rtems/score/cpu.h: Fix broken #endif.
    69 
    70 2005-01-07      Ralf Corsepius <ralf.corsepius@rtems.org>
    71 
    72         * Makefile.am: Eliminate CFLAGS_OPTIMIZE_V.
    73 
    74 2005-01-01      Ralf Corsepius <ralf.corsepius@rtems.org>
    75 
    76         * Makefile.am: Remove build-variant support.
    77 
    78 2004-11-21      Ralf Corsepius <ralf.corsepius@rtems.org>
    79 
    80         * rtems/score/types.h: Use __rtems_score_types_h as preprocessor
    81         guard.
    82 
    83 2004-11-21      Ralf Corsepius <ralf.corsepius@rtems.org>
    84 
    85         * asm.h: Add doxygen preamble.
    86 
    87 2004-10-02      Ralf Corsepius <ralf_corsepius@rtems.org>
    88 
    89         * rtems/score/cpu.h: Add doxygen preamble.
    90         * rtems/score/sparc.h: Add doxygen preamble.
    91         * rtems/score/types.h: Add doxygen preamble.
     132006-09-07      Ken Peters <ken.peters@jpl.nasa.gov>
    9214
    93 2004-04-06      Ralf Corsepius <ralf_corsepius@rtems.org>
     15        PR 1173/rtems
     16        * rtems/score/cpu.h: Add missing comment characters on endif.
    9417
    95         * configure.ac: Remove (Merged into$(top_srcdir)/configure.ac).
    96         * Makefile.am: Don't include multilib.am.
    97         Reflect merging configure.ac into $(top_srcdir)/configure.ac.
    98 
    99 2004-04-01      Ralf Corsepius <ralf_corsepius@rtems.org>
    100 
    101         * Makefile.am: Install asm.h to $(includedir)/rtems.
    102 
    103 2004-04-01      Ralf Corsepius <ralf_corsepius@rtems.org>
    104 
    105         * cpu_asm.S: Include <rtems/asm.h> instead of <asm.h>.
    106 
    107 2004-03-30      Ralf Corsepius <ralf_corsepius@rtems.org>
    108 
    109         * cpu.c, rtems/score/cpu.h, rtems/score/sparc.h: Convert to using
    110         c99 fixed size types.
    111 
    112 2004-03-29      Ralf Corsepius <ralf_corsepius@rtems.org>
    113 
    114         * configure.ac: RTEMS_TOP([../../../..]).
     182005-10-05  Jiri Gaisler <jiri@gaisler.com>
     19            Edvin Catovic <edvin@gaisler.com>
     20            Konrad Eisele <konrad@gaisler.com>
     21
     22        PR 827/bsps
     23        * ChangeLog, cpu.c, cpu_asm.S, rtems/score/cpu.h: Portion of large
     24        update of SPARC BSPs. Includes addition of sis, leon2 and leon3 BSPs,
     25        deletion of leon BSP, addition of SMC91111 NIC driver and much more.
     26
     272004-06-16      Edvin Catovic <edvin@gaisler.com>
     28
     29        * cpu_asm.S: Added FP context initialization routine
     30        _CPU_Context_initialize_fp
     31        * cpu.c: Changed FP context initialization.
     32        * rtems/score/sparc.h: Defined SPARC_HAS_FPU to be 1 (Non-FP BSPs
     33        erc32nfp and leon1 are removed)
    11534
    116352004-02-26      Andreas Karlsson <andreas.karlsson@space.se>
    11736
     
    11938        * cpu_asm.S: Close window while restoring interrupted task state which
    12039        resulted in CWP corruption.
    12140
    122 2004-01-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    123 
    124         * configure.ac: Move RTEMS_TOP one subdir down.
    125 
    126 2004-01-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    127 
    128         * Makefile.am: Add PREINSTALL_DIRS.
    129 
    130 2004-01-14      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    131 
    132         * Makefile.am: Re-add dirstamps to PREINSTALL_FILES.
    133         Add PREINSTALL_FILES to CLEANFILES.
    134 
    135 2004-01-12      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    136 
    137         * configure.ac: Requires automake >= 1.8.1.
    138 
    139 2004-01-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    140 
    141         * Makefile.am: Include compile.am, again.
    142 
    143 2004-01-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    144 
    145         * Makefile.am: Convert to using automake compilation rules.
    146 
    147 2003-12-12      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    148 
    149         * Makefile.am: Use mkdir_p. Remove dirs from PREINSTALL_FILES.
    150 
    151 2003-12-12      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    152 
    153         * configure.ac: Require automake >= 1.8, autoconf >= 2.59.
    154 
    155 2003-12-01      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    156 
    157         * Makefile.am: Remove TMPINSTALL_FILES.
    158 
    159 2003-11-30      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    160 
    161         * Makefile.am: Add $(dirstamp) to preinstallation rules.
    162 
    163 2003-11-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    164 
    165         * Makefile.am: Don't use gmake rules for preinstallation.
    166 
    167 2003-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    168 
    169         * configure.ac: Remove RTEMS_CANONICAL_HOST.
    170 
    171 2003-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    172 
    173         * configure.ac: Remove RTEMS_CHECK_CPU.
    174 
    175412003-09-04      Joel Sherrill <joel@OARcorp.com>
    17642
    17743        * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/sparc.h,
  • cpukit/score/cpu/sparc/Makefile.am

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/sparc/Makefile.am,v
    retrieving revision 1.39
    retrieving revision 1.20
    diff -u -r1.39 -r1.20
     
    11##
    2 ## $Id: Makefile.am,v 1.39 2006/01/12 09:57:43 ralf Exp $
     2## $Id: Makefile.am,v 1.20 2002/12/11 17:08:30 ralf Exp $
    33##
    44
    5 include $(top_srcdir)/automake/compile.am
     5ACLOCAL_AMFLAGS = -I ../../../aclocal
    66
    7 include_rtemsdir = $(includedir)/rtems
    8 include_rtems_HEADERS = rtems/asm.h
     7include $(top_srcdir)/../../../automake/multilib.am
     8include $(top_srcdir)/../../../automake/compile.am
     9include $(top_srcdir)/../../../automake/lib.am
     10
     11$(PROJECT_INCLUDE)/%.h: %.h
     12        $(INSTALL_DATA) $< $@
     13
     14$(PROJECT_INCLUDE):
     15        $(mkinstalldirs) $@
     16
     17$(PROJECT_INCLUDE)/rtems:
     18        $(mkinstalldirs) $@
     19
     20$(PROJECT_INCLUDE)/rtems/score:
     21        $(mkinstalldirs) $@
     22
     23include_HEADERS= asm.h
     24PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%)
    925
    1026include_rtems_scoredir = $(includedir)/rtems/score
    11 include_rtems_score_HEADERS = rtems/score/sparc.h rtems/score/cpu.h \
     27include_rtems_score_HEADERS = \
     28    rtems/score/sparc.h \
     29    rtems/score/cpu.h \
    1230    rtems/score/types.h
     31PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \
     32    $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h)
     33
     34C_FILES = cpu.c
     35OBJS = $(C_FILES:%.c=$(ARCH)/%.$(OBJEXT))
     36
     37S_FILES = cpu_asm.S
     38OBJS += $(S_FILES:%.S=$(ARCH)/%.$(OBJEXT))
     39
     40LIB = $(ARCH)/libscorecpu.a
     41
     42$(LIB): $(OBJS)
     43        $(make-library)
     44
     45all-local: $(ARCH) $(PREINSTALL_FILES) $(LIB) \
     46    $(TMPINSTALL_FILES)
    1347
    14 noinst_LIBRARIES = libscorecpu.a
    15 libscorecpu_a_SOURCES = cpu.c cpu_asm.S
    16 libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS)
     48EXTRA_DIST = cpu.c cpu_asm.S
    1749
    18 include $(srcdir)/preinstall.am
    19 include $(top_srcdir)/automake/local.am
     50include $(top_srcdir)/../../../automake/local.am
  • cpukit/score/cpu/sparc/cpu.c

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/sparc/cpu.c,v
    retrieving revision 1.19
    retrieving revision 1.16.2.3
    diff -u -r1.19 -r1.16.2.3
     
    88 *  found in the file LICENSE in this distribution or at
    99 *  http://www.rtems.com/license/LICENSE.
    1010 *
    11  *  $Id: cpu.c,v 1.19 2007/04/17 04:51:28 ralf Exp $
     11 *  $Id: cpu.c,v 1.16.2.3 2007/05/10 18:41:42 joel Exp $
    1212 */
    1313
    1414#include <rtems/system.h>
     
    5353  void            (*thread_dispatch)      /* ignored on this CPU */
    5454)
    5555{
    56 #if (SPARC_HAS_FPU == 1)
    57   Context_Control_fp *pointer;
     56  void                  *pointer;
    5857
    5958  /*
    60    *  This seems to be the most appropriate way to obtain an initial
    61    *  FP context on the SPARC.  The NULL fp context is copied it to
     59   *  FP context is initialized.  The NULL fp context is copied it to
    6260   *  the task's FP context during Context_Initialize.
    6361   */
    6462
    6563  pointer = &_CPU_Null_fp_context;
    66   _CPU_Context_save_fp( &pointer );
    67 #endif
     64  _CPU_Context_initialize_fp(pointer);
    6865
    6966  /*
    7067   *  Grab our own copy of the user's CPU table.
    7168   */
    7269
    7370  _CPU_Table = *cpu_table;
     71
     72  /*
     73   *  Since no tasks have been created yet and no interrupts have occurred,
     74   *  there is no way that the currently executing thread can have an
     75   *  _ISR_Dispatch stack frame on its stack.
     76   */
     77  _CPU_ISR_Dispatch_disable = 0;
    7478}
    7579
    7680/*PAGE
     
    8387 *    returns the current interrupt level (PIL field of the PSR)
    8488 */
    8589 
    86 uint32_t  _CPU_ISR_Get_level( void )
     90unsigned32 _CPU_ISR_Get_level( void )
    8791{
    88   uint32_t  level;
     92  unsigned32 level;
    8993 
    9094  sparc_get_interrupt_level( level );
    9195 
     
    131135 */
    132136 
    133137void _CPU_ISR_install_raw_handler(
    134   uint32_t    vector,
     138  unsigned32  vector,
    135139  proc_ptr    new_handler,
    136140  proc_ptr   *old_handler
    137141)
    138142{
    139   uint32_t               real_vector;
     143  unsigned32             real_vector;
    140144  CPU_Trap_table_entry  *tbr;
    141145  CPU_Trap_table_entry  *slot;
    142   uint32_t               u32_tbr;
    143   uint32_t               u32_handler;
     146  unsigned32             u32_tbr;
     147  unsigned32             u32_handler;
    144148
    145149  /*
    146150   *  Get the "real" trap number for this vector ignoring the synchronous
     
    187191
    188192  *slot = _CPU_Trap_slot_template;
    189193
    190   u32_handler = (uint32_t  ) new_handler;
     194  u32_handler = (unsigned32) new_handler;
    191195
    192196  slot->mov_vector_l3 |= vector;
    193197  slot->sethi_of_handler_to_l4 |=
     
    218222 */
    219223
    220224void _CPU_ISR_install_vector(
    221   uint32_t    vector,
     225  unsigned32  vector,
    222226  proc_ptr    new_handler,
    223227  proc_ptr   *old_handler
    224228)
    225229{
    226    uint32_t  real_vector;
     230   unsigned32 real_vector;
    227231   proc_ptr   ignored;
    228232
    229233  /*
     
    273277
    274278void _CPU_Context_Initialize(
    275279  Context_Control  *the_context,
    276   uint32_t         *stack_base,
    277   uint32_t          size,
    278   uint32_t          new_level,
     280  unsigned32       *stack_base,
     281  unsigned32        size,
     282  unsigned32        new_level,
    279283  void             *entry_point,
    280284  boolean           is_fp
    281285)
    282286{
    283     uint32_t     stack_high;  /* highest "stack aligned" address */
    284     uint32_t     the_size;
    285     uint32_t     tmp_psr;
     287    unsigned32   stack_high;  /* highest "stack aligned" address */
     288    unsigned32   the_size;
     289    unsigned32   tmp_psr;
    286290 
    287291    /*
    288292     *  On CPUs with stacks which grow down (i.e. SPARC), we build the stack
    289293     *  based on the stack_high address. 
    290294     */
    291295 
    292     stack_high = ((uint32_t  )(stack_base) + size);
     296    stack_high = ((unsigned32)(stack_base) + size);
    293297    stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
    294298 
    295299    the_size = size & ~(CPU_STACK_ALIGNMENT - 1);
     
    298302     *  See the README in this directory for a diagram of the stack.
    299303     */
    300304 
    301     the_context->o7    = ((uint32_t  ) entry_point) - 8;
     305    the_context->o7    = ((unsigned32) entry_point) - 8;
    302306    the_context->o6_sp = stack_high - CPU_MINIMUM_STACK_FRAME_SIZE;
    303307    the_context->i6_fp = stack_high;
    304308
     
    316320    tmp_psr |= (new_level << 8) & SPARC_PSR_PIL_MASK;
    317321    tmp_psr &= ~SPARC_PSR_EF_MASK;      /* disabled by default */
    318322   
    319 #if (SPARC_HAS_FPU == 1)
    320323    /*
    321324     *  If this bit is not set, then a task gets a fault when it accesses
    322325     *  a floating point register.  This is a nice way to detect floating
     
    325328
    326329    if ( is_fp )
    327330      tmp_psr |= SPARC_PSR_EF_MASK;
    328 #endif
     331
    329332    the_context->psr = tmp_psr;
     333
     334  /*
     335   *  Since THIS thread is being created, there is no way that THIS
     336   *  thread can have an _ISR_Dispatch stack frame on its stack.
     337   */
     338    the_context->isr_dispatch_disable = 0;
    330339}
  • cpukit/score/cpu/sparc/cpu_asm.S

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/sparc/cpu_asm.S,v
    retrieving revision 1.12
    retrieving revision 1.8.2.5
    diff -u -r1.12 -r1.8.2.5
     
    1818 *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
    1919 *  European Space Agency.
    2020 *
    21  *  $Id: cpu_asm.S,v 1.12 2006/11/14 21:44:25 joel Exp $
     21 *  $Id: cpu_asm.S,v 1.8.2.5 2007/05/10 18:41:42 joel Exp $
    2222 */
    2323
    24 #include <rtems/asm.h>
     24#include <asm.h>
    2525
    26 #if (SPARC_HAS_FPU == 1)
     26/*
     27 *  void _CPU_Context_initialize_fp(
     28 *    void *fp_context_ptr
     29 *  )
     30 *
     31 *  This routine is responsible for initializing the FP context
     32 *  at *fp_context_ptr. All registers and FSR in the FP context
     33 *  are initailized to 0. 
     34 * 
     35 */
     36
     37        .align 4
     38        PUBLIC(_CPU_Context_initialize_fp)
     39SYM(_CPU_Context_initialize_fp):
     40        set     0, %l1
     41fpcontextinit: 
     42        std     %g0, [%o0]              ! write register fields of the FP context
     43        add     %l1, 1, %l1
     44        cmp     %l1, 16
     45        bne     fpcontextinit                                                   
     46        add     %o0, 8, %o0
     47        retl           
     48        st      %g0, [%o0]              ! write fsr field of the FP context
     49               
     50       
    2751
    2852/*
    2953 *  void _CPU_Context_save_fp(
     
    123147        ret
    124148        restore
    125149
    126 #endif /* SPARC_HAS_FPU */
    127 
    128150/*
    129151 *  void _CPU_Context_switch(
    130152 *    Context_Control  *run,
     
    143165        std     %g4, [%o0 + G4_OFFSET]
    144166        std     %g6, [%o0 + G6_OFFSET]
    145167
     168        ! load the address of the ISR stack nesting prevention flag
     169        sethi    %hi(SYM(_CPU_ISR_Dispatch_disable)), %g2
     170        ld       [%g2 + %lo(SYM(_CPU_ISR_Dispatch_disable))], %g2
     171        ! save it a bit later so we do not waste a couple of cycles
     172
    146173        std     %l0, [%o0 + L0_OFFSET]       ! save the local registers
    147174        std     %l2, [%o0 + L2_OFFSET]
    148175        std     %l4, [%o0 + L4_OFFSET]
    149176        std     %l6, [%o0 + L6_OFFSET]
    150177
     178        ! Now actually save ISR stack nesting prevention flag
     179        st       %g2, [%o0 + ISR_DISPATCH_DISABLE_STACK_OFFSET]
     180
    151181        std     %i0, [%o0 + I0_OFFSET]       ! save the input registers
    152182        std     %i2, [%o0 + I2_OFFSET]
    153183        std     %i4, [%o0 + I4_OFFSET]
     
    270300        ldd     [%o1 + G4_OFFSET], %g4
    271301        ldd     [%o1 + G6_OFFSET], %g6
    272302
     303        ! Load thread specific ISR dispatch prevention flag
     304        ld      [%o1 + ISR_DISPATCH_DISABLE_STACK_OFFSET], %o2
     305        sethi    %hi(SYM(_CPU_ISR_Dispatch_disable)), %o3
     306        ! Store it to memory later to use the cycles
     307
    273308        ldd     [%o1 + L0_OFFSET], %l0        ! restore the local registers
    274309        ldd     [%o1 + L2_OFFSET], %l2
    275310        ldd     [%o1 + L4_OFFSET], %l4
    276311        ldd     [%o1 + L6_OFFSET], %l6
    277312
     313        ! Now restore thread specific ISR dispatch prevention flag
     314        st       %o2,[%o3 + %lo(SYM(_CPU_ISR_Dispatch_disable))]
     315
    278316        ldd     [%o1 + I0_OFFSET], %i0        ! restore the output registers
    279317        ldd     [%o1 + I2_OFFSET], %i2
    280318        ldd     [%o1 + I4_OFFSET], %i4
     
    633671
    634672        orcc     %l6, %g0, %g0   ! Is dispatching disabled?
    635673        bnz      simple_return   ! Yes, then do a "simple" exit
    636         nop                      ! delay slot
     674        ! NOTE: Use the delay slot
     675        sethi    %hi(SYM(_CPU_ISR_Dispatch_disable)), %l6
     676
     677        ! Are we dispatching from a previous ISR in the interrupted thread?
     678        ld       [%l6 + %lo(SYM(_CPU_ISR_Dispatch_disable))], %l7
     679        orcc     %l7, %g0, %g0   ! Is this thread already doing an ISR?
     680        bnz      simple_return   ! Yes, then do a "simple" exit
     681        ! NOTE: Use the delay slot
     682        sethi    %hi(SYM(_Context_Switch_necessary)), %l4
     683       
    637684
    638685        /*
    639686         *  If a context switch is necessary, then do fudge stack to
    640687         *  return to the interrupt dispatcher.
    641688         */
    642689
    643         sethi    %hi(SYM(_Context_Switch_necessary)), %l4
    644690        ld       [%l4 + %lo(SYM(_Context_Switch_necessary))], %l5
    645691
    646692        orcc     %l5, %g0, %g0   ! Is thread switch necessary?
    647693        bnz      SYM(_ISR_Dispatch) ! yes, then invoke the dispatcher
    648         nop                      ! delay slot
     694        ! NOTE: Use the delay slot
     695        sethi    %hi(SYM(_ISR_Signals_to_thread_executing)), %l6
    649696
    650697        /*
    651698         *  Finally, check to see if signals were sent to the currently
    652699         *  executing task.  If so, we need to invoke the interrupt dispatcher.
    653700         */
    654701
    655         sethi    %hi(SYM(_ISR_Signals_to_thread_executing)), %l6
    656702        ld       [%l6 + %lo(SYM(_ISR_Signals_to_thread_executing))], %l7
    657703
    658704        orcc     %l7, %g0, %g0   ! Were signals sent to the currently
     
    669715
    670716        PUBLIC(_ISR_Dispatch)
    671717SYM(_ISR_Dispatch):
     718        ! Set ISR dispatch nesting prevention flag
     719        mov      1,%l6
     720        sethi    %hi(SYM(_CPU_ISR_Dispatch_disable)), %l5
     721        st       %l6,[%l5 + %lo(SYM(_CPU_ISR_Dispatch_disable))]
    672722
    673723        /*
    674724         *  The following subtract should get us back on the interrupted
     
    684734        nop
    685735        nop
    686736        nop
    687 
     737isr_dispatch:
    688738        call    SYM(_Thread_Dispatch), 0
    689739        nop
    690740
     
    700750        ta      0                               ! syscall (disable interrupts)
    701751
    702752        /*
     753         *  While we had ISR dispatching disabled in this thread,
     754         *  did we miss anything.  If so, then we need to do another
     755         *  _Thread_Dispatch before leaving this ISR Dispatch context.
     756         */
     757
     758        sethi    %hi(SYM(_Context_Switch_necessary)), %l4
     759        ld       [%l4 + %lo(SYM(_Context_Switch_necessary))], %l5
     760
     761        ! NOTE: Use some of delay slot to start loading this
     762        sethi    %hi(SYM(_ISR_Signals_to_thread_executing)), %l6
     763        ld       [%l6 + %lo(SYM(_ISR_Signals_to_thread_executing))], %l7
     764
     765        orcc     %l5, %g0, %g0   ! Is thread switch necessary?
     766        bnz      dispatchAgain   ! yes, then invoke the dispatcher AGAIN
     767        ! NOTE: Use the delay slot to catch the orcc below
     768
     769        /*
     770         *  Finally, check to see if signals were sent to the currently
     771         *  executing task.  If so, we need to invoke the interrupt dispatcher.
     772         */
     773
     774        ! NOTE: Delay slots above were used to perform the load AND
     775        !       this orcc falls into the delay slot for bnz above
     776        orcc     %l7, %g0, %g0   ! Were signals sent to the currently
     777                                 !   executing thread?
     778        bz       allow_nest_again ! No, then clear out and return
     779        ! NOTE: use the delay slot from the bz to load 3 into %g1
     780
     781        ! Yes, then invoke the dispatcher
     782dispatchAgain:
     783        mov     3,%g1                           ! syscall (enable interrupts)
     784        ta      0                               ! syscall (enable interrupts)
     785        ba      isr_dispatch
     786        nop
     787
     788allow_nest_again:
     789
     790        ! Zero out ISR stack nesting prevention flag
     791        sethi    %hi(SYM(_CPU_ISR_Dispatch_disable)), %l5
     792        st       %g0,[%l5 + %lo(SYM(_CPU_ISR_Dispatch_disable))]
     793
     794        /*
    703795         *  The CWP in place at this point may be different from
    704796         *  that which was in effect at the beginning of the ISR if we
    705797         *  have been context switched between the beginning of this invocation
  • cpukit/score/cpu/sparc/rtems/score/cpu.h

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/sparc/rtems/score/cpu.h,v
    retrieving revision 1.22
    retrieving revision 1.13.2.4
    diff -u -r1.22 -r1.13.2.4
     
    1 /**
    2  * @file rtems/score/cpu.h
    3  */
    4 
    5 /*
     1/*  cpu.h
     2 *
    63 *  This include file contains information pertaining to the port of
    74 *  the executive to the SPARC processor.
    85 *
    9  *  COPYRIGHT (c) 1989-2006.
     6 *  COPYRIGHT (c) 1989-1999.
    107 *  On-Line Applications Research Corporation (OAR).
    118 *
    129 *  The license and distribution terms for this file may be
    1310 *  found in the file LICENSE in this distribution or at
    1411 *  http://www.rtems.com/license/LICENSE.
    1512 *
    16  *  $Id: cpu.h,v 1.22 2007/05/09 15:28:49 ralf Exp $
     13 *  $Id: cpu.h,v 1.13.2.4 2007/05/10 18:41:42 joel Exp $
    1714 */
    1815
    19 #ifndef _RTEMS_SCORE_CPU_H
    20 #define _RTEMS_SCORE_CPU_H
     16#ifndef __CPU_h
     17#define __CPU_h
    2118
    2219#ifdef __cplusplus
    2320extern "C" {
     
    157154 *  not provide one.
    158155 */
    159156
    160 #define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
     157#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
    161158
    162159/*
    163160 *  Does the stack grow up (toward higher addresses) or down
     
    189186 *  routines are handled.
    190187 */
    191188
     189#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
    192190#define CPU_BIG_ENDIAN                           TRUE
    193191#define CPU_LITTLE_ENDIAN                        FALSE
    194192
     
    212210#ifndef ASM
    213211
    214212typedef struct {
    215   uint32_t    l0;
    216   uint32_t    l1;
    217   uint32_t    l2;
    218   uint32_t    l3;
    219   uint32_t    l4;
    220   uint32_t    l5;
    221   uint32_t    l6;
    222   uint32_t    l7;
    223   uint32_t    i0;
    224   uint32_t    i1;
    225   uint32_t    i2;
    226   uint32_t    i3;
    227   uint32_t    i4;
    228   uint32_t    i5;
    229   uint32_t    i6_fp;
    230   uint32_t    i7;
     213  unsigned32  l0;
     214  unsigned32  l1;
     215  unsigned32  l2;
     216  unsigned32  l3;
     217  unsigned32  l4;
     218  unsigned32  l5;
     219  unsigned32  l6;
     220  unsigned32  l7;
     221  unsigned32  i0;
     222  unsigned32  i1;
     223  unsigned32  i2;
     224  unsigned32  i3;
     225  unsigned32  i4;
     226  unsigned32  i5;
     227  unsigned32  i6_fp;
     228  unsigned32  i7;
    231229  void       *structure_return_address;
    232230  /*
    233231   *  The following are for the callee to save the register arguments in
    234232   *  should this be necessary.
    235233   */
    236   uint32_t    saved_arg0;
    237   uint32_t    saved_arg1;
    238   uint32_t    saved_arg2;
    239   uint32_t    saved_arg3;
    240   uint32_t    saved_arg4;
    241   uint32_t    saved_arg5;
    242   uint32_t    pad0;
     234  unsigned32  saved_arg0;
     235  unsigned32  saved_arg1;
     236  unsigned32  saved_arg2;
     237  unsigned32  saved_arg3;
     238  unsigned32  saved_arg4;
     239  unsigned32  saved_arg5;
     240  unsigned32  pad0;
    243241}  CPU_Minimum_stack_frame;
    244242
    245243#endif /* ASM */
     
    298296     *  and stores safely in the context switch.
    299297     */
    300298    double     g0_g1;
    301     uint32_t  g2;
    302     uint32_t  g3;
    303     uint32_t  g4;
    304     uint32_t  g5;
    305     uint32_t  g6;
    306     uint32_t  g7;
    307 
    308     uint32_t  l0;
    309     uint32_t  l1;
    310     uint32_t  l2;
    311     uint32_t  l3;
    312     uint32_t  l4;
    313     uint32_t  l5;
    314     uint32_t  l6;
    315     uint32_t  l7;
    316 
    317     uint32_t  i0;
    318     uint32_t  i1;
    319     uint32_t  i2;
    320     uint32_t  i3;
    321     uint32_t  i4;
    322     uint32_t  i5;
    323     uint32_t  i6_fp;
    324     uint32_t  i7;
    325 
    326     uint32_t  o0;
    327     uint32_t  o1;
    328     uint32_t  o2;
    329     uint32_t  o3;
    330     uint32_t  o4;
    331     uint32_t  o5;
    332     uint32_t  o6_sp;
    333     uint32_t  o7;
     299    unsigned32 g2;
     300    unsigned32 g3;
     301    unsigned32 g4;
     302    unsigned32 g5;
     303    unsigned32 g6;
     304    unsigned32 g7;
     305
     306    unsigned32 l0;
     307    unsigned32 l1;
     308    unsigned32 l2;
     309    unsigned32 l3;
     310    unsigned32 l4;
     311    unsigned32 l5;
     312    unsigned32 l6;
     313    unsigned32 l7;
     314
     315    unsigned32 i0;
     316    unsigned32 i1;
     317    unsigned32 i2;
     318    unsigned32 i3;
     319    unsigned32 i4;
     320    unsigned32 i5;
     321    unsigned32 i6_fp;
     322    unsigned32 i7;
     323
     324    unsigned32 o0;
     325    unsigned32 o1;
     326    unsigned32 o2;
     327    unsigned32 o3;
     328    unsigned32 o4;
     329    unsigned32 o5;
     330    unsigned32 o6_sp;
     331    unsigned32 o7;
    334332
    335     uint32_t   psr;
     333    unsigned32 psr;
     334    unsigned32 isr_dispatch_disable;
    336335} Context_Control;
    337336
    338337#endif /* ASM */
     
    378377#define O7_OFFSET    0x7C
    379378
    380379#define PSR_OFFSET   0x80
     380#define ISR_DISPATCH_DISABLE_STACK_OFFSET 0x84
    381381
    382 #define CONTEXT_CONTROL_SIZE 0x84
     382#define CONTEXT_CONTROL_SIZE 0x88
    383383
    384384/*
    385385 *  The floating point context area.
     
    404404    double      f26_f27;
    405405    double      f28_f29;
    406406    double      f30_f31;
    407     uint32_t    fsr;
     407    unsigned32  fsr;
    408408} Context_Control_fp;
    409409
    410410#endif /* ASM */
     
    444444
    445445typedef struct {
    446446  CPU_Minimum_stack_frame  Stack_frame;
    447   uint32_t                 psr;
    448   uint32_t                 pc;
    449   uint32_t                 npc;
    450   uint32_t                 g1;
    451   uint32_t                 g2;
    452   uint32_t                 g3;
    453   uint32_t                 g4;
    454   uint32_t                 g5;
    455   uint32_t                 g6;
    456   uint32_t                 g7;
    457   uint32_t                 i0;
    458   uint32_t                 i1;
    459   uint32_t                 i2;
    460   uint32_t                 i3;
    461   uint32_t                 i4;
    462   uint32_t                 i5;
    463   uint32_t                 i6_fp;
    464   uint32_t                 i7;
    465   uint32_t                 y;
    466   uint32_t                 tpc;
     447  unsigned32               psr;
     448  unsigned32               pc;
     449  unsigned32               npc;
     450  unsigned32               g1;
     451  unsigned32               g2;
     452  unsigned32               g3;
     453  unsigned32               g4;
     454  unsigned32               g5;
     455  unsigned32               g6;
     456  unsigned32               g7;
     457  unsigned32               i0;
     458  unsigned32               i1;
     459  unsigned32               i2;
     460  unsigned32               i3;
     461  unsigned32               i4;
     462  unsigned32               i5;
     463  unsigned32               i6_fp;
     464  unsigned32               i7;
     465  unsigned32               y;
     466  unsigned32               tpc;
    467467} CPU_Interrupt_frame;
    468468
    469469#endif /* ASM */
     
    508508  void       (*postdriver_hook)( void );
    509509  void       (*idle_task)( void );
    510510  boolean      do_zero_of_workspace;
    511   uint32_t     idle_task_stack_size;
    512   uint32_t     interrupt_stack_size;
    513   uint32_t     extra_mpci_receive_server_stack;
    514   void *     (*stack_allocate_hook)( uint32_t  );
     511  unsigned32   idle_task_stack_size;
     512  unsigned32   interrupt_stack_size;
     513  unsigned32   extra_mpci_receive_server_stack;
     514  void *     (*stack_allocate_hook)( unsigned32 );
    515515  void       (*stack_free_hook)( void* );
    516516  /* end of fields required on all CPUs */
    517517
     
    553553SCORE_EXTERN void *_CPU_Interrupt_stack_high;
    554554
    555555/*
     556 *  This flag is context switched with each thread.  It indicates
     557 *  that THIS thread has an _ISR_Dispatch stack frame on its stack.
     558 *  By using this flag, we can avoid nesting more interrupt dispatching
     559 *  attempts on a previously interrupted thread's stack.
     560 */
     561
     562SCORE_EXTERN volatile uint32_t _CPU_ISR_Dispatch_disable;
     563
     564/*
    556565 *  The following type defines an entry in the SPARC's trap table.
    557566 *
    558567 *  NOTE: The instructions chosen are RTEMS dependent although one is
     
    562571 */
    563572 
    564573typedef struct {
    565   uint32_t     mov_psr_l0;                     /* mov   %psr, %l0           */
    566   uint32_t     sethi_of_handler_to_l4;         /* sethi %hi(_handler), %l4  */
    567   uint32_t     jmp_to_low_of_handler_plus_l4;  /* jmp   %l4 + %lo(_handler) */
    568   uint32_t     mov_vector_l3;                  /* mov   _vector, %l3        */
     574  unsigned32   mov_psr_l0;                     /* mov   %psr, %l0           */
     575  unsigned32   sethi_of_handler_to_l4;         /* sethi %hi(_handler), %l4  */
     576  unsigned32   jmp_to_low_of_handler_plus_l4;  /* jmp   %l4 + %lo(_handler) */
     577  unsigned32   mov_vector_l3;                  /* mov   _vector, %l3        */
    569578} CPU_Trap_table_entry;
    570579 
    571580/*
     
    637646#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
    638647
    639648/*
    640  *  Should be large enough to run all tests.  This ensures
     649 *  Should be large enough to run all tests.  This insures
    641650 *  that a "reasonable" small application should not have any problems.
    642651 *
    643652 *  This appears to be a fairly generous number for the SPARC since
     
    750759#define _CPU_ISR_Set_level( _newlevel ) \
    751760   sparc_enable_interrupts( _newlevel << 8)
    752761 
    753 uint32_t  _CPU_ISR_Get_level( void );
     762unsigned32 _CPU_ISR_Get_level( void );
    754763 
    755764/* end of ISR handler macros */
    756765
     
    772781
    773782void _CPU_Context_Initialize(
    774783  Context_Control  *the_context,
    775   uint32_t         *stack_base,
    776   uint32_t          size,
    777   uint32_t          new_level,
     784  unsigned32       *stack_base,
     785  unsigned32        size,
     786  unsigned32        new_level,
    778787  void             *entry_point,
    779788  boolean           is_fp
    780789);
     
    810819
    811820#define _CPU_Context_Initialize_fp( _destination ) \
    812821  do { \
    813    *(*(_destination)) = _CPU_Null_fp_context; \
     822   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
    814823  } while (0)
    815824
    816825/* end of Context handler macros */
     
    825834
    826835#define _CPU_Fatal_halt( _error ) \
    827836  do { \
    828     uint32_t  level; \
     837    unsigned32 level; \
    829838    \
    830839    level = sparc_disable_interrupts(); \
    831840    asm volatile ( "mov  %0, %%g1 " : "=r" (level) : "0" (level) ); \
     
    884893 */
    885894 
    886895void _CPU_ISR_install_raw_handler(
    887   uint32_t    vector,
     896  unsigned32  vector,
    888897  proc_ptr    new_handler,
    889898  proc_ptr   *old_handler
    890899);
     
    896905 */
    897906
    898907void _CPU_ISR_install_vector(
    899   uint32_t    vector,
     908  unsigned32  vector,
    900909  proc_ptr    new_handler,
    901910  proc_ptr   *old_handler
    902911);
     
    943952 */
    944953
    945954void _CPU_Context_save_fp(
    946   Context_Control_fp **fp_context_ptr
     955  void **fp_context_ptr
    947956);
    948957
    949958/*
     
    953962 */
    954963
    955964void _CPU_Context_restore_fp(
    956   Context_Control_fp **fp_context_ptr
     965  void **fp_context_ptr
    957966);
    958967
    959968/*
     
    975984 *  following code at optimization level four (i.e. -O4).
    976985 */
    977986 
    978 static inline uint32_t CPU_swap_u32(
    979   uint32_t value
     987static inline unsigned int CPU_swap_u32(
     988  unsigned int value
    980989)
    981990{
    982   uint32_t  byte1, byte2, byte3, byte4, swapped;
     991  unsigned32 byte1, byte2, byte3, byte4, swapped;
    983992 
    984993  byte4 = (value >> 24) & 0xff;
    985994  byte3 = (value >> 16) & 0xff;
  • cpukit/score/cpu/sparc/rtems/score/sparc.h

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/sparc/rtems/score/sparc.h,v
    retrieving revision 1.12
    retrieving revision 1.6.4.1
    diff -u -r1.12 -r1.6.4.1
     
    1 /**
    2  * @file rtems/score/sparc.h
    3  */
    4 
    5 /*
     1/*  sparc.h
     2 *
    63 *  This include file contains information pertaining to the SPARC
    74 *  processor family.
    85 *
     
    1310 *  found in the file LICENSE in this distribution or at
    1411 *  http://www.rtems.com/license/LICENSE.
    1512 *
    16  *  $Id: sparc.h,v 1.12 2005/02/04 05:40:52 ralf Exp $
     13 *  $Id: sparc.h,v 1.6.4.1 2003/09/04 18:47:40 joel Exp $
    1714 */
    1815
    19 #ifndef _RTEMS_SCORE_SPARC_H
    20 #define _RTEMS_SCORE_SPARC_H
     16#ifndef _INCLUDE_SPARC_h
     17#define _INCLUDE_SPARC_h
    2118
    2219#ifdef __cplusplus
    2320extern "C" {
     
    231228 
    232229#define sparc_flash_interrupts( _level ) \
    233230  do { \
    234     register uint32_t  _ignored = 0; \
     231    register unsigned32 _ignored = 0; \
    235232    \
    236233    sparc_enable_interrupts( (_level) ); \
    237234    sparc_disable_interrupts( _ignored ); \
     
    240237/*
    241238#define sparc_set_interrupt_level( _new_level ) \
    242239  do { \
    243     register uint32_t  _new_psr_level = 0; \
     240    register unsigned32 _new_psr_level = 0; \
    244241    \
    245242    sparc_get_psr( _new_psr_level ); \
    246243    _new_psr_level &= ~SPARC_PSR_PIL_MASK; \
     
    252249
    253250#define sparc_get_interrupt_level( _level ) \
    254251  do { \
    255     register uint32_t  _psr_level = 0; \
     252    register unsigned32 _psr_level = 0; \
    256253    \
    257254    sparc_get_psr( _psr_level ); \
    258255    (_level) = \
     
    265262}
    266263#endif
    267264
    268 #endif /* _RTEMS_SCORE_SPARC_H */
     265#endif /* ! _INCLUDE_SPARC_h */
     266/* end of include file */
  • cpukit/score/cpu/sparc/rtems/score/types.h

    RCS file: /usr1/CVS/rtems/cpukit/score/cpu/sparc/rtems/score/types.h,v
    retrieving revision 1.12
    retrieving revision 1.3.2.1
    diff -u -r1.12 -r1.3.2.1
     
    1 /**
    2  * @file rtems/score/types.h
    3  */
    4 
    5 /*
     1/*  sparctypes.h
     2 *
    63 *  This include file contains type definitions pertaining to the
    74 *  SPARC processor family.
    85 *
     
    1310 *  found in the file LICENSE in this distribution or at
    1411 *  http://www.rtems.com/license/LICENSE.
    1512 *
    16  *  $Id: types.h,v 1.12 2006/11/17 05:58:03 ralf Exp $
     13 *  $Id: types.h,v 1.3.2.1 2003/09/04 18:47:40 joel Exp $
    1714 */
    1815
    19 #ifndef _RTEMS_SCORE_TYPES_H
    20 #define _RTEMS_SCORE_TYPES_H
     16#ifndef __SPARC_TYPES_h
     17#define __SPARC_TYPES_h
    2118
    2219#ifndef ASM
    2320
    24 #include <rtems/stdint.h>
    25 
    2621#ifdef __cplusplus
    2722extern "C" {
    2823#endif
     
    3126 *  This section defines the basic types for this processor.
    3227 */
    3328
    34 typedef uint16_t         Priority_Bit_map_control;
     29typedef unsigned char      unsigned8;            /* unsigned 8-bit  integer */
     30typedef unsigned short     unsigned16;           /* unsigned 16-bit integer */
     31typedef unsigned int       unsigned32;           /* unsigned 32-bit integer */
     32typedef unsigned long long unsigned64;           /* unsigned 64-bit integer */
     33
     34typedef unsigned16         Priority_Bit_map_control;
     35
     36typedef signed char        signed8;              /* 8-bit  signed integer */
     37typedef signed short       signed16;             /* 16-bit signed integer */
     38typedef signed int         signed32;             /* 32-bit signed integer */
     39typedef signed long long   signed64;             /* 64 bit signed integer */
    3540
    36 typedef uint32_t         boolean;              /* Boolean value   */
     41typedef unsigned32         boolean;              /* Boolean value   */
    3742
    3843typedef float              single_precision;     /* single precision float */
    3944typedef double             double_precision;     /* double precision float */
     
    4853#endif  /* !ASM */
    4954
    5055#endif
     56/* end of include file */