Stack is not properly aligned during interrupt processing

[Sebastian Huber]

On a public boundary, the stack pointer must be aligned on an 8-byte boundary. However, it may temporarily be only aligned on a 4-byte boundary. The interrupt handling code must ensure that the stack pointer is properly aligned before it calls a function. See also:

​https://developer.arm.com/documentation/den0013/d/Interrupt-Handling/External-interrupt-requests/Nested-interrupt-handling

[Sebastian Huber <sebastian.huber@…>]

In 2d1ea1ab/rtems:

arm: Use push/pop instructions for readability

Update #4579.

[Sebastian Huber <sebastian.huber@…>]

In 0290e44/rtems:

arm: Rework per-CPU control in interrupt handling

Use volatile register r0 for the per-CPU control of the current
processor instead of the non-volatile register r7. This enables the use
of r7 in a follow up patch. Do the interrupt handling in ARM mode.

Update #4579.

[Sebastian Huber <sebastian.huber@…>]

In 41a1903d/rtems:

arm: Avoid duplicate move from CPSR

Update #4579.

[Sebastian Huber <sebastian.huber@…>]

In 84ba194/rtems:

arm: Fix stack alignment during interrupt handling

On a public interface, the stack pointer must be aligned on an 8-byte
boundary. However, it may temporarily be only aligned on a 4-byte
boundary. The interrupt handling code must ensure that the stack
pointer is properly aligned before it calls a function. See also:

​https://developer.arm.com/documentation/den0013/d/Interrupt-Handling/External-interrupt-requests/Nested-interrupt-handling

Update #4579.

[Sebastian Huber]

A test case is missing.

[Chris Johns]

If this is to be fixed for 6.1 please move it to a suitable milestone.