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Opened on 03/21/21 at 09:02:28
Last modified on 03/21/21 at 15:13:24
#4351 assigned enhancement
about mips mutil-core
| Reported by: | only_yipie | Owned by: | Needs Funding |
|---|---|---|---|
| Priority: | normal | Milestone: | Indefinite |
| Component: | arch/mips | Version: | 4.11 |
| Severity: | normal | Keywords: | mips mutil core |
| Cc: | Blocked By: | ||
| Blocking: |
Description (last modified by Joel Sherrill)
rtems MIPS architecture does not provide multi-core support.
Change History (3)
comment:1 Changed on 03/21/21 at 15:08:06 by Joel Sherrill
| Component: | admin → arch/mips |
|---|---|
| Description: | modified (diff) |
| Milestone: | 5.1 → Indefinite |
| Type: | defect → enhancement |
comment:2 Changed on 03/21/21 at 15:13:00 by Joel Sherrill
comment:3 Changed on 03/21/21 at 15:13:24 by Joel Sherrill
| Owner: | set to Needs Funding |
|---|---|
| Status: | new → assigned |
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Yes. The MIPS is a likely candidate for SMP support. I changed the attributes of this ticket to make them more correct. This is unlikely to happen unless someone volunteers or pays a core developer.
A first and useful step would be to figure out if the MIPS Malta BSP can support multicore on Qemu. Otherwise, AFAIK this effort will require a new BSP also for an SMP capable platform. Perhaps there is a qemu target other than the Malta which is useful for this. I just don't know and some research is needed to make a project plan.