Ticket #3242: gcc-sparc-ticket-3242-v2.patch

gcc/config/sparc/sparc.c

@@ -914 +914 @@
   return NULL_RTX;
 }
 
+/* True if any of INSN's source register(s) is REG.  */
+
+static bool
+insn_uses_reg_p (rtx_insn *insn, unsigned int reg)
+{
+  extract_insn (insn);
+  return ((REG_P (recog_data.operand[1])
+           && REGNO (recog_data.operand[1]) == reg)
+          || (recog_data.n_operands == 3
+              && REG_P (recog_data.operand[2])
+              && REGNO (recog_data.operand[2]) == reg));
+}
+
+/* True if INSN is a floating-point division or square-root.  */
+
+static bool
+div_sqrt_insn_p (rtx_insn *insn)
+{
+  if (GET_CODE (PATTERN (insn)) != SET)
+    return false;
+
+  switch (get_attr_type (insn))
+    {
+    case TYPE_FPDIVS:
+    case TYPE_FPSQRTS:
+    case TYPE_FPDIVD:
+    case TYPE_FPSQRTD:
+      return true;
+    default:
+      return false;
+    }
+}
+
+/* True if INSN is a floating-point instruction.  */
+
+static bool
+fpop_insn_p (rtx_insn *insn)
+{
+  if (GET_CODE (PATTERN (insn)) != SET)
+    return false;
+
+  switch (get_attr_type (insn))
+    {
+    case TYPE_FPMOVE:
+    case TYPE_FPCMOVE:
+    case TYPE_FP:
+    case TYPE_FPCMP:
+    case TYPE_FPMUL:
+    case TYPE_FPDIVS:
+    case TYPE_FPSQRTS:
+    case TYPE_FPDIVD:
+    case TYPE_FPSQRTD:
+      return true;
+    default:
+      return false;
+    }
+}
+
+/* True if INSN is an atomic instruction.  */
+
+static bool
+atomic_insn_for_leon3_p (rtx_insn *insn)
+{
+  switch (INSN_CODE (insn))
+    {
+    case CODE_FOR_swapsi:
+    case CODE_FOR_ldstub:
+    case CODE_FOR_atomic_compare_and_swap_leon3_1:
+      return true;
+    default:
+      return false;
+    }
+}
+
 /* We use a machine specific pass to enable workarounds for errata.
 
    We need to have the (essentially) final form of the insn stream in order
@@ -939 +1013 @@
     {
       bool insert_nop = false;
       rtx set;
+      rtx_insn *jump;
+      rtx_sequence *seq;
 
       /* Look into the instruction in a delay slot.  */
-      if (NONJUMP_INSN_P (insn))
-        if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (PATTERN (insn)))
+      if (NONJUMP_INSN_P (insn)
+          && (seq = dyn_cast <rtx_sequence *> (PATTERN (insn))))
+        {
+          jump = seq->insn (0);
           insn = seq->insn (1);
+        }
+      else if (JUMP_P (insn))
+        jump = insn;
+      else
+        jump = NULL;
+
+      /* Place a NOP at the branch target of an integer branch if it is a
+         floating-point operation or a floating-point branch.  */
+      if (sparc_fix_gr712rc
+          && jump
+          && jump_to_label_p (jump)
+          && get_attr_branch_type (jump) == BRANCH_TYPE_ICC)
+        {
+          rtx_insn *target = next_active_insn (JUMP_LABEL_AS_INSN (jump));
+          if (target
+              && (fpop_insn_p (target)
+                  || (JUMP_P (target)
+                      && get_attr_branch_type (target) == BRANCH_TYPE_FCC)))
+            emit_insn_before (gen_nop (), target);
+        }
+
+      /* Insert a NOP between load instruction and atomic instruction.  Insert
+         a NOP at branch target if there is a load in delay slot and an atomic
+         instruction at branch target.  */
+      if (sparc_fix_ut700
+          && NONJUMP_INSN_P (insn)
+          && (set = single_set (insn)) != NULL_RTX
+          && mem_ref (SET_SRC (set))
+          && REG_P (SET_DEST (set)))
+        {
+          if (jump && jump_to_label_p (jump))
+            {
+              rtx_insn *target = next_active_insn (JUMP_LABEL_AS_INSN (jump));
+              if (target && atomic_insn_for_leon3_p (target))
+                emit_insn_before (gen_nop (), target);
+            }
+
+          next = next_active_insn (insn);
+          if (!next)
+            break;
+
+          if (atomic_insn_for_leon3_p (next))
+            insert_nop = true;
+        }
+
+      /* Look for a sequence that starts with a fdiv or fsqrt instruction and
+         ends with another fdiv or fsqrt instruction with no dependencies on
+         the former, along with an appropriate pattern in between.  */
+      if (sparc_fix_lost_divsqrt
+          && NONJUMP_INSN_P (insn)
+          && div_sqrt_insn_p (insn))
+        {
+          int i;
+          int fp_found = 0;
+          rtx_insn *after;
+
+          const unsigned int dest_reg = REGNO (SET_DEST (single_set (insn)));
+
+          next = next_active_insn (insn);
+          if (!next)
+            break;
+
+          for (after = next, i = 0; i < 4; i++)
+            {
+              /* Count floating-point operations.  */
+              if (i != 3 && fpop_insn_p (after))
+                {
+                  /* If the insn uses the destination register of
+                     the div/sqrt, then it cannot be problematic.  */
+                  if (insn_uses_reg_p (after, dest_reg))
+                    break;
+                  fp_found++;
+                }
+
+              /* Count floating-point loads.  */
+              if (i != 3
+                  && (set = single_set (after)) != NULL_RTX
+                  && REG_P (SET_DEST (set))
+                  && REGNO (SET_DEST (set)) > 31)
+                {
+                  /* If the insn uses the destination register of
+                     the div/sqrt, then it cannot be problematic.  */
+                  if (REGNO (SET_DEST (set)) == dest_reg)
+                    break;
+                  fp_found++;
+                }
+
+              /* Check if this is a problematic sequence.  */
+              if (i > 1
+                  && fp_found >= 2
+                  && div_sqrt_insn_p (after))
+                {
+                  /* If this is the short version of the problematic
+                     sequence we add two NOPs in a row to also prevent
+                     the long version.  */
+                  if (i == 2)
+                    emit_insn_before (gen_nop (), next);
+                  insert_nop = true;
+                  break;
+                }
+
+              /* No need to scan past a second div/sqrt.  */
+              if (div_sqrt_insn_p (after))
+                break;
+
+              /* Insert NOP before branch.  */
+              if (i < 3
+                  && (!NONJUMP_INSN_P (after)
+                      || GET_CODE (PATTERN (after)) == SEQUENCE))
+                {
+                  insert_nop = true;
+                  break;
+                }
+
+              after = next_active_insn (after);
+              if (!after)
+                break;
+            }
+        }
 
       /* Look for either of these two sequences:
 
@@ -1003 +1200 @@
                  then the sequence cannot be problematic.  */
               if (i == 0)
                 {
-                  if (((set = single_set (after)) != NULL_RTX)
-                      && (MEM_P (SET_DEST (set)) || MEM_P (SET_SRC (set))))
+                  if ((set = single_set (after)) != NULL_RTX
+                      && (MEM_P (SET_DEST (set)) || mem_ref (SET_SRC (set))))
                     break;
 
                   after = next_active_insn (after);
@@ -1014 +1211 @@
 
               /* Add NOP if third instruction is a store.  */
               if (i == 1
-                  && ((set = single_set (after)) != NULL_RTX)
+                  && (set = single_set (after)) != NULL_RTX
                   && MEM_P (SET_DEST (set)))
                 insert_nop = true;
             }
         }
-      else
+
       /* Look for a single-word load into an odd-numbered FP register.  */
-      if (sparc_fix_at697f
-          && NONJUMP_INSN_P (insn)
-          && (set = single_set (insn)) != NULL_RTX
-          && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4
-          && MEM_P (SET_SRC (set))
-          && REG_P (SET_DEST (set))
-          && REGNO (SET_DEST (set)) > 31
-          && REGNO (SET_DEST (set)) % 2 != 0)
+      else if (sparc_fix_at697f
+               && NONJUMP_INSN_P (insn)
+               && (set = single_set (insn)) != NULL_RTX
+               && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4
+               && mem_ref (SET_SRC (set))
+               && REG_P (SET_DEST (set))
+               && REGNO (SET_DEST (set)) > 31
+               && REGNO (SET_DEST (set)) % 2 != 0)
         {
           /* The wrong dependency is on the enclosing double register.  */
           const unsigned int x = REGNO (SET_DEST (set)) - 1;
@@ -1095 +1292 @@
                && NONJUMP_INSN_P (insn)
                && (set = single_set (insn)) != NULL_RTX
                && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) <= 4
-               && mem_ref (SET_SRC (set)) != NULL_RTX
+               && (mem_ref (SET_SRC (set)) != NULL_RTX
+                   || INSN_CODE (insn) == CODE_FOR_movsi_pic_gotdata_op)
                && REG_P (SET_DEST (set))
                && REGNO (SET_DEST (set)) < 32)
         {
@@ -1133 +1331 @@
                                && REGNO (src) != REGNO (x)))
                        && !reg_mentioned_p (x, XEXP (dest, 0)))
                 insert_nop = true;
+
+              /* GOT accesses uses LD.  */
+              else if (INSN_CODE (next) == CODE_FOR_movsi_pic_gotdata_op
+                       && !reg_mentioned_p (x, XEXP (XEXP (src, 0), 1)))
+                insert_nop = true;
             }
         }
 
@@ -1272 +1475 @@
   /* opt_pass methods: */
   virtual bool gate (function *)
     {
-      return sparc_fix_at697f || sparc_fix_ut699 || sparc_fix_b2bst;
+      return sparc_fix_at697f || sparc_fix_ut699 || sparc_fix_b2bst
+          || sparc_fix_gr712rc || sparc_fix_ut700 || sparc_fix_lost_divsqrt;
     }
 
   virtual unsigned int execute (function *)
@@ -1642 +1846 @@
   if (!(target_flags_explicit & MASK_LRA))
     target_flags |= MASK_LRA;
 
-  /* Enable the back-to-back store errata workaround for LEON3FT.  */
+  /* Enable applicable errata workarounds for LEON3FT.  */
   if (sparc_fix_ut699 || sparc_fix_ut700 || sparc_fix_gr712rc)
+    {
     sparc_fix_b2bst = 1;
+    sparc_fix_lost_divsqrt = 1;
+    }
 
   /* Disable FsMULd for the UT699 since it doesn't work correctly.  */
   if (sparc_fix_ut699)

gcc/config/sparc/sparc.md

@@ -430 +430 @@
    (symbol_ref "(sparc_fix_b2bst != 0
                  ? FIX_B2BST_TRUE : FIX_B2BST_FALSE)"))
 
+(define_attr "fix_lost_divsqrt" "false,true"
+   (symbol_ref "(sparc_fix_lost_divsqrt != 0
+                 ? FIX_LOST_DIVSQRT_TRUE : FIX_LOST_DIVSQRT_FALSE)"))
+
+(define_attr "fix_gr712rc" "false,true"
+   (symbol_ref "(sparc_fix_gr712rc != 0
+                 ? FIX_GR712RC_TRUE : FIX_GR712RC_FALSE)"))
+
 ;; Length (in # of insns).
 ;; Beware that setting a length greater or equal to 3 for conditional branches
 ;; has a side-effect (see output_cbranch and output_v9branch).
@@ -577 +585 @@
 (define_attr "in_branch_delay" "false,true"
   (cond [(eq_attr "type" "uncond_branch,branch,cbcond,uncond_cbcond,call,sibcall,call_no_delay_slot,multi")
            (const_string "false")
+         (and (eq_attr "fix_lost_divsqrt" "true")
+              (eq_attr "type" "fpdivs,fpsqrts,fpdivd,fpsqrtd"))
+           (const_string "false")
          (and (eq_attr "fix_b2bst" "true") (eq_attr "type" "store,fpstore"))
            (const_string "false")
          (and (eq_attr "fix_ut699" "true") (eq_attr "type" "load,sload"))
@@ -590 +601 @@
            (const_string "true")
         ] (const_string "false")))
 
+(define_attr "in_integer_branch_annul_delay" "false,true"
+  (cond [(and (eq_attr "fix_gr712rc" "true")
+              (eq_attr "type" "fp,fpcmp,fpmove,fpcmove,fpmul,
+                               fpdivs,fpsqrts,fpdivd,fpsqrtd"))
+           (const_string "false")
+         (eq_attr "in_branch_delay" "true")
+           (const_string "true")
+        ] (const_string "false")))
+
 (define_delay (eq_attr "type" "call")
   [(eq_attr "in_call_delay" "true") (nil) (nil)])
 
@@ -599 +619 @@
 (define_delay (eq_attr "type" "return")
   [(eq_attr "in_return_delay" "true") (nil) (nil)])
 
-(define_delay (eq_attr "type" "branch")
+(define_delay (and (eq_attr "type" "branch")
+              (not (eq_attr "branch_type" "icc")))
   [(eq_attr "in_branch_delay" "true") (nil) (eq_attr "in_branch_delay" "true")])
 
+(define_delay (and (eq_attr "type" "branch")
+              (eq_attr "branch_type" "icc"))
+  [(eq_attr "in_branch_delay" "true") (nil)
+  (eq_attr "in_integer_branch_annul_delay" "true")])
+
 (define_delay (eq_attr "type" "uncond_branch")
   [(eq_attr "in_branch_delay" "true") (nil) (nil)])
 

gcc/config/sparc/sparc.opt

@@ -253 +253 @@
 TargetVariable
 unsigned int sparc_fix_b2bst
 
+;; Enable workaround for GRLIB-TN-0013 errata
+TargetVariable
+unsigned int sparc_fix_lost_divsqrt
+
 Mask(LONG_DOUBLE_128)
 ;; Use 128-bit long double
 

gcc/config/sparc/sync.md

@@ -212 +212 @@
   "cas<modesuffix>\t%1, %2, %0"
   [(set_attr "type" "multi")])
 
-(define_insn "*atomic_compare_and_swap_leon3_1"
+(define_insn "atomic_compare_and_swap_leon3_1"
   [(set (match_operand:SI 0 "register_operand" "=r")
         (match_operand:SI 1 "mem_noofs_operand" "+w"))
    (set (match_dup 1)
@@ -222 +222 @@
           UNSPECV_CAS))]
   "TARGET_LEON3"
 {
+  if (sparc_fix_gr712rc)
+    output_asm_insn (".align\t16", operands);
   if (TARGET_SV_MODE)
     return "casa\t%1 0xb, %2, %0"; /* ASI for supervisor data space.  */
   else
     return "casa\t%1 0xa, %2, %0"; /* ASI for user data space.  */
 }
-  [(set_attr "type" "multi")])
+  [(set_attr "type" "multi")
+   (set (attr "length") (if_then_else (eq_attr "fix_gr712rc" "true")
+                      (const_int 4) (const_int 1)))])
 
 (define_insn "*atomic_compare_and_swapdi_v8plus"
   [(set (match_operand:DI 0 "register_operand" "=h")
@@ -275 +279 @@
    (set (match_dup 1)
         (match_operand:SI 2 "register_operand" "0"))]
   "(TARGET_V8 || TARGET_V9) && !sparc_fix_ut699"
-  "swap\t%1, %0"
-  [(set_attr "type" "multi")])
+{
+  if (sparc_fix_gr712rc)
+    return ".align\t16\n\tswap\t%1, %0";
+  else
+    return "swap\t%1, %0";
+}
+  [(set_attr "type" "multi")
+   (set (attr "length") (if_then_else (eq_attr "fix_gr712rc" "true")
+                      (const_int 4) (const_int 1)))])
 
 (define_expand "atomic_test_and_set"
   [(match_operand:QI 0 "register_operand" "")
@@ -307 +318 @@
                             UNSPECV_LDSTUB))
    (set (match_dup 1) (const_int -1))]
   "!sparc_fix_ut699"
-  "ldstub\t%1, %0"
-  [(set_attr "type" "multi")])
+{
+  if (sparc_fix_gr712rc)
+    return ".align\t16\n\tldstub\t%1, %0";
+  else
+    return "ldstub\t%1, %0";
+}
+  [(set_attr "type" "multi")
+   (set (attr "length") (if_then_else (eq_attr "fix_gr712rc" "true")
+                      (const_int 4) (const_int 1)))])